MAXIM DS8500

Rev 0; 10/08
HART Modem
The DS8500 is a single-chip modem with Highway
Addressable Remote Transducer (HART) capabilities
and satisfies the HART physical layer requirements.
The device integrates the modulation and demodulation
of the 1200Hz/2200Hz FSK signal, has very low power
consumption, and needs only a few external components due to the integrated digital signal processing.
The input signal is sampled by an analog-to-digital converter (ADC), followed by a digital filter/demodulator.
This architecture ensures reliable signal detection in
noisy environments. The output digital-to-analog converter (DAC) generates a sine wave and provides a
clean signal with phase-continuous switching between
1200Hz and 2200Hz. Low power is achieved by disabling the receive circuits during transmit and vice
versa. The DS8500 is ideal for low-power process control transmitters.
Applications
4–20mA Loop-Powered Transmitters for
Temperature, Pressure, Flow, and Level
Measurement
HART Multiplexers
Features
♦ Single-Chip, Half-Duplex, 1200bps FSK
Modulation and Demodulation
♦ Digital Signal Processing Provides Reliable Input
Signal Detection in Noisy Conditions
♦ Sinusoidal Output Signal with Lowest Harmonic
Distortion
♦ Few External Components Enable a Space-Saving
Solution
♦ Standard Component 3.6864MHz Crystal
♦ Complies to HART Physical Layer Requirements
♦ 2.7V to 3.6V Operating Voltage
♦ 285µA (max) Current Consumption
♦ Space-Saving, 5mm x 5mm x 0.8mm, 20-Pin TQFN
Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS8500-JND+
-40°C to +85°C
20 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
HART Modem Interface Connectivity
FSK_IN
REF
FSK_OUT
AVDD
TOP VIEW
AGND
Pin Configuration
15
14
13
12
11
DGND 16
10
XCEN
DGND 17
9
DGND
8
XTAL2
7
XTAL1
6
RTS
DGND 18
DS8500
D_OUT 19
*EXPOSED PAD.
2
3
4
5
RST
OCD
DVDD
1
DGND
+
DVDD
D_IN 20
*EP
THIN QFN
(5mm × 5mm)
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS8500
General Description
DS8500
HART Modem
ABSOLUTE MAXIMUM RATINGS
Voltage Range on All Pins (including AVDD,
DVDD) Relative to Ground .................................-0.5V to +3.6V
Voltage Range on Any Pin Relative to
Ground Except AVDD, DVDD .............-0.5V to (VDVDD + 0.5V)
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VDVDD = VAVDD = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Supply Voltage
VDVDD
2.7
3.6
V
Analog Supply Voltage
VAVDD
VAVDD = VDVDD
2.7
3.6
V
Ground
GND
AGND = DGND
0
0
V
Digital Power-Fail Reset Voltage
VRST
Monitors VDVDD
2.59
2.69
V
285
μA
DGND
0.30 x
VDVDD
V
0.75 x
VDVDD
VDVDD
V
I OL = 4mA
DGND
0.4
V
VOH
I OH = -4mA
0.8 x
VDVDD
CIO
Guaranteed by design (Note 3)
Active Current
IDD
Input Low Voltage
VIL
Input High Voltage
VIL
Output Low Voltage
VOL
Output High Voltage
I/O Pin Capacitance
2.64
VAVDD = VDVDD = 2.7V (Note 2)
V
15
pF
RST Pullup Resistance
RRST
19
45
k
Input Leakage Current XTAL,
RST
I ILRX
-30
+30
μA
Input Leakage Current All Other
Pins
I IL
-2
+2
μA
Input Low Current for RST
I IL1
170
μA
+1%
MHz
VIN = 0.4V
CLOCK SOURCE
External Clock Frequency
fHFIN
-1%
3.6864
VOLTAGE REFERENCE
Internal Reference Voltage
VREF
1.23
V
FSK INPUT
Input Voltage Range at FSK_IN
0
VREF
V
600
mVP-P
FSK OUTPUT
Output Voltage at FSK_OUT
Frequency of FSK_OUT (Note 4)
Note 1:
Note 2:
Note 3:
Note 4:
2
VOUT
AC-coupled max 30k load
400
500
For a mark
-1%
1200
+1%
For a space
-1%
2200
+1%
Specifications to -40°C are guaranteed by design and are not production tested.
Active currents are measured when the device is driven by an external clock XCEN = 1 condition.
Guaranteed by design and not production tested.
Accuracy is guaranteed based on the external crystal or clock provided.
_______________________________________________________________________________________
kHz
HART Modem
PIN
NAME
1, 2
DVDD
Digital Supply Voltage
FUNCTION
3, 9, 16,
17, 18
DGND
Digital Ground
4
RST
Active-Low Reset, Digital Input/Output. This pin includes an internal pullup resistor and is driven low
as an output when an internal reset condition occurs.
5
OCD
Carrier Detect, Digital Output. A logic-high indicates a valid carrier detection on FSK_IN.
OCD = 1 when FSK_IN amplitude is greater than 120mVP-P.
OCD = 0 when FSK_IN amplitude is less than 80mVP-P.
6
RTS
Request to Send, Digital Input. When set high, the device is put into the demodulator mode. A logic-low
puts the device into modulator mode.
7
XTAL1
Crystal Pin or Input for External Clock at 3.6864MHz
8
XTAL2
Crystal Pin or Output of the Crystal Amplifier
10
XCEN
External Clock Enable, Digital Input. When set high, this pin allows the user to drive an external clock
signal through XTAL1. When in this mode, XTAL2 should be left unconnected. An external crystal must
be connected between XTAL1 and XTAL2 when set low.
11
AVDD
Analog Supply Voltage
12
FSK_OUT
13
REF
14
FSK_IN
FSK In, Analog Input. Input for the FSK-modulated HART receive signal from the 4mA to 20mA current
loop interface circuit.
15
AGND
Analog Ground
19
D_OUT
20
D_IN
FSK Out, Analog Output. Output of the modulator. Provides a phase-continuous, FSK-modulated output
signal (1200Hz and 2200Hz output frequencies) to the 4mA to 20mA current loop interface circuit.
Reference, Analog Output. The internal voltage reference is provided as output. This pin must be
connected to a 0.1μF capacitor.
Digital Data Out, Digital Output. Output from the demodulator.
Digital Data In, Digital Input. Input to the modulator.
Block Diagram
XTAL1
XTAL2
CRYSTAL
OSCILLATOR
RST
DVDD DGND
CLOCK
GENERATOR
POWER
MONITOR
AGND
AVDD
VREF
1.23V
REF
XCEN
OCD
D_OUT
RTS
D_IN
Rx
DEMODULATOR
DIGITAL
FILTER
Tx
MODULATOR
SAMPLE/HOLD
ADC
DAC
FSK_IN
FSK_OUT
DS8500
_______________________________________________________________________________________
3
DS8500
Pin Description
DS8500
HART Modem
Introduction to HART
HART is a backward-compatible enhancement to existing 4mA to 20mA instrumentation networks that allows
two-way, half-duplex, digital communication with a
microcontroller-based field device. The digital signal is
encoded on top of the existing instrumentation signal.
Communication is accomplished through a series of
commands and responses dependent on the specific
protocol and network topology. The DS8500 does not
implement any portion of the communication protocol; it
only handles the modulation and demodulation of the
encoded information. Digital data is encoded using frequency-shift keying (FSK), which is illustrated in Figure
1. A “1” is identified as a mark symbol and is represented with a center frequency of 1.2kHz. A “0” is identified
as a space symbol and is represented with a center frequency of 2.2kHz. This allows a throughput of 1.2kbps,
with each symbol occupying an 833µs slot.
V
The input HART signal’s noise interference is attenuated by a one-pole highpass filter that is external to the
chip; the attenuated signal is digitized by the ADC and
filtered by the receive state machine. The transmit state
machine modulates the input to the HART-compliant
signal with the help of the modulator and the DAC.
Modulator
The modulator performs the FSK modulation of the digital data at the D_IN input. The FSK-modulated sinusoidal signal is present at the FSK_OUT output as
illustrated in Figure 1. The modulator is enabled by RTS
being a logic-low. The modulation is done between
1200Hz (mark) or 2200Hz (space) depending on the
logic level of the input signal. The modulator preserves a
continuous phase when switching between frequencies
to minimize the bandwidth of the transmitted signal.
Figure 2 illustrates an example waveform of the DS8500
in modulate mode. The data to be modulated is presented in a UART format (start, 8 data bits, parity, stop
bit) at D_IN. FSK_OUT shows the modulated output.
Demodulator
T
The demodulator accepts an FSK signal at the FSK_IN
input and reproduces the original modulating signal at
the D_OUT output. The HART signal should be presented as an 11-bit UART character with a start, data, parity, and stop bits for proper operation of the
demodulator block. The nominal bit rate of the D_OUT
signal is 1200 bits per second. A simple RC filter is sufficient for anti-aliasing. Figure 3 illustrates an example
waveform of the DS8500 in demodulate mode.
Applications Information
1.2kHz MARK
"1"
2.2kHz SPACE
"0"
Figure 1. HART FSK Signal
Functional Description
The DS8500 modem chip consists of a demodulator, carrier detect, digital filter, ADC for input signal conversion, a
modulator and DAC for output signal generation, and
receive and transmit state machine blocks to perform the
HART communication. The Block Diagram illustrates
the interface between various blocks of circuitry.
4
Figure 4 shows the typical application circuit. As the
DS8500 integrates a digital filter, only a simple passive
RC filter is required in front of the ADC. R3 and C3
implement a lowpass filter with a 10kHz cutoff frequency; C2 and R2/R1 implement a highpass filter with a
480Hz cutoff frequency. The resistor-divider formed by
R1 and R2 provides an input bias voltage of VREF/2 to
the ADC input (R1 = R2).
The output DAC provides a sine-wave signal, and C4
provides the AC-coupled signal output from the
DS8500. The typical value of C4 can be anything
greater than 20nF based on the application.
_______________________________________________________________________________________
HART Modem
DS8500
1200bps/833μs
D_IN
STOP
START
8-BIT DATA
PARITY
FSK_OUT
Figure 2. Actual DS8500 Modulator Waveform
FSK_IN
START
8-BIT DATA
STOP
PARITY
D_OUT
1200bps/833μs
ONE UART CHARACTER (START, 8 DATA BITS, PARITY, STOP)
Figure 3. Actual DS8500 Demodulator Waveform
_______________________________________________________________________________________
5
DS8500
HART Modem
POWER SUPPLY
2.7V TO 3.6V
3.6864MHz
RST
DVDD
DGND
AGND
AVDD
XTAL1
3.6864MHz
CRYSTAL
CRYSTAL
OSCILLATOR
CLOCK
GENERATOR
VREF
1.23V
POWER
MONITOR
REF
XTAL2
C1
XCEN
R1
OCD
Rx
DEMODULATOR
D_OUT
DIGITAL
FILTER
SAMPLE/HOLD
ADC
C2
FSK_IN
R3
HART IN
C3
R2
DS8500
C4
RTS
Tx
MODULATOR
D_IN
DAC
HART AND
4mA TO 20mA
OUT
FSK_OUT
MICROCONTROLLER
4mA TO 20mA
DAC OUTPUT
Figure 4. Typical Application Circuit
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
20 TQFN
T2055+3
21-0140
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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