SMD Passive Delay Line EPA3192 PCA Part Number : Package Electrical Specifications 100 Ω ± 10% Impedance 4 1 28 26 2.6 nS Max. TR Output TR True PCA EPA3192 D.C. ----12 Tap Delay 1.3 nS ± 1 nS Delay Time 13.0 nS ± 5% .360 18 .440 .165 Attenuation 0.8% Ref. Distortion ± 10.0% Max. D.C. Resistance 0.86 Ω Ref. I.R. 1 KM Ω Min. @ 100 Vdc .050 .050 Schematic 27 28 1 2 3 4 13 14 15 16 Input Dielectric Strength .018 X .008 Tin plated Kovar 17 Output 100 Vdc Gnd 26 Temp. Coef. of Delay 100 PPM / °C Operating Temp. 0 to 70°C Pin # 12 N.C. Gnd 18 Notes : Test Conditions @ 25°C Pw 39.0 nS Vcc Prr 1.0 MHz Temp Ein 1.2 V Load Tri 2.0 nS Tfi *Unless otherwise specified, all tests to be conducted @ 25°C and RH of 93% Max. DSA3192 Rev. - 10/31/95 Unless Otherwise Noted Dimensions in Inches Tolerances: Fractional = ± 1/32 .XX = ± .030 .XXX = ± .010 QAF-CSO1a Rev. - ELECTRONICS INC. 7/27/95 16799 SCHOENBORN ST. NORTH HILLS, CA 91343 TEL: (818) 892-0761 FAX: (818) 894-5791