SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM 64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant) Revision 1.3 August 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Revision History Revision 1.0 (September, 2003) • Finalized Revision 1.1 (October, 2003) Deleted speed -7C and AC parameter notes 5. Revision 1.2 (May, 2004) • Added Note 5. sentense of tRDL parameter Revision 1.3 (August, 2004) • Corrected typo. Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM 4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Burst read single-bit write operation • DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh • 64ms refresh period (4K cycle) • Pb-free Package • RoHS compliant GENERAL DESCRIPTION The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Ordering Information Part No. Orgainization Max Freq. K4S640432H-UC(L)75 16Mb x 4 133MHz(CL=3) K4S640832H-UC(L)75 8Mb x 8 133MHz(CL=3) K4S641632H-UC(L)60 166MHz(CL=3) 4Mb x 16 K4S641632H-UC(L)70 K4S641632H-UC(L)75 Interface Package LVTTL 54pin TSOP(II) 143MHz(CL=3) 133MHz(CL=3) Organization Row Address Column Address 16Mx4 A0~A11 A0-A9 8Mx8 A0~A11 A0-A8 4Mx16 A0~A11 A0-A7 Row & Column address configuration Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Package Physical Dimension 0~8°C #1 #27 10.16 0.400 0.125+0.075 -0.035 0.005+0.003 -0.001 22.62 MAX 0.891 22.22 0.875 0.10 MAX 0.004 ( 0.71 ) 0.028 +0.10 0.30 -0.05 0.012 +0.004 -0.002 ± 0.10 0.21 0.008 ± 0.004 ± 0.05 ± 0.002 1.00 0.039 0.80 0.0315 ± 0.10 ± 0.004 ( 0.50 ) 0.020 #28 11.76±0.20 0.463±0.008 #54 0.45~0.75 0.018~0.030 0.25 TYP 0.010 1.20 MAX 0.047 0.05 MIN 0.002 54Pin TSOP(II) Package Dimension Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 4M x 4 / 2M x 8 / 1M x 16 4M x 4 / 2M x 8 / 1M x 16 Output Buffer 4M x 4 / 2M x 8 / 1M x 16 Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 4M x 4 / 2M x 8 / 1M x 16 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LDQM LWCBR Timing Register CLK CKE CS RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM PIN CONFIGURATION (Top view) x8 x4 x16 VDD VDD VDD DQ0 DQ0 N.C VDDQ VDDQ VDDQ DQ1 N.C N.C DQ2 DQ1 DQ0 VSSQ VSSQ VSSQ DQ3 N.C N.C DQ4 DQ2 N.C VDDQ VDDQ VDDQ DQ5 N.C N.C DQ6 DQ3 DQ1 VSSQ VSSQ VSSQ DQ7 N.C N.C VDD VDD VDD LDQM N.C N.C WE WE WE CAS CAS CAS RAS RAS RAS CS CS CS BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 x4 x8 VSS N.C VSSQ N.C DQ3 VDDQ N.C N.C VSSQ N.C DQ2 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : (x4 : CA0 ~ CA9, x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7) BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. DQ0 ~ X15 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No connection /reserved for future use This pin is recommended to be left No Connection on the device. Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Symbol Min Max Unit Note CCLK 2.5 4.0 pF 1 Clock RAS, CAS, WE, CS, CKE, DQM CIN 2.5 5.0 pF 2 Address CADD 2.5 5.0 pF 2 DQ0 ~ DQ3 COUT 4.0 6.5 pF 3 Notes : 1. -75 only specify a maximum value of 3.5pF 2. -75 only specify a maximum value of 3.8pF 3. -75 only specify a maximum value of 6.0pF Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x4, x8) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Version Test Condition 75 Unit Note 1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 75 mA CKE ≤ VIL(max), tCC = 10ns 1 mA CKE & CLK ≤ VIL(max), tCC = ∞ 1 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 15 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 6 CKE ≤ VIL(max), tCC = 10ns 3 CKE & CLK ≤ VIL(max), tCC = ∞ 3 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 30 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 25 mA mA mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs 115 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 135 mA 2 Self refresh current ICC6 CKE ≤ 0.2V C 1 mA 3 L 400 uA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S6404(08)32H-TC** 4. K4S6404(08)32H-TL** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ) Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x16 only) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Version Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 60 70 75 140 115 110 CKE ≤ VIL(max), tCC = 10ns 1 CKE & CLK ≤ VIL(max), tCC = ∞ 1 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 15 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 6 CKE ≤ VIL(max), tCC = 10ns 3 CKE & CLK ≤ VIL(max), tCC = ∞ 3 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 30 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 25 Unit Note mA 1 mA mA mA mA ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs 160 140 135 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 160 140 135 mA 2 Self refresh current ICC6 CKE ≤ 0.2V Operating current (Burst mode) C 1 mA 3 L 400 uA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S641632H-TC** 4. K4S641632H-TL** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ) Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output 870Ω Output Z0 = 50Ω 30pF 30pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Version Parameter Symbol 60 70 75 Unit Note Row active to row active delay tRRD(min) 12 14 15 ns 1 RAS to CAS delay tRCD(min) 18 20 20 ns 1 tRP(min) 18 20 20 ns 1 tRAS(min) 42 49 45 ns 1 Row precharge time Row active time tRAS(max) 100 Row cycle time tRC(min) Last data in to row precharge tRDL(min) 60 68 2 us 65 ns 1 CLK 2,5 Last data in to Active delay tDAL(min) 2 CLK + tRP - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 tCCD(min) 1 CLK 3 ea 4 Col. address to col. address delay Number of valid output data CAS latency = 3 2 CAS latency = 2 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter 60 Symbol Min CLK cycle time CAS latency=3 tCC CAS latency=2 CLK to valid output delay CAS latency=3 Output data hold time CAS latency=3 6 70 Max 1000 tSAC CAS latency=2 tOH CAS latency=2 Min 75 Max 7 1000 - Min 7.5 Unit Note ns 1 ns 1,2 ns 2 Max 1000 10 5 6 5.4 - - 6 2.5 3 3 - - 3 CLK high pulse width tCH 2.5 3 2.5 ns 3 CLK low pulse width tCL 2.5 3 2.5 ns 3 Input setup time tSS 1.5 2 1.5 ns 3 Input hold time tSH 1 1 0.8 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 tSHZ CAS latency=2 5 6 5.4 - - 6 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. DQ BUFFER OUTPUT DRIVE CHARACTERISTICS Parameter Symbol Condition Min Output rise time trh Measure in linear region : 1.2V ~ 1.8V Output fall time tfh Output rise time Output fall time Typ Max Unit Notes 1.37 4.37 Volts/ns 3 Measure in linear region : 1.2V ~ 1.8V 1.30 3.8 Volts/ns 3 trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6 Volts/ns 1,2 tfh Measure in linear region : 1.2V ~ 1.8V 2.0 2.9 5.0 Volts/ns 1,2 Notes : 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS. Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM IBIS SPECIFICATION 133MHz Pull-up 0 IOH Characteristics (Pull-up) (V) 3.45 3.30 3.00 2.70 2.50 1.95 1.80 1.65 1.50 1.40 1.00 0.20 133MHz Max I (mA) -1.68 -19.11 -51.87 -90.44 -107.31 -137.9 -158.34 -173.6 -188.79 -199.01 -241.15 -351.68 0.5 1 1.5 2 2.5 3 3.5 3 3.5 0 -100 -200 mA Voltage 133MHz Min I (mA) -0.35 -3.75 -6.65 -13.75 -17.75 -20.55 -23.55 -26.2 -36.25 -46.5 -300 -400 -500 -600 Voltage IOH Min (133MHz) IOH Max (133MHz) 133MHz Pull-down IOL Characteristics (Pull-down) (V) 3.45 3.30 3.00 1.95 1.80 1.65 1.50 1.40 1.00 0.85 0.65 0.40 133MHz Min I (mA) 43.92 43.36 41.20 40.56 39.60 38.40 37.28 30.08 26.64 21.52 14.16 133MHz Max I (mA) 155.82 153.72 148.40 146.02 141.75 136.08 131.39 105.84 93.66 75.25 49.14 250 200 150 mA Voltage 100 50 0 0 0.5 1 1.5 2 2.5 Voltage IOL Min (133MHz) IOL Max (133MHz) Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Minimum VDD clamp current (Referenced to VDD) VDD Clamp @ CLK, CKE, CS, DQM & DQ I (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31 20 15 mA VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 10 5 0 0 1 2 3 Voltage I (mA) Minimum VSS clamp current VSS Clamp @ CLK, CKE, CS, DQM & DQ I (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.0 -3 -2 -1 0 0 -10 -20 mA VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 -30 -40 -50 -60 Voltage I (mA) Rev. 1.3 August 2004 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM SIMPLIFIED TRUTH TABLE Command Register CKEn-1 Mode register set Auto refresh Refresh Entry Self refresh (V=Valid, X=Don′t care, H=Logic high, L=Logic low) H H CKEn CS RAS CAS WE DQM X L L L L X OP code L L L H X X X X H L L H H H H X X X X L L H H X V H X L H L H X V H X L H L L X V H X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X Entry H L Exit L H L H Bank active & row addr. H Read & column address Write & column address Exit Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable Burst stop Precharge Bank selection All banks Clock suspend or active power down Precharge power down mode DQM No operation command BA0,1 H X X X L H H H H X X X V V V L H H X X H X X X L H H H X A10/AP A11, A9 ~ A0 Note 1,2 3 3 3 3 Row address L Column address H L Column address H X V L X H 4 4,5 4 4,5 6 X X X X X X V X X X 7 Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 1.3 August 2004