ATMEL AT24C256C-SSHL-T

Features
• Low-voltage and Standard-voltage Operation
⎯ VCC = 1.7V to 5.5V
• Internally Organized as 32,768 x 8
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
Two-wire
Serial EEPROM
• 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.7V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 64-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
256K (32,768 x 8)
• High Reliability
⎯ Endurance: One Million Write Cycles
⎯ Data Retention: 40 Years
AT24C256C
• Lead-free/Halogen-free Devices Available
• 8-lead JEDEC SOIC, 8-lead UDFN, 8-lead TSSOP, and 8-ball VFBGA Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Preliminary
Description
The AT24C256C provides 262,144 bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits
each. The device’s cascadable feature allows up to eight devices to share a common
two-wire bus. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The devices
are available in space-saving 8-lead JEDEC SOIC, 8-lead UDFN, 8-lead TSSOP, and
8-ball VFBGA packages. In addition, this device operates from 1.7V to 5.5V.
Table 1.
Pin Name
A0 – A2
SDA
Pin Configurations
Function
Address Inputs
Serial Data
SCL
Serial Clock Input
WP
Write Protect
GND
Ground
8-lead SOIC
8-lead TSSOP
A0
A1
A2
GND
1
8
2
7
3
6
4
5
VCC
WP
SCL
SDA
8-ball VFBGA
A0
2 A1
VCC 8
WP 7
1
SCL 6
SDA 5
3
A2
4 GND
Bottom View
A0
A1
1
8
2
7
A2
GND
3
6
4
5
VCC
WP
SCL
SDA
8-lead UDFN
VCC
WP
SCL
SDA
8
1 A0
7
2 A1
6
3 A2
5
4 GND
Bottom View
8568A–SEEPR–9/09
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions beyond those indicated in
the operational sections of this specification are
not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
Operating Temperature ........................... • 55°C to +125°C
Storage Temperature ............................ • 65°C to + 150°C
Voltage on Any Pin
with Respect to Ground................................ • 1.0 V +7.0V
Maximum Operating Voltage..................................... 6.25V
DC Output Current .................................................. 5.0 mA
Figure 1.
Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SERIAL
CONTROL
LOGIC
LOAD
DEVICE
ADDRESS
COMPARATOR
A2
A1
A0
R/W
EN
H.V. PUMP/TIMING
COMP
LOAD
DATA RECOVERY
INC
DATA WORD
ADDR/COUNTER
Y DEC
X DEC
SCL
SDA
EEPROM
SERIAL MUX
DOUT/ACK
LOGIC
DIN
DOUT
2
AT24C256C [Preliminary]
8568A–SEEPR–9/09
AT24C256C [Preliminary]
1.
Pin Descriptions
SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and
negative-edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be
wire-ORed with any number of other open-drain or open-collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired
(directly to GND or to VCC) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight
256K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device
Addressing”_Device_Addressing) A device is selected when a corresponding hardware and software match is
true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to
capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address
pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP
is connected directly to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be
internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications,
Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel
recommends using 10kΩ or less.
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8568A–SEEPR–9/09
2.
Memory Organization
AT24C256C, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64 bytes each. Random word
addressing requires a 15-bit data word address.
(1)
Table 2.
Pin Capacitance
Applicable over recommended operating range from:
TA = 25°C, f = 1.0 MHz, VCC = +1.7V
Symbol
Test Condition
Max
Units
Conditions
CI/O
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN
Input Capacitance (A0, A1, SCL)
6
pF
VIN = 0V
Note:
1. This parameter is characterized and is not 100% tested.
Table 3.
DC Characteristics
Applicable over recommended operating range from:
TAI = − 40°C to +85°C, VCC = +1.7V to +5.5V (unless otherwise noted)
Symbol
Test Condition
Min
Typ
1.7
Max
Units
5.5
V
VCC1
Supply Voltage
ICC1
Supply Current
VCC = 5.0V
READ at 400 kHz
1.0
2.0
mA
ICC2
Supply Current
VCC = 5.0V
WRITE at 400 kHz
2.0
3.0
mA
Standby Current
(1.7V option)
VCC = 1.7V
1.0
μA
ISB1
6.0
μA
ILI
Input Leakage
Currentt VCC = 5.0V
VIN = VCC or VSS
0.10
3.0
μA
ILO
Output Leakage
Currentt VCC = 5.0V
VOUT = VCC or VSS
0.05
3.0
μA
VIL
Input Low Level
-0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
VCC = 5.0V
VIN = VCC or VSS
(1)
(1)
VIH
Input High Level
VOL2
Output Low Level
VCC = 3.0V
IOL = 2.1 mA
0.4
V
VOL1
Output Low Level
VCC = 1.7V
IOL = 0.15 mA
0.2
V
Note:
4
Parameter
1. VIL min and VIH max are reference only and are not tested.
AT24C256C [Preliminary]
8568A–SEEPR–9/09
AT24C256C [Preliminary]
Table 4.
AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from:
TAI = − 40°C to +85°C, VCC = +1.7V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.
1.7-volt
Symbol
2.5, 5.0-volt
Parameter
Units
Min
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
tHIGH
Clock Pulse Width High
Max
Min
400
Noise Suppression Time
tAA
Clock Low to Data Out Valid
1000
kHz
1.3
0.4
μs
0.6
0.4
μs
(1)
tI
Max
100
0.05
0.9
0.05
50
ns
0.55
μs
1.3
0.5
μs
Start Hold Time
0.6
0.25
μs
tSU.STA
Start Set-up Time
0.6
0.25
μs
tHD.DAT
Data In Hold Time
0
0
μs
tSU.DAT
Data In Set-up Time
100
100
ns
tBUF
Time the bus must be free before a new transmission can start
tHD.STA
tR
Inputs Rise Time
(1)
(1)
(1)
0.3
0.3
μs
300
100
ns
tF
Inputs Fall Time
tSU.STO
Stop Set-up Time
0.6
0.25
μs
tDH
Data Out Hold Time
50
50
ns
tWR
Write Cycle Time
5
25°C, Page Mode, 3.3V
1,000,000
Endurance
Note:
(1)
5
ms
Write
Cycles
1. This parameter is ensured by characterization and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5.5V), 10 kΩ (1.7V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 VCC
5
8568A–SEEPR–9/09
3.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (refer to Figure 2). Data changes during SCL high periods will indicate a
start or stop condition as defined below.
Figure 2.
Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other
command (refer to Figure 3).
Figure 3.
Start and Stop Definition
SDA
SCL
START
STOP
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (refer to Figure 3).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a “0” during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The AT24C256C features a low-power standby mode that is enabled upon power-up and after the
receipt of the stop bit and the completion of any internal operations.
6
AT24C256C [Preliminary]
8568A–SEEPR–9/09
AT24C256C [Preliminary]
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset
by following these steps:
a) Create a start bit condition,
b) Clock 9 cycles,
c) Create another start bit followed by stop bit condition as shown below.
The device is ready for next communication after above steps has been completed.
Figure 4.
Software Reset
Dummy Clock Cycles
Start bit
SCL
1
2
3
Start bit
8
Stop bit
9
SDA
Figure 5.
Bus Timing
tHIGH
tF
tR
tLOW
SCL
tSU.STA
tLOW
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 6.
Write Cycle Timing
SCL
SDA
8th BIT
ACK
WORDn
(1)
twr
STOP
CONDITION
START
CONDITION
7
8568A–SEEPR–9/09
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the
internal clear/write cycle.
Figure 7.
Output Acknowledge
1
SCL
8
9
DATA IN
DATA OUT
START
8
ACKNOWLEDGE
AT24C256C [Preliminary]
8568A–SEEPR–9/09
AT24C256C [Preliminary]
4.
Device Addressing
The 256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or
write operation (refer to Figure 8). The device address word consists of a mandatory “1”, “0” sequence for the first four
most significant bits as shown. This is common to all two-wire EEPROM devices.
Figure 8.
1
MSB
Device Addressing
0
1
0
A2
A1
A0
R/W
LSB
The next three bits are the A2, A1, A0 device address bits to allow as many as eight devices on the same bus. These
bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary
circuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high,
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the device will return
to a standby state.
DATA SECURITY: The AT24C256C has a hardware data protection scheme that allows the user to write protect the
whole memory when the WP pin is at VCC.
9
8568A–SEEPR–9/09
5.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first
8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as
a microcontroller, must then terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the
EEPROM will not respond until the write is complete (refer to Figure 9).
Figure 9.
Note:
Byte Write
* = DON’T CARE bit
PAGE WRITE: The 256K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller
can transmit up to 63 more data words. The EEPROM will respond with a “0” after each data word received. The
microcontroller must terminate the page write sequence with a stop condition (refer to Figure 10).
Figure 10.
Note:
Page Write
* = DON’T CARE bit
The data word address lower six bits are internally incremented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the memory page row location. When the word address,
internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If
more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will
be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same
page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a “0”, allowing the read or write sequence to continue.
10
AT24C256C [Preliminary]
8568A–SEEPR–9/09
AT24C256C [Preliminary]
6.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to “1”. There are three read operations: current address read, random address read, and
sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the
last read or write operation, incremented by one. This address stays valid between operations as long as the chip
power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte
of the first page.
Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does
generate a following stop condition (refer to Figure 11).
Figure 11.
Current Address Read
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller
must generate another start condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller does not respond with a “0” but does generate a following stop condition. (Refer to
Figure 12)
Figure 12.
Note:
Random Read
* = DON’T CARE bit
11
8568A–SEEPR–9/09
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After
the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When
the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a
following stop condition (refer to Figure 13).
Figure 13.
12
Sequential Read
AT24C256C [Preliminary]
8568A–SEEPR–9/09
AT24C256C [Preliminary]
7.
Ordering Information
7.1.
Ordering Code Detail
AT24C 256C -S S H L-B
Shipping Carrier Option
Atmel Designator
B or blank = Bulk (tubes)
T = Tape and reel
Product Family
Operating Voltage
L
= 1.7V to 5.5V
Package Device Grade or
Wafer/Die Thickness
Device Density
256 = 256K
H
= Green, NiPdAu lead finish,
Industrial Temperature Range
(-40°C to +85°C)
U = Green, matte Sn lead finish,
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil wafer thickness
Device Revision
Package Option
SS = JEDEC SOIC
X = TSSOP
MA = UDFN
W = wafer
WT = die in tape and reel
C = UFBGA
7.2.
AT24C256C Ordering Codes
Ordering Code
(1)
AT24C256C-SSHL-B
(2)
AT24C256C-SSHL-T
(1)
AT24C256C-XHL-B
(2)
AT24C256C-XHL-T
(2)
AT24C256C-MAHL-T
(2)
AT24C256C-CUL-T
(3)
AT24C256C-W11
Note:
Voltage
Package
Operating Range
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
8S1
8S1
8A2
8A2
8MA2
8U2-1
Lead-free/Halogen-free
Industrial Temperature (−40°C to 85°C)
1.7V to 5.5V
Die Sale
Industrial Temperature (−40°C to 85°C)
1. “-B” denotes bulk.
2. “-T” denotes tape & reel. SOIC = 4K per reel. TSSOP, VFBGA and UDFN = 5K per reel.
3. Bumped die available upon request. Contact Atmel Marketing.
Package Type
8S1
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8A2
8-lead, 4.40mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8MA2
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)
8U2-1
8-ball, die Ball Grid Array Package (VFBGA)
13
8568A–SEEPR–9/09
8.
Part Marketing Scheme
AT24C256C-SSHL
Top Mark
--A
--2
*
---
Seal Year
Seal Week
--- --- --T
M
L
--- --- --E
C
Lot Number
--- --- ---
--- --- --- --H
Y
W
W
--- --- --- --1
--- --- --- ---
Y =
6:
7:
8:
9:
SEAL YEAR
2006
0:
2007
1:
2008
2:
2009
3:
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
52 = Week 52
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
1
2010
2011
2012
2013
Pin 1 Indicator (Dot)
No Bottom Mark
AT24C256C-XHL
Top Mark
Pin 1 Indicator (Dot)
--- --- --- --*
H
Y
W
W
--- --- --- --- --2
E
C
1
--- --- --- --- ---
Bottom Mark
--- --- --- --- --- --- --X
X
--- --- --- --- --- --- --A
A
A
A
A
A
A
<- Pin 1 Indicator
Y =
6:
7:
8:
9:
SEAL YEAR
2006
0:
2007
1:
2008
2:
2009
3:
2010
2011
2012
2013
WW
02
04
::
::
50
52
=
=
=
:
:
=
=
SEAL
Week
Week
::::
::::
Week
Week
WEEK
2
4
:
::
50
52
WW
02
04
::
::
50
52
=
=
=
:
:
=
=
SEAL
Week
Week
::::
::::
Week
Week
WEEK
2
4
:
::
50
52
XX = Country of Origin
AT24C256C-MAHL
Seal Year
Top Mark
--- --- --A
T
M
--- --- --2
E
C
Lot Number
--- --- --*
Seal Year
Seal Week
--- --- --- --- --L
H
Y
W
W
--- --- --- --- --1
Y =
6:
7:
8:
9:
SEAL YEAR
2006
0:
2007
1:
2008
2:
2009
3:
2010
2011
2012
2013
--- --- --- --- ---
Pin 1 Indicator (Dot)
14
AT24C256C [Preliminary]
8568A–SEEPR–9/09
AT24C256C [Preliminary]
AT24C256C-CUL
Top Mark
Line 1 ----------->
Line 2 ----------->
2ECU
YMTC
<---
Pin 1 This Corner
Y = ONE DIGIT YEAR CODE
4: 2004
7: 2007
5: 2005
8: 2008
6: 2006
9: 2009
5
M =
A
B
"
J
K
L
SEAL MONTH (USE ALPHA DESIGNATOR A-L)
= JANUARY
= FEBRUARY
" """""""
= OCTOBER
= NOVEMBER
= DECEMBER
TC = TRACE CODE
15
8568A–SEEPR–9/09
9.
Packaging Information
8S1 – JEDEC SOIC
Figure 1.
8S1 – JEDECSOIC
C
1
E
E1
N
L
Top View
End View
e
COMMON DIMENSIONS
(Unit of Measure = mm)
B
A
SYMBOL
A1
D
MIN
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.00
E1
3.81
–
3.99
E
5.79
–
6.20
e
Side View
NOM
L
NOTE
1.27 BSC
0.40
–
1.27
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions,
tolerances, datums, etc.
10/07/03
R
16
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
REV.
8S1
B
AT24C256C [Preliminary]
8568A–SEEPR–9/09
AT24C256C [Preliminary]
8A2 – TSSOP
Figure 14.
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
L
N
End View
Top View
SYMBOL
A
b
D
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
4.50
3, 5
E
E1
e
D
Side View
A2
6.40 BSC
4.30
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
L
4
0.65 BSC
0.45
L1
Notes:
4.40
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC D rawing MO-153, Variation AA, for proper dimension s,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, prot rusions or gate burrs. Mold Flash, prot rusions and gate burrs shall not
exceed 0.15 mm (0.006 in) per sid e.
3. Dimension E1 does not include inter-lead Flash or prot rusions. Inter-lead Flash and prot rusions shall not exceed
0.25 mm (0.010 in) per sid e.
4. Dimension b does not include Dambar prot rusion. Allowable Dambar prot rusion shall be 0.08 mm total in excess of the
b dimension at maxi mum mate rial condition . Dambar cannot be located on the l ower radius of the foot. Minimum space
between protrusion and adjacent lead is 0.07 mm .
5. Dimension D and E1 to be dete rmined at Datum Plane H .
05/30/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
REV.
8A2
B
17
8568A–SEEPR–9/09
UDFN
Figure 15.
8MA2 – UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
A2
A
A1
E2
COMMON DIMENSIONS
(Unit of Measure = mm)
b (8x)
SYMBOL
8
1
Pin#1 ID
(R0.10)
7
0.35
2
D2
6
3
5
4
e (6x)
K
L (8x)
MIN
NOM
D
2.00 BSC
E
3.00 BSC
MAX
D2
1.40
1.50
E2
1.20
1.30
1.40
A
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
–
–
0.55
C
L
NOTE
1.60
0.152 REF
0.30
0.35
e
0.40
0.50 BSC
b
0.18
0.25
0.30
K
0.20
–
–
3
4/15/08
Package Drawing Contact:
packa[email protected]
18
TITLE
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ult ra Thin Dual Flat No
Lead Package (UDFN)
GPC
YNZ
DRAWING NO.
8MA2
REV.
A
AT24C256C [Preliminary]
8568A–SEEPR–9/09
AT24C256C [Preliminary]
8U2-1 – VFBGA
Figure 16.
8U2-1 – VFBGA
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
A1
A2
b
D
E
Notes:
1. This drawing is for general information.
2. Dimension 'b' is measured at the maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
e
e1
d
d1
Package Drawing Contact:•
[email protected]
MIN
0.81
0.15
0.40
0.25
NOM
MAX
NOTE
0.91 1.00
0.20 0.25
0.45 0.50
0.30 0.35
2.35 BSC
3.73 BSC
0.75 BSC
0.74 REF
0.75 BSC
0.80 REF
2/25/08
GPC
DRAWING NO. REV.
TITLE
8U2-1, 8 ball, 2.35 x 3.73 mm Body, 0.75 mm pitch
•
GWW
8U2-1
C
VFBGA Package (dBGA2)
19
8568A–SEEPR–9/09
Appendix A. Revision History
20
Doc. Rev.
Date
8568A
09/2009
Comments
Initial document release
AT24C256C [Preliminary]
8568A–SEEPR–9/09
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8568A–SEEPR–9/09