MOTOROLA MC33260

4若发应再挣
(<8手元!J侍应用 hOOO$6 月第 2 卷第 6 期
GreenLine™小型廉价功率因数控制器
MC33260 的持点及应用
摘
山东省临沂市电子工业局
毛兴武祝大卫 (276004)
山东省临沂市计算机公司
张润领
要摩托罗拉公司近期推出的i>FC 控制器 MC33260 ，是一种廉价的创新型羊片 IC o MC33260 在
开关电源或电子镇流器应用中，只需很少量的外部元件，就可实现一切所必需的控制与保护功能。本
文介绍了 MC33260 的结构、特点及功能，重点介绍了其应用情况。
关键词
PFC 控制器羊片 IC
表 1 列出的是 MC33260 的引脚功能 09
一、序言
表
自本世纪 80 年代中期至今，功率因数校正
(PFC) 控制器单片 IC 已达几十个品种。 PFC 单片 IC
脚号
该脚用作接收正比于预变换器输出电压的一
1
反馈输入
该脚与地之间连接一只电容，用作调节控制带
2
电压控制
宽。为得到非畸变输入电流，带宽瘟常设定在
20Hz 以下。
范围在 300W 以上，直至 4.5KW 。从全球开关电源和
电子镇流器负载容量看，至少有 70% 在 150W 以下。
个电流，覆行电压调整和过电压、欠电压保护
功能。该脚输入电流在内部自乘后用作振荡器
电容充电电流。
两大类。其中前者适用于 300W 以下，尤其是 100W
以下的 PFC 预调整器中作为控制器，后者适用功率
说明
功能
从 PFC 预变换器中(升压)电感电流传导方式上分，
主要有断续传导模式 (DCM) 和连续传导模式 (CCM)
MC33260 引脚符号及功能说明
3
振荡电容
( CT)
因此， DCM 功率因数控制器占主导地位。
该电路采用开通时间控制方式。通过 CT 电压
与控制电压比较，来控制开通时间。 CT 由平方
后的反馈输水电流充电。
过零电流检测输入。该脚接收一个正比于通过
电感器电流的负电压信号，并通过一只电流检
在目前所有 DCM 功率因数控制器 IC 中，尤其是
测电阻实现。只要该脚电压在 -60mV 之下，零
电流检测则阻止重新开始。该脚还用作履行峰
值电流限制 σ 连接该脚与外部电流检测电阻之
间的电阻可用作编程过电流门限。
4
零电流检测
输入
5
同步输入
也可以是电子镇流器等。
6
接地
二、内部结构及引脚功能
7
栅极驱动
栅极驱动器输出;适于驱动外部的一只 IGBT
或功率 MOSFET 。
8
Vcc
IC 电源电压。 Vα 启动门限为 11 :1: 1. 3V ，在门
限开通后禁能电压为 8.5 土1. 1V 。
采用 8 脚封装的 PFC 控制器 IC 中，功能最齐全、价格
最低的当属摩托罗拉公司 1999 年推出的创新型
MC33260 。该 PFC 单片 IC 适用于国际供电电路， AC
输入电压从 90V 到 270V ，而且负载既可以是 SMPS ，
MC33260 采用 8 脚 DIP 塑料封装，引脚排列如
图l( a) 所示。图l( b) 为 MC33260 的内部结构框图。
同步化输入。该脚为接收干个同步信号而设
计，例如，它能使 PFC 预变换器与 SMPS 同
步。、如果不用，该脚必须接地。
该脚必须连接到预调整器的地。
三、主要电气性能及特点
~
反馈输入 1 1 1 。
1I1'lli~
I
~
r-v Y I I
IIII
!.
VJO~12
._ ~ .
1.主要电气特性
71 栅极驱动
~I 3
MC33260 的最大额定参数如下:
振荡电容
电流检测输川 4
(1)最大额定参数
51 同步输入
脚 7 栅极驱动电流
源电流 [0 (source)
图l( a)
封装及引脚排列
.1
…...…………… .........500mA
灌电流Io ('ink) ………......................…… 500mA
..
11
GreeoLioe™小型廉份功率因巍栓俄J .a MC33260 筒精点反应用
Vo
Current Mirror
α←
3
民
l
@2
nt Ol
nu
VA
r
llV/8.5V
s'5
vdnC
Current
Sense
4
Vcc
OutpuCCtrl
MC33260
图 1 (b)
"
MC33260 内部结构的框图
脚 8 最高电源电压 VCC(m田)……........…… .....16V
极驱动输出电压上升和下降时间均为 5008 0
输入电压Vin .......……………….......... -
0.3 -IOV
2. 主要特点
•..•........... 600mW
ur 一般特征
最大功耗 (@T A
= 85 "C) PD
最高工作结温旦.................…...... ....
工作环境温度 TA
150"C
........….......... - 40 - 105 "C
(2 )主要电特性简述
MC33260 的启动门限电压典型值是 llV( 带
2.5V 的滞后) ，启动电源电流不大于 0.25 mA，工作电
流(@ 1 脚 1 =200μA) Icc~三 8mA( 典型值是 4mA)0 IC
脚 4 的零电流检测比较器门限电压为 -60mV( 典型
值) ，脚 7 上的同步门限电压为 1 :t O. 2V ，脚 1 上过电
压保护高电流电平门限为 13 :t 5μA ，热关闭门限为
150"C (带 30"C滞后)。振荡器最大摆幅是 lJ :t O. lV ,
CT 充、放电电流典型值分别为 100μA 和 400μA 。栅
12
·标准恒定输出电压或"后随升压"模式;
·开关型操作:电压模式;
·自锁 PWM ，逐周开通时间控制;
·固定开通时间操作，可节省一个附加
的乘法器;
·图腾柱(推挽)输出栅极驱动;
·随滞后欠电压闭锁;
·低启动和工作电流;
·同步化能力:
·内部微调基准电流源。
(2 )安全特征
.
V且
LH O
JFrt--w
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·在每个引脚上 ESD 保护。
·过电压保护:输出过电压检测;
·欠电压保护:开环保护;
四、工作原理与功能
·有效的零电流检测;
MC33260 典型应用布排如图 2 所示。在图 2 中，
·精密与可调最大开通时间限制;
飞
负载可以是 SMPS ，也可以是电子镇流器等。
FJV}LP·'
』
·过电流保护;
』p''ipLPK·-··viph'
滤波电容器
。
SNmSE
Ro
Rocp
rh CT
MC33260 典型应用
图 2
振荡器包含充电、放电和等候三种状态。
1.电压调整
在 PFC 预变换器 DC 输出电压 VO 与 MC33260
脚 1 之间，连接一只电阻此，
振荡器充电电流为:
/charge
以获取一个反馈电流
VO -
vi脚 1
R了一
、‘，，，，
_
'EA
反馈电流与内部参考电流/，ef 比较，使输出电压
压超过 ( VO) 吨H 时，反馈电流应等于内部电流源
I吨H 。因此:
(2)
JIIIi
由于脚 1 钳位电压值与 ( Vo) 吨H 比较是可以忽略
的， /，egH 典型值为 200μA ， Ro 的计算公式可简化为:
=5 X (
VO) ,egH( k11)
(3)
一旦 Ro 确定，输出电压调整电平则由此调
节。调整单元输出通过一只 300kfi 的电阻连接到 IC
,
脚 2 ，脚 2 上电压 (Vcontrol) 与振荡器锯齿波进行比较，
以实现 PWM 控制。脚 2 到地的一只电容，用于外部
环路补偿。为抑制主频率 ( 100/120Hz) 输出纹波，补
偿带宽应设定在 20Hz 以下。
2. 振荡器
)2
因此，上面等式可简化为:
_ 2X 阿
Rõ
卜----­
'cn"'ge
X /rer
t
(5)
振荡器有一个内部电容 Cint (1 5PF) ，总电容应
是 CT 与 Cint 之和，即 C 脚 3
O ),eidl - V
Ro = (\V
.Oheidl
.JI!II 1
1"唔;H
Ro
vi脚 1
V 脚 I 在 2.5V 的范围之内，与 VO 比较非常之小，
调整电平在( VO) ，efL与( Vo) ，egH 之间的变化。当输出电
,
(4)
Rõ X /ref
iE飞
T
=2 X Pr/ /rer
_1X (Vo -
I 脚 10 反馈电流的数值由下式给出:
2脚 1-
事
= CT + Cint o
3.PWM 闭锁
IC 在电压模式下工作，调整单元输出(民ontrol- V 脚 2)
与振荡器锯齿波电压比较，直到振荡器斜波超过
忆。ntml 之前，栅极驱动电压信号(脚 7) 是高电平。开通
时间由下式给出
儿
-
C脚二×忆。ntrol
(6)
lch缸雹β
将式 (5)代入式 (4) ，可得:
tnn = RÕX/'efXC脚 3 X VControl
2x 陀
(7)
当 Vcontrol 最大时(典型值是1. 5V) ，开通时间
最大。对于给定的仇，最大开通时间由式 (8) 给出:
13
GreenLine™ 小型廉份功率困或控制系 MC33260 的精点反应用
/-M
E一、
一
l­
E也
o-oEl-n­
HZ
-m-
(8)
10VPH ， 栅极驱动信号在反馈电流低于第二个电平 10VPL
之前，则维持低电平。过电平保护上门限为:
E
「llJ
叫"-
FA-
、
/飞-×-
「 L
-q0
一
c脚 3
,
×一忡忡。甘-
脚一脚一
221
-F=
h一切一2
-uu-X
R-R
pu-ru-20-20×-qh×
J-E
max
×一×
0n
、、自/
J'E‘、
4'U
VOVPH = V 脚 l+(Rox/oVPH)
由于 V 脚 1~2.5V ，是可以忽略的。若 Ro 单位是
XRõ
MO ，/oVPH 是 μ A ，式 (12) 可简化为:
阿 xKosc
VOVPH = Ro
式 (8) 中 ， Kocs 为振荡器增商上的摆幅比率。
X
IOVPH (V)
VOVPL
这对于用作升压操作是非常适宜的。
= V 脚 1 + ( Ro x lovpd
"'" Ro(MO) x
4. 电流检测
流经升压电感器(L)的电流通过电流检测电阻
(13)
另一方面， OVP 的下门限是:
从式 (8) 可以看出，最大开通时间与 V 2 0 成反比，
loVPL( μA)
(V)
(1 4)
8. 欠电压保护 (UVP) 与欠电压锁定 (UVLO)
当反馈电流低于Iref 的 140毛时，被 UVP 电路检
Rcs 变换为一个电压信号。 Rcs 两端的(负)电压与 ι
测。此情况下， PWM 问锁复位，功率开关关断。当忽略
成正比:
Vcs = -(Rcs-/d
(9)
V 脚 l 时， UVP 门限为:
VUVP = Ro(MO) x
Rιs 上的电压信号经一只电阻 Rocp 施加到 IC 脚
e
(12)
luvp( μA)
(V)
(1 5)
4 。只要脚 4 上的电压一低于 -60mV ，电流传感比较
IC 内的 UVLO 比较器监测脚 8 上的电压。只要
器就复位 PWM 问锁，迫使栅极驱动信号为低电平，
VCC > 11V ， IC 则被激活。当 Vcc 降低到 8.δV 以下时，
功率开关 MOSFET 或 (IGBT) 截止。在开通期间，脚 4
IC 则失能 O 电路在关断状态下，电流消耗不大于
上的信号被用作过电流限制。
100μA 。
5. 过零电流检测
9. 热关闭
只要电流检测电阻 Rcs 上的电压 Vcs 一低于电
如果 IC 结温超过 150"C， IC 则关闭其栅极驱动
流传感比较器的门限 ( -60mV) ，栅极驱动信号则保
输出。当结温降至 120 "C以下时， IC 则再次被启动，能
持低电平，功率 MOSFET 则关断。一旦升压电感器上
产生输出驱动信号。
的高频开关(振荡)电流降低到 600mV / Rcs 以下，亦
10. 同步化
即接过于零时， IC 则驱动功率 MOSFET 由截止跃变
MC33260 有两种工作模式:
到开通状态。在电感电流从零增大到其峰值之前，
(1)自由振荡 (free running) 断续模式:在升压电
MOSFET 则一直导通。只要电感电流沿斜坡增大到其
感器中的电流一降为零，功率开关则开通，下一个周
峰值， MOSFET 则开始关断，并一直维持到电感电流
期则开始。该模式的获得是通过 IC 脚 5 接地实现
沿向下的斜坡降至零之前。
的。
6. 过电流保护 (ocp)
(2) 同步化模式: IC 脚 5 上的电压只要超过 lV
在功率开关导通时，一个电流源施加到脚 4 ，在
Rocp 两端产生 1 个电压降 VocPo Rcs 与 VO ω 之和与
b. 通过最后一个同步上升沿跨越 lV 的门限，先
ιιk山叩 =i晶川
前的开通已被跟随。
式(1 0ω) 中 ， ι
1，忡阳m叩曰为过电流门限 ， loc
创CP = 却
2 05μA 。由于
Vocp>60mV ，故式 (10) 可简化为:
Roc/kO)
Rcs\O)
(11)
部不必设置任何滤波电容。
,/
反馈电流 10 与门限电流 10VPH 比较，如果超过
14
由于同步信号能延长功率开关关断时间，因此，
为保证同步化操作，要求电流周期(开通时间+电感
由于 IC 内设计了前沿消隐 (LEB) 电路，脚 4 外
7. 过电压保护 (OVp)
个条件满足之前，功率开关不能开通:
a. 零电流被检测;
一 60mV 相比较，最大容许电流由式(1 0) 给出:
kmax= 丁7AγXO.205(A)
的门限，该工作模式就被建立。在该模式中，在下面两
退磁时间)短于同步周期。电感器必须正确选择，以防
止系统工作在自由振荡断续模式。为在轻载条件下限
制开关频率，要求开关截止时间最小是 2 阳。
1 1.跟随器升压 (FolÍwer 丑008t)
以往的 PFC 预变换器为负载提供一个固定的调
整 DC 电压(如 400V) 。在 "Follower f3oost"操作中，预
{<ll亭玉~.a (非启用 hooo í:F 6 月
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变换器输出调整电平不是固定的。但是，在一个给定
的输入功率上， DC 输出电压随 AC 线路电压幅值线
rl-
p、
|调整块是有源区
!Yo=Vplt/
/
性变化。图 3(a) 为 MC33260 的跟随升压特性。
,
,,,,
飞
传统输出
(Pin)max
Vo(跟随器升压)
Vac
Vac
VacLL
负载
图 3b
MC33260 的跟随升压特性
图 3a
机与几关系曲线
为便于理解 MC33260 的工作原理与功能，图 4 给
大家知道，在 PFC 预变换器中，若瞬时 AC 输入
出了其典型波形。
电压为 Vin ， 升压电感器的电感是 Lp ， DC 输出电压是
五、典型应用
帆，在功率开关开通期间，电感电流则按斜率 Vin/ L p
线性增长;在功率开关关断期间，电感电流则按(民­
归 n)/ Lp 线性下降，从而形成三角形电流波形。采用
眼随升压技术，对于一个给定的峰值电感电流，开关
截止时间会变长，占空比变小。与传统的 PFC 预变换
器比较，其优点有二:一是 MOSFET 开通损耗减小，二
用 MC33260 作为控制器的 SMPS 或镇流器 PFC 预
变换器电路如图 5(a) 所示。图 5(b) 示出的是 IC 的民c 电
源电路。图 4 中 ， Ll 采用 EE25 磁心和 22AWG 号磁导线
绕制，初级线圈 Np=62T， 次级 N二 =5T，气隙长度为
0.072"( 臼 0.18mm) 。表 2 列出了 80W 升压式 PFC 预变
换器的实测数据。
l'
是允许利用较小的、廉价的电感元件。
设 AC 峰值输入电压为 VPK ， MOSFTE 开通时间
可表示为:
ton =
4 XL p X P in
阵宜
(1 6)
同步信号
根据式 (8) 和式 (16) ，可得到下面的跟随升压等式:
冒 ， _Ro"
I
川 -2 《 V
C脚冒 r
Kosc
×
Lp × PEnAFK
零电流检测
(1 7)
12. 模式选择
211s 延时
图 3(b) 示出了 MC33260 跟随提升输出电压与输
人交流电压凡的关系曲线。由图可知，机随儿
增加首先线性增大，最后钳位于调节设定值。在传统
的模式中，线性区必须被抑制。 MC33260 的工作模式
可以通过调节振荡器电容的数值来选择。如果( VO)
<e
gL
pbrhr'rp 低于输出调整电平，根据式 (17) ，可得:
4X
Kosc
X
Lp X (Pin)m阻 X (民 )ιL
.
;;?!: C;
CTr=-Umt
nt +二
Rõ X 阿K
电路输出
检测电流Ics
(1 8)
'(P】i
叫
iJ
=C】 +4 XKosc XLpX'
阿FK
V
电感电流
'~
为获得所希望的跟随升压特性，振荡器电容必须按
照公式 (18) 来选择。
图 4
'&
MC33260 的典型波形
..
15
GreenLine™小型廉份功率因我拉刽忌 MC33260 筒精点反应用
L1
D5
MUR460E
C1
330nF
500Vdc
R3
'
图 5a
表2
Vnns
MC33260 在 80W PFC 预变换器中的实际应用电路
PFC 预调整器测试数据
90
110
135
180
220
240
(W)
PF
88.2
86.3
85.2
87.0
84. 7
85.3 84.0
Ir"""
990
782
642
480
385
8. 1
7.0
8.2
9.5
15
16.5 18.8
H2
0.07
0.05
0.03
o. 16
0.5
o. 7 o. 7
H3
5.9
2. 7
1. 5
4.0
8.4
9.0
1 1. 0
H5
4.3
5. 7
6. 8
6.5
7.8
7.8
7.0
H7
1. 5
1. 1
1. 1
3. 1
5.3
7.4
9.0
H9
1. 7
0.8
1. 5
4.0
1. 9
3.8
4.0
(v)
181
222
265
360
379
384
392
..1 Vo
(V)
3 1. 2
26.4
20.8
16.0
14.0
14.0 13.2
h
440
360
300
225
210
210
79.6
79.9
795
8 1. 0
79.6
80.6 80.4
90.2
92.6
93.3
93. 1
94.4
91.5 95. 7
(v)
Pin"
260
(- ) 0.991 0.996 0.995 0.994 0.982 0.975 0.967
"
(mA)
注。
善
THD
输
入
电
流
谐
,
359
330
波
畸
变
(% )
Vo
C飞
已
输
出
(mA)
Po
(W)
叫
(%)
16
205
图 5b
MC33260 电源电路
.
MC33260
GreenLinet Compact
Power Factor Controller:
Innovative Circuit for
Cost Effective Solutions
The MC33260 is a controller for Power Factor Correction
preconverters meeting international standard requirements in
electronic ballast and off--line power conversion applications.
Designed to drive a free frequency discontinuous mode, it can also be
synchronized and in any case, it features very effective protections that
ensure a safe and reliable operation.
This circuit is also optimized to offer extremely compact and cost
effective PFC solutions. While it requires a minimum number of
external components, the MC33260 can control the follower boost
operation that is an innovative mode allowing a drastic size reduction
of both the inductor and the power switch. Ultimately, the solution
system cost is significantly lowered.
Also able to function in a traditional way (constant output voltage
regulation level), any intermediary solutions can be easily
implemented. This flexibility makes it ideal to optimally cope with a
wide range of applications.
Standard Constant Output Voltage or “Follower Boost” Mode
Switch Mode Operation: Voltage Mode
Latching PWM for Cycle--by--Cycle On--Time Control
Constant On--Time Operation That Saves the Use of an Extra Multiplier
Totem Pole Output Gate Drive
Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
Improved Regulation Block Dynamic Behavior
Synchronization Capability
Internally Trimmed Reference Current Source
These are Pb--Free Devices
Safety Features
D1...D4
Filtering
Capacitor
L1
Vcontrol
R cs
8
1
8
SO--8
D SUFFIX
CASE 751
CT
ROCP
1
2
3
4
8
7
6
5
+ C1
M1
Ro
1
33260
ALYW
G
1
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb--Free Package
PIN CONNECTIONS
Feedback Input
1
8 VCC
Vcontrol
2
7 Gate Drive
3
6 Gnd
4
5 Synchronization
Input
MC33260P
Oscillator
Capacitor (CT)
Current Sense
Input
Synchronization
Input
Gnd
D1
V CC
MC33260P
AWL
YYWWG
PDIP--8
P SUFFIX
CASE 626
Oscillator
Capacitor (CT)
Current Sense
Input
Overvoltage Protection: Output Overvoltage Detection
Undervoltage Protection: Protection Against Open Loop
Effective Zero Current Detection
Accurate and Adjustable Maximum On--Time Limitation
Overcurrent Protection
ESD Protection on Each Pin
MC33260






MARKING
DIAGRAMS
8
General Features











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LOAD
(SMPS, Lamp
Ballast,...)
1
8
Vcontrol
2
7
Feedback Input
3
6
VCC
5
Gate Drive
4
MC33260D
ORDERING INFORMATION
Sync
DIP--8 CONFIGURATION SHOWN
See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.
Figure 1. Typical Application
 Semiconductor Components Industries, LLC, 2010
November, 2010 -- Rev. 11
1
Publication Order Number:
MC33260/D
MC33260
Vo
Current Mirror
IOSC -- ch =
Io
2 x IO x IO
Iref
Io
Io
CT
Io
1
0
Current
Mirror
Iref
Vref
11 V
FB
1.5 V
15 pF
Io
97%Iref
300 k
Vreg
Vcontrol
Iref
Output_Ctrl
IovpH/IovpL
Vref
REGULATOR
11 V
+
Iref
Enable
--
OVP
r
Iuvp
r
--
11 V/8.5 V
+
+
UVP
--
Ics (205 mA)
1
Synchro
r
--60 mV
0
11 V
+
Current
Sense
LEB
11 V
Synchro
Arrangement
--
VCC
Output_Ctrl
ThStdwn
Drive
Gnd
S
R
+
R
--
R
Q
PWM
Latch
Output_Ctrl
Q
PWM Comparator
MC33260
Figure 2. Block Diagram
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2
MC33260
MAXIMUM RATINGS
Pin #
PDIP--8
Pin #
SO--8
Gate Drive Current*
Source
Sink
7
5
VCC Maximum Voltage
8
Rating
Symbol
Value
Unit
IO(Source)
IO(Sink)
--500
500
(Vcc)max
16
V
Vin
--0.3 to +10
V
PD
RθJA
600
100
mW
C/W
Operating Junction Temperature
TJ
150
C
Operating Ambient Temperature
TA
--40 to +105
C
mA
6
Input Voltage
Power Dissipation and Thermal Characteristics
P Suffix, PDIP Package
Maximum Power Dissipation @ TA = 85C
Thermal Resistance Junction--to--Air
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (VCC = 13 V, TJ = 25C for typical values, TJ = --40 to 105C for min/max values
unless otherwise noted.)
Pin #
PDIP--8
Pin #
SO--8
Gate Drive Resistor
Source Resistor @ IDrive = 100 mA
Sink Resistor @ IDrive = 100 mA
7
5
Gate Drive Voltage Rise Time (From 3.0 V Up to 9.0 V)
(Note 1)
7
Output Voltage Falling Time (From 9.0 V Down to 3.0 V)
(Note 1)
Symbol
Min
Typ
Max
ROL
ROH
10
5
20
10
35
25
5
tr
--
50
--
ns
7
5
tf
--
50
--
ns
Maximum Oscillator Swing
3
1
ΔVT
1.4
1.5
1.6
V
Charge Current @ IFB = 100 mA
3
1
Icharge
87.5
100
112.5
mA
Charge Current @ IFB = 200 mA
3
1
Icharge
350
400
450
mA
Ratio Multiplier Gain Over Maximum Swing
@ IFB = 100 mA
3
1
Kosc
5600
6400
7200
1/(V.A)
Ratio Multiplier Gain Over Maximum Swing
@ IFB = 200 mA
3
1
Kosc
5600
6400
7200
1/(V.A)
Average Internal Oscillator Pin Capacitance Over
Oscillator Maximum Swing (CT Voltage Varying From
0 Up to 1.5 V) (Note 2)
3
1
Cint
10
15
20
pF
Discharge Time (CT = 1.0 nF)
3
1
Tdisch
--
0.5
1.0
ms
Regulation High Current Reference
1
7
IregH
192
200
208
mA
Ratio (Regulation Low Current Reference) / IregH
1
7
IregL / IregH
0.965
0.97
0.98
--
Vcontrol Impedance
1
7
ZVcontrol
--
300
--
kΩ
Characteristic
Unit
GATE DRIVE SECTION
Ω
OSCILLATOR SECTION
REGULATION SECTION
NOTE: IFB is the current that is drawn by the Feedback Input Pin.
1. 1.0 nF being connected between the Pin 7 and ground for PDIP--8, between Pin 5 and ground for SO--8.
2. Guaranteed by design.
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3
MC33260
ELECTRICAL CHARACTERISTICS (VCC = 13 V, TJ = 25C for typical values, TJ = --40 to 105C for min/max values
unless otherwise noted.)
Pin #
PDIP--8
Pin #
SO--8
Symbol
Min
Typ
Max
Unit
Feedback Pin Clamp Voltage @ IFB = 100 mA
1
7
VFB--100
1.5
2.1
2.5
V
Feedback Pin Clamp Voltage @ IFB = 200 mA
1
7
VFB--200
2.0
2.6
3.0
V
Zero Current Detection Comparator Threshold
4
2
VZCD--th
--90
--60
--30
mV
Negative Clamp Level (ICS--pin = --1.0 mA)
4
2
Cl--neg
--
--0.7
--
V
Bias Current @ Vcs = VZCD--th
4
2
Ib--cs
--0.2
--
--
mA
Propagation Delay (Vcs > VZCD--th) to Gate Drive High
7
5
TZCD
--
500
--
ns
Current Sense Pin Internal Current Source
4
2
IOCP
192
205
218
mA
LEB
--
400
--
ns
Characteristic
REGULATION SECTION (continued)
CURRENT SENSE SECTION
Leading Edge Blanking Duration
OverCurrent Protection Propagation Delay
(Vcs < VZCD--th to Gate Drive Low)
7
5
TOCP
100
160
240
ns
Synchronization Threshold
PDIP--8
SO--8
5
--
-3
Vsync--th
Vsync--th
0.8
0.8
1.0
1.0
1.2
1.4
V
V
Negative Clamp Level (Isync = --1.0 mA)
5
3
Cl--neg
--
--0.7
--
V
Minimum Off--Time
7
5
Toff
1.5
2.1
2.7
ms
Minimum Required Synchronization Pulse Duration
5
3
Tsync
--
--
0.5
ms
OverVoltage Protection High Current Threshold
and IregH Difference
1
7
IOVPH --IregH
8.0
13
18
mA
OverVoltage Protection Low Current Threshold
and IregH Difference
1
7
IOVPL --IregH
0
--
--
--
Ratio (IOVPH/IOVPL)
1
7
IOVPH / IOVPL
1.02
--
--
--
Propagation Delay (IFB > 110% Iref to Gate Drive Low)
7
5
TOVP
--
500
--
ns
Ratio (UnderVoltage Protection Current
Threshold) / IregH
1
7
IUVP/IregH
12
14
16
%
Propagation Delay (IFB < 12% Iref to Gate Drive Low)
7
5
TUVP
--
500
--
ns
Thermal Shutdown Threshold
7
5
Tstdwn
—
150
--
C
Hysteresis
7
5
ΔTstdwn
--
30
--
C
Startup Threshold
8
6
Vstup--th
9.7
11
12.3
V
Disable Voltage After Threshold Turn--On
8
6
Vdisable
7.4
8.5
9.6
V
8
6
ICC
---
0.1
4.0
0.25
8.0
SYNCHRONIZATION SECTION
OVERVOLTAGE PROTECTION SECTION
UNDERVOLTAGE PROTECTION SECTION
THERMAL SHUTDOWN SECTION
VCC UNDERVOLTAGE LOCKOUT SECTION
TOTAL DEVICE
Power Supply Current
Startup (VCC = 5 V with VCC Increasing)
Operating @ IFB = 200 mA
NOTE:
Vcs is the Current Sense Pin Voltage and IFB is the Feedback Pin Current.
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4
mA
MC33260
1.6
Vcontrol : REGULATION BLOCK OUTPUT (V)
Vcontrol : REGULATION BLOCK OUTPUT (V)
Pin Numbers are Relevant to the PDIP--8 Version
1.4
1.2
1.0
0.8
0.6
-- 40C
0.4
25C
0.2
105C
0
0
20
40
60
80 100 120 140 160 180 200 220 240
1.6
-- 40C
1.4
25C
1.2
105C
1.0
0.8
0.6
0.4
0.2
0
185
190
1.340
3.5
1.335
3.0
1.330
1.325
1.320
1.315
1.310
1.305
--20
0
20
40
60
80
1.5
100
-- 40C
1.0
25C
0.5
0
105C
0
20
40
350
105C
300
250
200
150
100
50
0
0
20
40
60
80 100 120 140 160 180 200 220 240
Figure 6. Feedback Input Voltage versus
Feedback Current
I osc--ch , OSCILLATOR CHARGE CURRENT ( m A)
I osc--ch , OSCILLATOR CHARGE CURRENT ( m A)
25C
60
Ipin1: FEEDBACK CURRENT (mA)
500
400
210
2.0
Figure 5. Maximum Oscillator Swing versus
Temperature
450
205
2.5
JUNCTION TEMPERATURE (C)
-- 40C
200
Figure 4. Regulation Block Output versus
Feedback Current
FEEDBACK INPUT VOLTAGE (V)
MAXIMUM OSCILLATOR SWING (V)
Figure 3. Regulation Block Output versus
Feedback Current
1.300
--40
195
Ipin1: FEEDBACK CURRENT (mA)
Ipin1: FEEDBACK CURRENT (mA)
80 100 120 140 160 180 200 220 240
410
Ipin1 = 200 mA
405
400
395
390
385
--40
--20
0
20
40
60
80
JUNCTION TEMPERATURE (C)
Ipin1: FEEDBACK CURRENT (mA)
Figure 7. Oscillator Charge Current versus
Feedback Current
Figure 8. Oscillator Charge Current versus
Temperature
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5
100
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
120
103
Ipin1 = 100 mA
-- 40C
100
102
ON--TIME ( s)
OSCILLATOR CHARGE CURRENT ( A)
104
101
100
99
25C
105C
80
1 nF Connected to Pin 3
60
40
20
98
97
--40
--20
0
20
40
60
80
0
100
30
50
TJ, JUNCTION TEMPERATURE (C)
REGULATION AND CS CURRENT SOURCE ( A)
-- 40C
ON--TIME ( s)
25C
105C
1 nF Connected to Pin 3
45
35
25
15
60
50
70
80
130
150
170
190
210
90
100
207
IOCP
206
205
204
203
202
IregH
201
200
199
198
197
--40
--20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (C)
Ipin1: FEEDBACK CURRENT (mA)
Figure 11. On--Time versus Feedback Current
Figure 12. Internal Current Sources versus
Temperature
1.07
0.150
1.06
(IovpH/Iref)
1.05
1.04
1.03
1.02
1.01
UNDERVOLTAGE RATIO (I uvp /I ref )
(IovpH /I ref ), (I ovpL /I ref ), (I regL /I ref )
110
Figure 10. On--Time versus Feedback Current
75
55
90
Ipin1: FEEDBACK CURRENT (mA)
Figure 9. Oscillator Charge Current versus
Temperature
65
70
(IovpL/Iref)
1.00
0.99
0.98
0.97
0.96
--40
(IregL/Iref)
--20
0
20
40
60
80
100
0.148
0.146
0.144
0.142
0.140
0.138
0.136
0.134
0.132
0.130
--40
TJ, JUNCTION TEMPERATURE (C)
--20
0
20
40
60
80
TJ, JUNCTION TEMPERATURE (C)
Figure 13. (IovpH/Iref), (IovpL/Iref), (IregL/Iref)
versus Temperature
Figure 14. Undervoltage Ratio versus
Temperature
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6
100
MC33260
--54.8
4.5
--55
4.0
-- 40C
3.5
25C
3.0
105C
I CC , CIRCUIT CONSUMPTION (mA)
CURRENT SENSE THRESHOLD (mV)
Pin Numbers are Relevant to the PDIP--8 Version
--55.2
--55.4
--55.6
--55.8
--56
--56.2
--56.4
--56.6
--40
--20
0
20
40
60
80
100
2.5
2.0
1.5
1.0
0.5
0
2
0
TJ, JUNCTION TEMPERATURE (C)
6
8
10
12
14
16
VCC: SUPPLY VOLTAGE (V)
Figure 16. Circuit Consumption versus
Supply Voltage
Figure 15. Current Sense Threshold versus
Temperature
OSCILLATOR PIN INTERNAL CAPACITANCE (pF)
4
Vgate
20
--40C
15
25C
VCC = 12 V
Cgate = 1 nF
1
25C
10
Icross--cond (50 mA/div)
105C
5
2
0
0.2
0
0.4
0.6
0.8
1.0
1.2
1.4
Ch1
10.0 V
Ch2 10.0 mVΩ
M 1.00 ms
Ch1
600 mV
Vcontrol: PIN 2 VOLTAGE (V)
Figure 17. Oscillator Pin Internal Capacitance
Figure 18. Gate Drive Cross Conduction
Vgate
Vgate
-- 40C
VCC = 12 V
Cgate = 1 nF
1
105C
VCC = 12 V
Cgate = 1 nF
1
Icross--cond (50 mA/div)
Icross--cond (50 mA/div)
2
2
Ch1
10.0 V
Ch2 10.0 mVΩ
M 1.00 ms
Ch1
600 mV
Ch1
Figure 19. Gate Drive Cross Conduction
10.0 V
Ch2 10.0 mVΩ
M 1.00 ms
Ch1
Figure 20. Gate Drive Cross Conduction
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7
600 mV
MC33260
PIN FUNCTION DESCRIPTION
Pin #
PDIP--8
Pin #
SO--8
Function
Description
1
7
Feedback Input
This pin is designed to receive a current that is proportional to the preconverter output
voltage. This information is used for both the regulation and the overvoltage and
undervoltage protections. The current drawn by this pin is internally squared to be used
as oscillator capacitor charge current.
2
8
Vcontrol
This pin makes available the regulation block output. The capacitor connected between
this pin and ground, adjusts the control bandwidth. It is typically set below 20 Hz to
obtain a nondistorted input current.
3
1
Oscillator Capacitor
(CT)
The circuit uses an on--time control mode. This on--time is controlled by comparing the
CT voltage to the Vcontrol voltage. CT is charged by the squared feedback current.
4
2
Zero Current
Detection Input
This pin is designed to receive a negative voltage signal proportional to the current
flowing through the inductor. This information is generally built using a sense resistor.
The Zero Current Detection prevents any restart as long as the Pin 4 voltage is below
(--60 mV). This pin is also used to perform the peak current limitation. The overcurrent
threshold is programmed by the resistor connected between the pin and the external
current sense resistor.
5
3
Synchronization
Input
This pin is designed to receive a synchronization signal. For instance, it enables to
synchronize the PFC preconverter to the associated SMPS. If not used, this pin must
be grounded.
6
4
Ground
7
5
Gate Drive
8
6
VCC
This pin must be connected to the preregulator ground.
The gate drive current capability is suited to drive an IGBT or a power MOSFET.
This pin is the positive supply of the IC. The circuit turns on when VCC becomes higher
than 11 V, the operating range after startup being 8.5 V up to 16 V.
Filtering
Capacitor
D1...D4
L1
D1
+ C1
2
Vcontrol
ROCP
3
4
CT
8
MC33260
1
Load
(SMPS, Lamp
Ballast,...)
VCC
M1
7
Ro
6
5
Sync
Rcs
DIP--8 CONFIGURATION SHOWN
Figure 21. Application Schematic
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8
MC33260
FUNCTIONAL DESCRIPTION
Pin Numbers are Relevant to the PDIP--8 Version
INTRODUCTION
OPERATION DESCRIPTION
The need of meeting the requirements of legislation on
line current harmonic content, results in an increasing
demand for cost effective solutions to comply with the
Power Factor regulations. This data sheet describes a
monolithic controller specially designed for this purpose.
Most off--line appliances use a bridge rectifier associated
to a huge bulk capacitor to derive raw dc voltage from the
utility ac line.
The MC33260 is optimized to just as well drive a free
running as a synchronized discontinuous voltage mode.
It also features valuable protections (overvoltage and
undervoltage protection, overcurrent limitation, ...) that
make the PFC preregulator very safe and reliable while
requiring very few external components. In particular, it is
able to safely face any uncontrolled direct charges of the
output capacitor from the mains which occur when the
output voltage is lower than the input voltage (startup,
overload, ...).
In addition to the low count of elements, the circuit can
control an innovative mode named “Follower Boost” that
permits to significantly reduce the size of the preconverter
inductor and power MOSFET. With this technique, the
output regulation level is not forced to a constant value, but
can vary according to the a.c. line amplitude and to the
power. The gap between the output voltage and the ac line
is then lowered, what allows the preconverter inductor and
power MOSFET size reduction. Finally, this method brings
a significant cost reduction.
A description of the functional blocks is given below.
Rectifiers
AC
Line
Converter
+
Bulk
Storage
Capacitor
Load
Figure 22. Typical Circuit Without PFC
This technique results in a high harmonic content and in
poor power factor ratios. In effect, the simple rectification
technique draws power from the mains when the
instantaneous ac voltage exceeds the capacitor voltage. This
occurs near the line voltage peak and results in a high charge
current spike. Consequently, a poor power factor (in the
range of 0.5 -- 0.7) is generated, resulting in an apparent input
power that is much higher than the real power.
REGULATION SECTION
Connecting a resistor between the output voltage to be
regulated and the Pin 1, a feedback current is obtained.
Typically, this current is built by connecting a resistor
between the output voltage and the Pin 1. Its value is then
given by the following equation:
Vpk
Rectified DC
0
I
Line Sag
0
Figure 23. Line Waveforms Without PFC
Active solutions are the most popular way to meet the
legislation requirements. They consist of inserting a PFC
pre--regulator between the rectifier bridge and the bulk
capacitor. This interface is, in fact, a step--up SMPS that
outputs a constant voltage while drawing a sinusoidal
current from the line.
pin1
Ro
Regulation Block Output
1.5 V
Io
Load
+
Vo − V
Converter
Bulk Storage
Capacitor
MC33260
AC
Line
PFC Preconverter
High Frequency
Bypass Capacitor
Rectifiers
=
where:
Ro is the feedback resistor,
Vo is the output voltage,
Vpin1 is the Pin 1 clamp value.
The feedback current is compared to the reference current
so that the regulation block outputs a signal following the
characteristic depicted in Figure 25. According to the power
and the input voltage, the output voltage regulation level
varies between two values (Vo)regL and (Vo)regH
corresponding to the IregL and IregH levels.
AC Line Voltage
AC Line Current
pin1
IregL
(97%Iref)
IregH
(Iref)
Figure 25. Regulation Characteristic
Figure 24. PFC Preconverter
The feedback resistor must be chosen so that the feedback
current should equal the internal current source IregH when
the output voltage exceeds the chosen upper regulation
voltage [(Vo)regH].
The MC33260 was developed to control an active solution
with the goal of increasing its robustness while lowering its
global cost.
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9
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
Consequently:
Ro =
V o
where:
Vo is the output voltage,
Ro is the feedback resistor,
Vpin1 is the Pin 1 clamp voltage.
In practice, Vpin1 that is in the range of 2.5 V, is very small
compared to Vo. The equation can then be simplified by
neglecting Vpin1:
−V
regH
pin1
I
regH
In practice, Vpin1 is small compared to (Vo)regH and this
equation can be simplified as follows (IregH being also
replaced by its typical value 200 mA
R o ≈ 5 × V o
regH
(kΩ)
I
The regulation block output is connected to the Pin 2
through a 300 kΩ resistor. The Pin 2 voltage (Vcontrol) is
compared to the oscillator sawtooth for PWM control.
An external capacitor must be connected between Pin 2
and ground, for external loop compensation. The bandwidth
is typically set below 20 Hz so that the regulation block
output should be relatively constant over a given ac line
cycle. This integration that results in a constant on--time over
the ac line period, prevents the mains frequency output
ripple from distorting the ac line current.
C
0
=C +C
T
int
1
0
t on =
15 pF
The oscillator charge current is dependent on the feedback
current (Io). In effect
I2
=2× o
charge
I
ref
t onmax =
where:
Icharge is the oscillator charge current,
Io is the feedback current (drawn by Pin 1),
Iref is the internal reference current (200 mA
So, the oscillator charge current is linked to the output
voltage level as follows:

×V
I
control
ch
R2
o×I
ref
×C
pin3
2 × V2
o
×V
control
C
pin3
× R2
o×I
ref

× V
2 × V2
o

control max
This equation can be simplified replacing
[(Vcontrol)2max * Iref] by Kosc
Refer to Electrical Characteristics, Oscillator Section.
Then:
2
2
C
× Ro
t on max = pin3
2 × Vo − V
pin1
R2
o×I
pin3
One can notice that the on--time depends on Vo
(preconverter output voltage) and that the on--time is
maximum when Vcontrol is maximum (1.5 V typically).
At a given Vo, the maximum on--time is then expressed by
the following equation:
Figure 26. Oscillator

C
where:
ton is the on--time,
Cpin3 is the total oscillator capacitor (sum of the
internal and external capacitor),
Icharge is the oscillator charge current (Pin 3 current),
Vcontrol is the Pin 2 voltage (regulation block output).
Consequently, replacing Icharge by the expression given in
the Oscillator Section:
Output_Ctrl
3
=
pin3
t on =
CT
charge
ref
The MC33260 operates in voltage mode: the regulation
block output (Vcontrol -- Pin 2 voltage) is compared to the
oscillator sawtooth so that the gate drive signal (Pin 7) is
high until the oscillator ramp exceeds Vcontrol.
The on--time is then given by the following equation:
Icharge = 2 ¢ Io ¢ Io / Iref
I
R2
o×I
PWM LATCH SECTION
The oscillator consists of three phases:
 Charge Phase: The oscillator capacitor voltage grows
up linearly from its bottom value (ground) until it
exceeds Vcontrol (regulation block output voltage). At
that moment, the PWM latch output gets low and the
oscillator discharge sequence is set.
 Discharge Phase: The oscillator capacitor is abruptly
discharged down to its valley value (0 V).
 Waiting Phase: At the end of the discharge sequence,
the oscillator voltage is maintained in a low state until
the PWM latch is set again.
I
2 × V2
o
It must be noticed that the oscillator terminal (Pin 3) has
an internal capacitance (Cint) that varies versus the Pin 3
voltage. Over the oscillator swing, its average value
typically equals 15 pF (min 10 pF, max 20 pF).
The total oscillator capacitor is then the sum of the internal
and external capacitors.
OSCILLATOR SECTION
1
charge
≈
K osc × V 2
o
ref
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10
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
Zero Current Detection
This equation shows that the maximum on--time is inversely
proportional to the squared output voltage. This property is
used for follower boost operation (refer to Follower Boost
section).
The Zero Current Detection function guarantees that the
MOSFET cannot turn on as long as the inductor current
hasn’t reached zero (discontinuous mode).
The Pin 4 voltage is simply compared to the (--60 mV)
threshold so that as long as Vcs is lower than this threshold,
the circuit gate drive signal is kept in low state.
Consequently, no power MOSFET turn on is possible until
the inductor current is measured as smaller than (60 mV/Rcs)
that is, the inductor current nearly equals zero.
CURRENT SENSE BLOCK
The inductor current is converted into a voltage by
inserting a ground referenced resistor (Rcs) in series with the
input diodes bridge (and the input filtering capacitor).
Therefore a negative voltage proportional to the inductor
current is built:
V cs = -- R cs × I

L
Iocp (205 mA)
D1...D4
where:
IL is the inductor current,
Rcs is the current sense resistor,
Vcs is the measured Rcs voltage.
1
0
ROCP
Inductor Current Power Switch Drive
Rcs
VOCP
S
Output_Ctrl
--60 mV
4
LEB
+
--
PWM
Latch
Output_Ctrl
R
Q
R
To Output Buffer
(Output_Ctrl Low <=> Gate Drive in Low State)
Figure 28. Current Sense Block
Time
Overcurrent Protection
Rcs Voltage
During the power switch conduction (i.e. when the Gate
Drive Pin voltage is high), a current source is applied to the
Pin 4. A voltage drop VOCP is then generated across the
resistor ROCP that is connected between the sense resistor
and the Current Sense Pin (refer to Figure 28). So, instead
of Vcs, the sum (Vcs + VOCP) is compared to (--60 mV) and
the maximum permissible current is the solution of the
following equation:
-- R cs × Ipk max + V
Pin 4 Voltage
VOCP
OCP
= --60 mV
where:
Ipkmax is maximum allowed current,
Rcs is the sensing resistor.
The overcurrent threshold is then:
--60 mV
Zero Current Detection
Ipk max =
VOCP = ROCP ¢ IOCP
An overcurrent is detected if Vpin4 crosses the threshold (--60 mV)
during the Power Switch on state
ROCP × IOCP + 60 × 10 --3
R cs
where:
ROCP is the resistor connected between the pin and the
sensing resistor (Rcs),
IOCP is the current supplied by the Current Sense Pin
when the gate drive signal is high (power switch
conduction phase). IOCP equals 205 mA typically.
Practically, the VOCP offset is high compared to 60 mV
and the precedent equation can be simplified. The maximum
current is then given by the following equation:
Figure 27. Current Sensing
The negative signal Vcs is applied to the current sense
through a resistor ROCP. The pin is internally protected by a
negative clamp (--0.7 V) that prevents substrate injection.
As long as the Pin 4 voltage is lower than (--60 mV), the
Current Sense comparator resets the PWM latch to force the
gate drive signal low state. In that condition, the power
MOSFET cannot be on.
During the on--time, the Pin 4 information is used for the
overcurrent limitation while it serves the zero current
detection during the off time.
Ipk max ≈
R
(kΩ)
OCP
× 0.205 (A)
R cs(Ω)
Consequently, the ROCP resistor can program the OCP level
whatever the Rcs value is. This gives a high freedom in the
choice of Rcs. In particular, the inrush resistor can be utilized.
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11
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
VCC
Th--Stdwn
Synchronization
Arrangement
5
S
OVP, UVP
Current Sense
Comparator
--
Output
Buffer
Q
7
PWM
Latch
ZCD & OCP
R
+
&
Output_Ctrl
--60 mV
+
Q
--
PWM Latch
Comparator
Vcontrol (Vpin2 -- Regulation Output)
Oscillator Sawtooth
Figure 29. PWM Latch
A LEB (Leading Edge Blanking) has been implemented.
This circuitry disconnects the Current Sense comparator
from Pin 4 and disables it during the 400 first ns of the power
switch conduction. This prevents the block from reacting on
the current spikes that generally occur at power switch turn
on. Consequently, proper operation does not require any
filtering capacitor on Pin 4.
Practically, Vpin1 that is in the range of 2.5 V, can be
neglected. The equation can then be simplified:
PROTECTIONS
where IovpL is the internal low OVP current threshold.
Consequently, Vpin1 being neglected:
V
(mA) (V)

V
ovpL
= R o(MΩ) × I

(mA) (V)
ovpL
The OVP hysteresis prevents erratic behavior.
IovpL is guaranteed to be higher than IregH (refer to
parameters specification). This ensures that the OVP
function doesn’t interfere with the regulation one.
OVP (Overvoltage Protection)
The feedback current (Io) is compared to a threshold
current (IovpH). If it exceeds this value, the gate drive signal
is maintained low until this current gets lower than a second
level (IovpL).
UVP (Undervoltage Protection)
This function detects when the feedback current is lower
than 14% of Iref. In this case, the PWM latch is reset and the
power switch is kept off.
This protection is useful to:
 Protect the preregulator from working in too low
mains conditions.
 To detect the feedback current absence (in case of a
nonproper connection for instance).
The UVP threshold is:
Gate
Drive
Enable
Vcontrol
Io
IregL IregH IovpL IovpH
V uvp ≈ V
Figure 30. Internal Current Thresholds
pin1
+ R o(MΩ) × Iuvp(mA) (V)
Practically (Vpin1 being neglected),
So, the OVP upper threshold is:

ovpH
V ovpL = V pin1 + R o × I ovpL
Refer to Current Sense Block.
V ovpH = V pin1 + R o × I ovpH
= R o(MΩ) × I
On the other hand, the OVP low threshold is:
OCP (Overcurrent Protection)
Iuvp
ovpH
V uvp = R o(MΩ) × I uvp(mA) (V)

Maximum On--Time Limitation
where:
Ro is the feedback resistor that is connected between
Pin 1 and the output voltage,
IovpH is the internal upper OVP current threshold,
Vpin1 is the Pin 1 clamp voltage.
As explained in PWM Latch, the maximum on--time is
accurately controlled.
Pin Protection
All the pins are ESD protected.
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MC33260
Pin Numbers are Relevant to the PDIP--8 Version
In particular, a 11 V Zener diode is internally connected
between the terminal and ground on the following pins:
Sync
Feedback, Vcontrol, Oscillator, Current Sense, and
Synchronization.
+
5
1V
S1
--
Q1
Rsync
UVLO
Q1 High <=>
Synchronization Mode
R2
2 ms
&
PWM
Latch
Set
S2
Q2
1V
R2
Output_Ctrl
Figure 31. Synchronization Arrangement
SYNCHRONIZATION BLOCK
OUTPUT SECTION
The MC33260 features two modes of operation:
 Free Running Discontinuous Mode: The power switch
is turned on as soon as there is no current left in the
inductor (Zero Current Detection). This mode is
simply obtained by grounding the synchronization
terminal (Pin 5).
 Synchronization Mode: This mode is set as soon as a
signal crossing the 1.0 V threshold, is applied to the
Pin 5. In this case, operation in free running can only
be recovered after a new circuit startup. In this mode,
the power switch cannot turn on before the two
following conditions are fulfilled.
-- Still, the zero current must have been detected.
-- The precedent turn on must have been followed by (at
least) one synchronization raising edge crossing the
1.0 V threshold.
In other words, the synchronization acts to prolong the
power switch off time.
Consequently, a proper synchronized operation requires
that the current cycle (on--time + inductor demagnetization)
is shorter than the synchronization period. Practically, the
inductor must be chosen accordingly. Otherwise, the system
will keep working in free running discontinuous mode.
Figure 36 illustrates this behavior.
It must be noticed that whatever the mode is, a 2.0 ms
minimum off--time is forced. This delay limits the switching
frequency in light load conditions.
The output stage contains a totem pole optimized to
minimize the cross conduction current during high speed
operation. The gate drive is kept in a sinking mode whenever
the Undervoltage Lockout is active. The rise and fall times
have been controlled to typically equal 50 ns while loaded
by 1.0 nF.
REFERENCE SECTION
An internal reference current source (Iref) is trimmed to be
4% accurate over the temperature range (the typical value
is 200 mA). Iref is the reference used for the regulation
(IregH = Iref).
UNDERVOLTAGE LOCKOUT SECTION
An Undervoltage Lockout comparator has been
implemented to guarantee that the integrated circuit is
operating only if its supply voltage (VCC) is high enough to
enable a proper working. The UVLO comparator monitors
the Pin 8 voltage and when it exceeds 11 V, the device gets
active. To prevent erratic operation as the threshold is
crossed, 2.5 V of hysteresis is provided.
The circuit off state consumption is very low: in the range
of 100 mA @ VCC = 5.0 V. This consumption varies versus
VCC as the circuit presents a resistive load in this mode.
THERMAL SHUTDOWN
An internal thermal circuitry is provided to disable the
circuit gate drive and then to prevent it from oscillating, if
the junction temperature exceeds 150C typically.
The output stage is again enabled when the temperature
drops below 120C typically (30C hysteresis).
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MC33260
Pin Numbers are Relevant to the PDIP--8 Version
FOLLOWER BOOST
of the follower boost: it allows the use of smaller, lighter and
cheaper inductors compared to traditional systems.
Finally, this technique utilization brings a drastic system
cost reduction by lowering the size and then the cost of both
the inductor and the power switch.
Traditional PFC preconverters provide the load with a fixed
and regulated voltage that generally equals 230 V or 400 V
according to the mains type (U.S., European, or universal).
In the “Follower Boost” operation, the preconverter
output regulation level is not fixed but varies linearly versus
the ac line amplitude at a given input power.
IL
traditional preconverter
follower boost preconverter
Ipk
Traditional Output
Vo (Follower Boost)
time
Vin
Vin
Vac
Vin
Vin
IL
IL
Vout
Load
the power switch is on
the power switch is off
Figure 33. Off--Time Duration Increase
Figure 32. Follower Boost Characteristics
This technique aims at reducing the gap between the
output and the input voltages to minimize the boost
efficiency degradation.
Follower Boost Implementation
In the MC33260, the on--time is differently controlled
according to the feedback current level. Two areas can be
defined:
 When the feedback current is higher than IregL (refer
to regulation section), the regulation block output
(Vcontrol) is modulated to force the output voltage to a
desired value.
 On the other hand, when the feedback current is lower
than IregL, the regulation block output and therefore,
the on--time are maximum. As explained in PWM
Latch Section, the on--time is then inversely
proportional to the output voltage square. The
Follower Boost is active in these conditions in which
the on--time is simply limited by the output voltage
level. Note: In this equation, the Feedback Pin voltage
(Vpin1) is neglected compared to the output voltage
(refer to the PWM Latch Section).
Follower Boost Benefits
The boost presents two phases:
 The on--time during which the power switch is on. The
inductor current grows up linearly according to a slope
(Vin/Lp), where Vin is the instantaneous input voltage
and Lp the inductor value.
 The off--time during which the power switch is off.
The inductor current decreases linearly according the
slope (Vo -- Vin) / Lp, where Vo is the output voltage.
This sequence that terminates when the current equals
zero, has a duration that is inversely proportional to the
gap between the output and input voltages.
Consequently, the off--time duration becomes longer
in follower boost.
Consequently, for a given peak inductor current, the
longer the off time, the smaller power switch duty cycle and
then its conduction dissipation. This is the first benefit of this
technique: the MOSFET on--time losses are reduced.
The increase of the off time duration also results in a
switching frequency diminution (for a given inductor
value). Given that in practise, the boost inductor is selected
big enough to limit the switching frequency down to an
acceptable level, one can immediately see the second benefit
t on = t on max =
C
pin3
× R2
o
K osc × V 2
o
where:
Cpin3 is the total oscillator capacitor (sum of the
internal and external capacitors -- Cint + CT),
Kosc is the ratio (oscillator swing over oscillator gain),
Vo is the output voltage,
Ro is the feedback resistor.
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MC33260
Pin Numbers are Relevant to the PDIP--8 Version
On the other hand, the boost topology has its own rule that
dictates the on--time necessary to deliver the required power:
t on =
4 × Lp × P
V2
pk
(Pin)min
in
Pin
where:
Vpk is the peak ac line voltage,
Lp is the inductor value,
Pin is the input power.
Combining the two equations, one can obtain the
Follower Boost equation:
Vo =
Ro
×
2

Vo = Vpk
Regulation Block is Active
Vo
(Pin)max
non usable area
C
pin3
×V
pk
K osc × L p × P in
Vac
Consequently, a linear dependency links the output
voltage to the ac line amplitude at a given input power.
VacLL
Vac
VacHL
Figure 35. Follower Boost Output Voltage
Mode Selection
(Vac)max
Input Power
Output Voltage
The Regulation Block is Active
Vac
The operation mode is simply selected by adjusting the
oscillator capacitor value. As shown in Figure 35, the output
voltage first has an increasing linear characteristic versus the
ac line magnitude and then is clamped down to the
regulation value. In the traditional mode, the linear area
must be rejected. This is achieved by dimensioning the
oscillator capacitor so that the boost can deliver the
maximum power while the output voltage equals its
regulation level and this, whatever the given input voltage.
Practically, that means that whatever the power and input
voltage conditions are, the follower boost would generate
output voltages values higher than the regulation level, if
there was no regulation block.
In other words, if (Vo)regL is the low output regulation
level:
Output Voltage
Input Power
Pin
(Vac)min
Vo
ton = k/Vo2
ton
on--time
Figure 34. Follower Boost Characteristics
The behavior of the output voltage is depicted in
Figures 34 and 35. In particular, Figure 35 illustrates how
the output voltage converges to a stable equilibrium level.
First, at a given ac line voltage, the on--time is dictated by the
power demand. Then, the follower boost characteristic
makes correspond one output voltage level to this on--time.
Combining these two laws, it appears that the power level
forces the output voltage.
One can notice that the system is fully stable:
 If an output voltage increase makes it move away from
its equilibrium value, the on--time will immediately
diminish according to the follower boost law. This will
result in a delivered power decrease. Consequently,
the supplied power being too low, the output voltage
will decrease back,
 In the same way, if the output voltage decreases, more
power will be transferred and then the output voltage
will increase back.
V o
regL
≤
Ro
×
2

C +C
T
int
K osc × L p × P

in max
×V
pk
Consequently,
C T ≥ --C int +
2
4 × K osc × L p × P in max × V o regL
2
R2
o × V pk
Using IregL (regulation block current reference), this
equation can be simplified as follows:
C T ≥ --C int +
4 × K osc × L p × P
 max × I2
in
regL
V2
pk
In the Follower Boost case, the oscillator capacitor must
be chosen so that the wished characteristics are obtained.
Consequently, the simple choice of the oscillator
capacitor enables the mode selection.
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MC33260
Synchronization
Signal
Zero Current
Detection
2 ms
Delay
2 ms
2 ms
2 ms
2 ms
Vcontrol
Oscillator
Circuit
Output
205 mA
Ics
Inductor
Current
1
2
case no. 1: the turn on is delayed by the Zero Current Detection
cases no. 2 and no. 3: the turn on is delayed by the synchronization signal
case no. 4: the turn on is delayed by the minimum off--time (2 ms)
Figure 36. Typical Waveforms
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3
4
MC33260
MAIN DESIGN EQUATIONS (Note 3)
rms Input Current (Iac)
I ac =
 (preconverter efficiency) is generally in the
range of 90 -- 95%.
Po
η × Vac
Maximum Inductor Peak Current ((Ipk)max):
(Ipk)max is the maximum inductor current.
Output Voltage Peak to Peak 100Hz (120Hz) Ripple ((ΔVo)pk--pk):
fac is the ac line frequency (50 or 60Hz).
2 × 2 × (P o) max
(I ) max =
pk
η×V
acLL
Po
(ΔVo )
=
pk–pk
2π × f ac × C o × Vo
Inductor Value (Lp):
2×t×
Lp =

Vo
2
−V
acLL

t is the maximum switching period.
(t = 40 ms) for universal mains operation and
(t = 20ms) for narrow range are generally
used.
2
×V
acLL
Vo × V
× (I ) max
acLL
pk
Maximum Power MOSFET Conduction Losses ((pon)max):

(Pon ) max ≈ 1 × (Rds)on × (I ) max 2 × 1 −
pk
3
1.2 × V
acLL
Vo

(Rds)on is the MOSFET drain source on--time
resistor.
In Follower Boost, the ratio (VacLL/Vo) is
higher. The on--time MOSFET losses are then
reduced.
Maximum Average Diode Current (Id):
The Average Diode Current depends on the
power and on the output voltage.
Current Sense Resistor Losses (pRcs):
This formula indicates the required dissipation
capability for Rcs (current sense resistor).
(P ) max
(I ) max = o
d
(Vo) min
pR cs = 1 × (Rds)on × (I ) 2 max
pk
6
Over Current Protection Resistor (ROCP):
R
OCP
≈
R cs × (I
Oscillator External Capacitor Value (CT):
--Traditional Operation
2×K
C ≥−C +
T
int
-- Follower Boost:
Vo =
Ro
×
2
Feedback Resistor (Ro):
Ro =
pk
0.205
) max
(kΩ)
2
osc × L p × (Pin ) max × I regL
V 2ac

C +C
T
int
K osc × L p × P
in
The overcurrent threshold is adjusted by ROCP
at a given Rcs.
Rcs can be a preconverter inrush resistor.
The Follower Boost characteristic is adjusted
by the CT choice.
The Traditional Mode is also selected by CT.
Cint is the oscillator pin internal capacitor.
×V
pk
(Vo ) reg − VFB
V
≈ o
200
I
regH
(MΩ)
3. The preconverter design requires the following characteristics specification:
-- (Vo)reg: desired output voltage regulation level
-- (ΔVo)pk--pk: admissible output peak to peak ripple voltage
-- Po: desired output power
-- Vac: ac rms operating line voltage
-- VacLL: minimum ac rms operating line voltage
-- VFB: Feedback Pin voltage
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17
The output voltage regulation level is adjusted
by Ro.
MC33260
L1
1N4007
D1
90 to
270 Vac
EMI
Filter
D2
D3
C1
330 nF
500 Vdc
D4
320 mH
D5
MUR460E
R1
1 MΩ
0.25 W
Q1
MTP4N50E
+
80 W Load
(SMPS, Lamp
Ballast,...)
C2
47 mF
450 V
R2
1 MΩ
0.25 W
R4
R3
15 kΩ/0.25 W
1 Ω/2 W
R5
22 Ω/0.25 W
Feedback
Input
Io
Vreg
Vreg
Vcontrol
C3
680 nF
Io
Io
Feedback
Block
1.5 V
Iref
Vprot
Regulation
Block
300 k
UVP, OVP
Io
(-- -- --)
Iuvp
IovpL IovpH
Io
97%.Iref
Iref
Iref
Vref
Iref
MC33260
REGULATOR
--
Enable
+
11 V/8.5 V
VCC
Vprot
ThStdwn
Output
Buffer
PWM Comp
Oscillator
I osc–ch =
C4
330 pF
Gnd
+
2x|0x|0
I ref
R
-Iocp (205 mA)
CT
0
1
1
0
--60 mV
15 pF
Q
PWM
Latch
Current
Sense
Block
S
Q
Output
+
Synchro
Synchronization
Block
--
LEB
Output
Drive
L1: Coilcraft N2881 -- A (primary: 62 turns of # 22 AWG -- Secondary: 5 turns of # 22 AWG Core: Coilcraft PT2510, EE 25
L1: Gap: 0.072 total for a primary inductance (Lp) of 320 mH)
Figure 37. 80 W Wide Mains Power Factor Corrector
POWER FACTOR CONTROLLER TEST DATA*
AC Line Input
Current Harmonic Distortion (% Ifund)
Vrms
(V)
Pin
(W)
PF
(--)
Ifund
(mA)
THD
H2
H3
H5
H7
DC Output
H9
Vo
(V)
ΔVo
(V)
Io
(mA)
Po
(W)

(%)
90
88.2
0.991
990
8.1
0.07
5.9
4.3
1.5
1.7
181
31.2
440
79.6
90.2
110
86.3
0.996
782
7.0
0.05
2.7
5.7
1.1
0.8
222
26.4
360
79.9
92.6
135
85.2
0.995
642
8.2
0.03
1.5
6.8
1.1
1.5
265
20.8
300
79.5
93.3
180
87.0
0.994
480
9.5
0.16
4.0
6.5
3.1
4.0
360
16.0
225
81.0
93.1
220
84.7
0.982
385
15
0.5
8.4
7.8
5.3
1.9
379
14.0
210
79.6
94.4
240
85.3
0.975
359
16.5
0.7
9.0
7.8
7.4
3.8
384
14.0
210
80.6
94.5
260
84.0
0.967
330
18.8
0.7
11.0
7.0
9.0
4.0
392
13.2
205
80.4
95.7
*Measurements performed using Voltech PM1200 ac power analysis.
http://onsemi.com
18
MC33260
Rstup
D1...D4
15 V
2
3
8
MC33260
1
4
r
+
Cpin8
VCC
+
7
6
5
PDIP--8 CONFIGURATION SHOWN
Figure 38. Circuit Supply Voltage
MC33260 VCC SUPPLY VOLTAGE
When the PFC preconverter is loaded by an SMPS, the
MC33260 should preferably be supplied by the SMPS itself.
In this configuration, the SMPS starts first and the PFC gets
active when the MC33260 VCC supplied by the power
supply, exceeds the device startup level. With this
configuration, the PFC preconverter doesn’t require any
auxiliary winding and finally a simple coil can be used.
In some applications, the arrangement shown in Figure 38
must be implemented to supply the circuit. A startup resistor
is connected between the rectified voltage (or one--half
wave) to charge the MC33260 VCC up to its startup
threshold (11 V typically). The MC33260 turns on and the
VCC capacitor (Cpin8) starts to be charged by the PFC
transformer auxiliary winding. A resistor, r (in the range of
22 Ω) and a 15 V Zener should be added to protect the circuit
from excessive voltages.
PCB LAYOUT
The connections of the oscillator and Vcontrol capacitors
should be as short as possible.
Preconverter Output
2
3
4
8
MC33260
1
7
6
+
+
+
+
VCC
+
+
+
5
SMPS Driver
DIP--8 CONFIGURATION SHOWN
Figure 39. Preconverter Loaded by a Flyback SMPS: MC33260 VCC Supply
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19
MC33260
ORDERING INFORMATION
Package
Shipping†
MC33260PG
PDIP--8
(Pb--Free)
50 Units / Rail
MC33260DG
SOIC--8
(Pb--Free)
98 Units / Rail
MC33260DR2G
SOIC--8
(Pb--Free)
2500 Units / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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20
MC33260
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626--05
ISSUE M
D
A
D1
8
E
5
E1
1
4
NOTE 5
F
c
E2
END VIEW
TOP VIEW
NOTE 3
e/2
A
L
A1
C
SEATING
PLANE
E3
e
8X
SIDE VIEW
b
0.010
M
C A
END VIEW
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21
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSION E IS MEASURED WITH THE LEADS RESTRAINED PARALLEL AT WIDTH E2.
4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
A1
b
C
D
D1
E
E1
E2
E3
e
L
INCHES
NOM
MAX
-------- 0.210
--------------0.018 0.022
0.010 0.014
0.365 0.400
--------------0.310 0.325
0.250 0.280
0.300 BSC
--------------- 0.430
0.100 BSC
0.115 0.130 0.150
MIN
-------0.015
0.014
0.008
0.355
0.005
0.300
0.240
MILLIMETERS
MIN
NOM
MAX
--------------5.33
0.38
--------------0.35
0.46
0.56
0.20
0.25
0.36
9.02
9.27 10.02
0.13
--------------7.62
7.87
8.26
6.10
6.35
7.11
7.62 BSC
--------------- 10.92
2.54 BSC
2.92
3.30
3.81
MC33260
PACKAGE DIMENSIONS
SOIC--8
CASE 751--07
ISSUE AJ
--X--
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751--01 THRU 751--06 ARE OBSOLETE. NEW
STANDARD IS 751--07.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
--Y--
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
--Z--
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm 
inches
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GreenLine is a trademark of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303--675--2175 or 800--344--3860 Toll Free USA/Canada
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC33260/D
AND8016/D
Design of Power Factor
Correction Circuit Using
Greenline Compact Power
Factor Controller MC33260
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Prepared by
Ming Hian Chew
ON Semiconductor Analog Applications Engineering
APPLICATION NOTE
Introduction
The MC33260 is an active power factor controller that
functions as a boost pre–converter which, meeting
international standard requirement in electronic ballast and
off–line power supply application. MC33260 is designed to
drive a free running frequency discontinuous mode, it can
also be synchronized and in any case, it features very
effective protections that ensure a safe and reliable
operation.
This circuit is also optimized to offer extremely compact
and cost effective PFC solutions. It does not entail the need
of auxiliary winding for zero current detection hence a
simple coil can be used instead of a transformer if the
MC33260 Vcc is drawn from the load (please refer to page
19 of the data sheet). While it requires a minimum number
D1
D3
D2
D4
of external components, the MC33260 can control the
follower boost operation that is an innovative mode
allowing a drastic size reduction of both the inductor and the
power switch. Ultimately, the solution system cost is
significantly lowered.
Also able to function in a traditional way (constant output
voltage regulation level), any intermediary solutions can be
easily implemented. This flexibility makes it ideal to
optimally cope with a wide range of applications.
This application note will discuss on the design of power
factor correction circuit with MC33260 with traditional
boost constant output voltage regulation level operation and
follower boost variable output voltage regulation level
operation. For derivation of the design equations related to
the IC please refer to MC33260 data sheet.
R6
D5
R7
C1
L1
+
D7
C4
D5
1
8
2
7
+
C5
R5
Q1
MC33260
C2
R2
3
6
4
5
C3
R1
R3
R4
C6
Figure 1. Application Schematic of MC33260
PFC Techniques
Many PFC techniques have been proposed, boost
topology, which can operate in continuous and
discontinuous mode, is the most popular. Typically,
continuous mode is more favorable for high power
application for having lower peak current. On the other
hand, for less than 500 W application, discontinuous mode
offers smaller inductor size, minimal parts count and lowest
 Semiconductor Components Industries, LLC, 2002
June, 2002 – Rev. 1
cost. This paper will discuss design of PFC with MC33260,
which operates in critical conduction mode.
Discontinuous Conduction Mode Operation
Critical conduction mode operation presents two major
advantages in PFC application. For critical conduction
mode, the inductor current must fall to zero before start the
next cycle. This operation results in higher efficiency and
1
Publication Order Number:
AND8016/D
AND8016/D
eliminates boost rectifier reverse recovery loss as MOSFET
cannot turn–on until the inductor current reaches zero.
Secondly, since there are no dead–time gaps between
cycles, the ac line current is continuous thus limiting the
peak switch to twice the average input current. The
converter works right on critical conduction mode, which
results in variable frequency operation.
I
where
inpk
2 I
(5)
inrms
Input power of the PFC circuit, Pin can be expressed in
following equation, by substituting equation (3) and (5).
P V
I
in
inrms inrms
V
inpk
2
I
V
I
inpk inpk
inpk
2
2
(6)
The output power, Po is given by:
Inductor Waveform
Po V oI o ηP
in
V di
L
dt
(1)
PFC circuit efficiency is needed in the design equation, for
low line operation, it is typically set at 92% while 95% for
high line operation. Substituting equation (6) into
equation (7),
Equation (1) is the center of the operation of PFC boost
converter where V=Vin(t), the instantaneous voltage across
the inductor. Assuming the inductance and the on–time over
each line half–cycle are constant, di is actually the peak
current, ILpk, this is because the inductor always begins
charging at zero current.
I
Iin(t)
I
inpk
2 P
2Po
o
ηV
ηV
inpk
inrms
(9)
L(avg)
I
(10)
in
It has been understood that peak inductor current, ILpk is
exactly twice the average inductor current, IL(avg) for critical
conduction operation.
ON
OFF
I
I
inpk
2 V
t
(3)
2 2 Po
ηV
inrms
(11)
Lpk
2 2 Po
ηV
ac(LL)
(12)
(on)
I
L
P
Lpk Vinpk
(13)
Substituting equation (3) and (12) into equation (13),
results in:
Instantaneous Input Current, Iin(t)
Peak Input Current, Iinpk,
Both Iin(t) and Iinpk are related by below equation
I (t) I
sin(ωt),
in
inpk
L(avg)
On–time
By solving inductor equation (1), on–time required to
charge the inductor to the correct peak current is:
(2)
inrms
2I
Switching Time
In theory, the on–time, t(on) is constant. In practice, t(on)
tends to increase at the ac line zero crossings due to the
charge on output capacitor Cout. Let Vac = Vac(LL) for initial
t(on) and t(off) calculations.
PFC Power Section Design
Instantaneous Input Voltage, Vin(t)
Peak Input Voltage, Vinpk
Both Vin(t) and Vinpk are related by below equation
V (t) V
sin(ωt)
in
inpk
Lpk
Since ILpk is maximum at minimum required ac line
voltage, Vac(LL),
Design Criteria
The basic design specification concerns the following:
• Mains Voltage Range: Vac(LL) – Vac(HL)
• Regulated DC Output Voltage: Vo
• Rated Output Power: Po
• Expected Efficiency, V
(8)
The average input current is equal to average inductor
current, IL(avg),
Figure 2. Inductor Waveform
where
V
I
inpk inpk
2
Express the above equation in term of Iinpk,
IL(t)
Iinpk
MOSFET
Po ηP η
in
Vin(t)
Vinpk
ILpk
(7)
t
(on)
(4)
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2
2 2 Po
ηV
ac(LL)
L
P
2 Vac(LL)
2Po L
P
ηV 2ac(LL)
(14)
AND8016/D
Off–time
The instantaneous switch off–time varies with the line and
load conditions, as well as with the instantaneous line
voltage. Off–time is analyzed by solving equation (1) for the
inductor discharging where the voltage across the inductor
is Vo minus Vin.
t
(off)
Multiplying nominator
Vinpksin(t) results in:
t
(15)
and
denominator
total
with
total
L
Lpk P
V
sin(ωt)
t
inpk
(on)
(16)
t
(off)
Vo V
sin(ωt)
Vo
inpk
1
2 Vinpk sin(θ)
V
sin(ωt)
inpk
I
(off)min
L
Lpk P
,θ 0°
Vo
Lp t
(on)
1
t
(off)
(off)max
2Po L
P
ηV 2ac(LL)
L
Lpk P
, (θ) 90°
Vo V
inpk
2
(23)
2 V P
o o
o Vac(LL) Vac(LL)
V
total
2
(24)
Vo I
Lpk
Let the switching cycle t = 40s for universal input (85 to
265 Vac) operation and 20 s for fixed input (92 to 138 Vac,
or 184 to 276 Vac) operation.
(17)
Inductor Design Summary
The required energy storage of the boost inductor is:
2
W 1L I
L
2 P Lpk
(25)
The number of turns required for a selected core size and
material is:
(18)
L I
10 6
P Lpk
N P
B maxA e
(26)
where Bmax is in Teslas and Ae is in square millimeters
(mm2)
The required air gap to achieve the correct inductance and
storage is expressed by:
l gap 2
410 7 N p A e
mm
L
P
(27)
Design of Auxiliary Winding
MC33260 does not entail an auxiliary winding for zero
current detection. Hence if DC voltage can be tapped from
the SMPS or electronic ballast connected to the output of
PFC, this step can be skipped. Then an inductor is what it
needs.
The auxiliary winding exhibits a low frequency ripple
(100–120 Hz). The Vcc capacitor must be large enough
(about 47 F) to minimize voltage variations. As a rule of
thumb, you can use the below equation to estimate the
auxiliary turn number:
(19)
I
t
(22)
V
Lp Inductor Value
Maximum on–time needs to be programmed into the PFC
controller timing circuit. Both t(on)max and t(off)max will be
individually calculated and added together to obtain the
maximum conversion period, ttotal. This is required to obtain
the inductor value.
(on)max
o Vac(LL) ηV2ac(LL)
total
2t
Switching frequency changes with the steady state line
and load operating conditions along with the instantaneous
input line voltage. Typically, the PFC converter is designed
to operate above the audible range after accommodating all
circuit and component tolerances. 25 kHz is a good first
approximation. Higher frequency operation that can
significantly reduce the inductor size without negatively
impacting efficiency or cost should also be evaluated.
The minimum switching frequency occurs at the peak of
the ac line voltage. As the ac line voltage traverses from peak
to zero, t(off) approaches zero producing an increase in
switching frequency.
t
Equation (23) can be rewritten by substituting rearranged
equation (12) in term of √2Po.
Switching Frequency
f
(21)
(off)max
2 P L V
o P o
V
2
V ac(LL) η o V
ac(LL)
2
t
where t = The off–time, t(off) is greatest at the peak of the ac line
voltage and approaches zero at the ac line zero crossings.
Theta () represents the angle of the ac line voltage.
The off–time is at a minimum at ac line crossings. This
equation is used to calculate t(off) as Theta approaches zero.
t
(on)max
By rearranging in term of Lp,
I
t
t
Equation (21) becomes
I
t
L
Lpk P
Vo V
sin(ωt)
inpk
The exact inductor value can be determined by solving
equation (21) by substituting equation (19) and (20) at the
selected minimum operating frequency.
Naux (20)
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3
Np Vaux
Np Vaux
Vo Vac(HL)
VL
(28)
AND8016/D
The MC33260 VCC maximum voltage being 16 V, one
must add a resistor (in the range of 22 ) and a 15 V zener
to protect the circuit against excessive voltages. Vaux should
be chosen above the Under–Voltage Lockout threshold
(10 V) and below the zener voltage.
Overcurrent protection resistor, ROCP can be determined
with below equation:
Selection of Output Capacitor
The choice of output capacitance value is dictated by the
required hold–up time, thold or the acceptable output ripple
voltage, Vorip for a given application. As a rule of thumb, can
start with 1 F/watt.
Current Limiting With Boost Topology Power
Factor Correction Circuit
Unlike buck and flyback circuits, because there is no
series switch between input and output in the boost topology,
high current occurring with the start–up inrush current surge
charging the bulk capacitor and fault load conditions cannot
be limited or controlled without additional circuitry.
The MC33260 Zero Current Detection uses the current
sensing information to prevent any power switch turn on as
long as some current flows through the inductor. Then,
during start–up, the power MOSFET is not allowed to turn
on while in–rush current flows. Then there is no risk to have
the power switch destroyed at start–up because of the
in–rush current.
In the same way, in an overload case, the power MOSFET
is kept off as long as there is a direct output capacitor charge
current, i.e., when the input voltage is higher than the output
voltage. Consequently, overload working is fully safe for the
power MOSFET. This is one of the major advantages
compared to MC33262 and competition.
R
OCP
Selection of Semiconductors
Maximum currents and voltages must first be determined
for over all operating conditions to select the MOSFET and
boost rectifier. As a rule of thumb, derate all semiconductors
to about 75–80% of their maximum ratings. This implying
the need of devices with at least 500 V breakdown voltage.
Bipolar transistors are an acceptable alternative to MOSFET
if the switching frequency is maintained fairly low. High
voltage diodes with recovery times of 200 ns, or less should
be used for the boost rectifier. One series of the popular
devices is the MURXXX Ultrafast Rectifier Series from
ON Semiconductor.
Maximum power MOSFET conduction losses.
2
P
1R
I
1
(on)max
ds(on)
Lpk
6
1.2 V
ac(LL) (29)
Vo
2 K osc L P V 2
P
in
o C
int
2
2
V ac(LL) R o
(30)
Design of Regulation and Overvoltage
Protection Circuit
The output voltage regulation level can be adjusted by Ro,
Vo
Ro 200 A
(31)
Designing the Current Sense Circuit
The inductor current is converted into a voltage by
inserting a ground referenced resistor, RCS in series with the
input diode bridge. Therefore a negative voltage
proportional to the inductor current is built.
The current sense resistor losses, PRcs:
2
P
1R
I Lpk
Rcs
CS
6
(33)
Current Limiting for Start–up Inrush
Initially Vo is zero, when the converter is turned on, the
bulk capacitor will charge resonantly to twice Vin. The
voltage can be as high as 750 V if Vin happens to be at the
peak high–line 265 V condition (375 V). The peak resonant
charging current through the inductor will be many times
greater than normal full load current. the inductor must be
designed to be much larger and more expensive to avoid
saturation. The boost shunt switch cannot do anything to
prevent this and could be worse if turned on during start–up.
The inrush current and voltage overshoot during the
start–up phase is intolerable. A fuse is not suitable, as it will
blow each time the supply is turned on.
There are several methods that may be used to solve the
start–up problem:
Designing the Oscillator Circuit
For traditional boost operation, CT is chosen with below
equation:
C T
R I
Lpk
CS
I
OCP
1. Start–up Bypass Rectifier
This is implemented by adding an additional rectifier
bypassing the boost inductor. The bypass rectifier will divert
the start–up inrush current away from the boost inductor as
shown in Figure 3. The bulk capacitor charges through
Dbypass to the peak AC line voltage without resonant
overshoot and without excessive inductor current. Dbypass is
(32)
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4
AND8016/D
• Regulated DC Output Voltage: Vo = 400 Vdc
• Rated Output Power: Po = 80 W
• Expected Efficiency, > 90%
reverse–biased under normal operating conditions. If load
overcurrent pulls down Vo, Dbypass conducts, but this is
probably preferable to having the high current flowing
through boost inductor.
A. The input power, Pin is given by
Dbypass
PFC
IC
P
P o 80 86.96 W
in
0.92
η
+
B. Input diode current is maximum at
Vinrms = Vac(LL)
VOUT
VAC
I
inpk
2 P
o 2 80 1.447 A
0.92 85
ηV
ac(LL)
C. Inductor design
1. Inductor peak current:
Figure 3. Rectifier bypass of start–up inrush current
I
2. External Inrush Current Limiting Circuit
For low power system, a thermistor in series with the
pre–converter input will limit the inrush current. Concern is
the thermistor may not respond fast enough to provide
protection after a line dropout of a few cycles.
A series input resistor shunted by a Triac or SCR is a more
efficient approach. A control circuit is necessary. This
method can function on a cycle–by–cycle basis for
protection after a dropout.
Lpk
2I
inpk
2 1.447 2.894 A
2. Inductor value:
2t
Lp o Vac(LL) Vac(LL)
V
total
2
Vo I
Lpk
2 40 10 6
400
2
85 85
400 2.894
1.162 mH
Let the switching cycle t = 40 s for universal input (85 to
265 Vac) operation.
3. The number of turns required for a selected core size
and material is:
Load Overcurrent Limiting
If an overcurrent condition occurs and exceeds the boost
converter power limit established by the control circuit, Vo
will eventually be dragged down below the peak value of the
AC line voltage. If this happens, current will rise rapidly and
without limit through the series inductor and rectifier. This
may result in saturation of the inductor and components will
fail. The control circuit holds off the shunt switch, since the
current limit function is activated. It cannot help to turn the
switch ON – the inductor current will rise even more rapidly
and switch failure will occur.
Typically, a power factor correction circuit is connected to
another systems like switched mode power supply or
electronic ballast. These downstream converters typically
will have current limiting capability, eliminating concern
about load faults. However, a downstream converter or the
bulk capacitor might fail. Hence there is a possibility of a
short circuit at the load.
If it is considered necessary to limit the current to a safe
value in the event of a downstream fault, some means
external to the boost converter must be provided.
L I
10 6
3 2.894 10 6
P Lpk
N 1.162 10
P
0.3 60
B maxA e
186.8 turns 187 turns
Using EPCOS E 30/15/7, Bmax =0.3 T and Ae = 60 mm2.
4. The required air gap to achieve the correct inductance
and storage is:
l gap 7 2
N p Ae
L
P
4 10 7 187 2 60 10 6
410
1.162 10 3
2.269 mm
5. Design of Auxiliary Winding
N aux Design Example I – Traditional Boost Constant
Output Voltage Regulation Level Operation
Power Factor Correction
The basic design specification concerns the following:
• Mains Voltage Range: Vac(LL) – Vac(HL) = 85 – 265 Vac
Vaux N
P
Vo Vac(HL) 14 187
(400 265)
19.4 turns 20 turns
Round up to 20 turns to make sure enough voltage at the
auxiliary winding.
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AND8016/D
445
415
385
355
E. Calculation of MOSFET conduction losses
A 8A, 500V MOSFET, MTP8N50E is chosen. The on
resistance, Rds(on) 1.75 @100°C. Therefore, maximum
power MOSFET conduction losses is:
325
295
265
235
205
175
2
P
1R
I Lpk 1 (on)max
ds(on)
6
Vo/(V)
D. To determine the output capacitor
As rule of thumb, for 80 W output, start with 100 F,
450 V capacitor.
1.2 V
ac(LL)
Vo
145
115
85
1 1.75 2.894 2 1 1.2 85 1.82 W
6
400
F. Design of regulation and overvoltage
protection circuit
The output voltage regulation level can be adjusted by Ro,
85 100 115 1130 145 160 175 190 205 220 235 250 265 280
Vac (V)
Figure 4. Theoretical Vo versus Vac with CT = 10nF
Vo
Ro 400 2 MΩ
200 µA
200 µA
H. Design of the current sense circuit
Choose Rcs = 0.68 1. So the current sense resistor losses, PRcs:
Use two 1 M resistors in series.
2
2
P
1R
I Lpk 1 1 2.894 0.949 W
Rcs
CS
6
6
G. Designing the oscillator circuit
For traditional boost operation, CT is chosen with below
equation:
C T
Full Load
Half Load
Vacpeak
Therefore the power rating of RCS is chosen to be 2 W.
2. Overcurrent protection resistor, ROCP can be
determined with below equation:
2 K osc L P V 2
P
in
o C int
V 2ac(LL) R 2
o
R
OCP
2 6400 1.162mH 86.96 400 2 15pF 7.16nF
85 2 2MΩ 2
R
I
Lpk
CS
0.68 2.894 9600 Ω
I
205 µA
OCP
Use 10000 resistor. This provide current limit at 3.01 A
versus calculated value of ILpk = 2.894 A.
Use 10 nF capacitor.
80 W, Universal Input, Traditional Boost Constant Output Voltage Level Regulation Operation Power Factor
Correction Circuit Part List
Index
Value
Comment
Index
Value
Comment
C1
0.63 F@600 V
Filtering Capacitor
R6
22 @0.25 W
Aux Winding Resistor
C2
680 nF
Pin 2 Vcontrol Capacitor
R7
100 K@2 W
Start–up Resistor
C3
10 nF
Pin 3 Oscillator Capacitor
R8
1N5406
Input Diode
C4
100 F@50 V
Aux Capacitor, E–Cap
D1
1N5406
Input Diode
C5
100F@450V
Output Capacitor, E–Cap
D2
1N5406
Input Diode
C6
1 nF@50 V
Feedback Filtering Capacitor
D3
1N5406
Input Diode
R1
0.68 @2 W
Current Sense Resistor
D4
1N4937
Aux Winding Diode
R2
10 [email protected] W
OCP Sensing Resistor
D5
MUR460
Boost Diode
R3
1 [email protected] W
Feedback Resistor
D6
1N5245
Aux 15 V Zener Diode
R4
1 [email protected] W
Feedback Resistor
D7
MTP8N50E
Power MOSFET
R5
10 @0.25 W
Gate Resistor
Q1
1.162 mH
Inductor
* E 30/15/7, N67 Material from EPCOS
Primary – 187 turns of # 23 AWG, Secondary – 19 turns of # 23 AWG.
Gap length 2.269mm total for a primary inductance LP of 1.162mH.
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AND8016/D
D1
D3
D2
D4
D5
R6
R7
C1
L1
+
D7
C4
D5
1
8
2
7
+
C5
R5
Q1
MC33260
C2
R2
3
6
4
5
C3
R1
R3
R4
C6
Figure 5. 80 W Universal Input, Traditional Boost Constant Output Voltage Regulation Level Operation Power
Factor Correction Circuit
Design Table for Universal Input, Traditional Boost Constant Output Voltage Regulation Level Operation Power
Factor Correction
Po
25
50
75
100
125
150
200
(Watts)
LP
3.720
1.860
1.240
0.930
0.744
0.620
0.465
(mH)
Co
33
68
100
100
150
150
220
(F)
RCS
2
1
0.68
0.5
0.39
0.33
0.25
ROCP
10000
10000
10000
9100
9100
9100
9100
Cin
0.22
0.63
0.63
1.0
1.0
1.0
1.0
(F)
CT
10
10
10
10
10
10
10
(nF)
Q
MTP4N50E
Dout
MUR160
MTP8N50E
MUR460
Din
1N4007
1N5406
Design Example II – Follower Boost Variable
Output Voltage Regulation Level Operation
Power Factor Correction
The basic design specification concerns the following:
• Mains Voltage Range: Vac(LL) – Vac(HL) = 85 – 265 Vac
• Maximum Regulated DC Output Voltage: Vo = 400 Vdc
• Minimum Regulated DC Output Voltage: Vomin =
140 Vdc
• Rated Output Power: Po = 80 W
• Expected Efficiency, > 90%
MTW14N50E
B. Input diode current is maximum at Vinrms =
Vac(LL)
I
inpk
2 P
o 2 80 1.447 A
0.92 85
ηV
ac(LL)
C. Inductor design
1. Inductor peak current:
I
Lpk
2I
inpk
2 1.447 2.894 A
2. Inductor value, for follower boost operation, Vo =
Vomin:
A. The input power, Pin is given by
P
P o 80 86.96 W
in
0.92
η
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AND8016/D
2t
total
Lp V
omin V
2
ac(LL)
F. Design of regulation and overvoltage
protection circuit
The output voltage regulation level can be adjusted by Ro,
V
I
omin Lpk
2 40 10 6
140
2
85 85
140 2.894
Vo
Ro 400 2 MΩ
200 µA
200 µA
Use two 1M resistors in series.
0.235 µH
Let the switching cycle t = 40 s for universal input (85 to
265 Vac) operation.
3. The number of turns required for a selected core size
and material is:
G. Designing the Oscillator Circuit
For follower boost operation, CT is chosen with below
equation:
C T
10 6
L I
P Lpk
N P
B maxA e
2 6400 0.234mH 86.96 140 2 15pF 162 pF
85 2 2 MΩ 2
0.235 10 3 2.894 10 6 70.6 turns 71 turns
0.3 32.1
Use 150 pF capacitor.
Using EPCOS E 20/10/6, N67 material, Bmax =0.3 T and
Ae = 32.1 mm2.
4. The required air gap to achieve the correct inductance
and storage is:
445
415
385
355
7 2
N p Ae
L
P
4 10 7 71 2 32.1 10 6
410
Vo/(V)
l gap 0.235 10 3
0.856 mm
5. Design of Auxiliary Winding
N aux Vaux N
P
Vo Vac(HL) 2 K osc L P V 2
P
in
o C int
V 2ac(LL) R 2
o
325
295
265
235
205
175
145
115
85
14 71
(400 265)
Full Load
Half Load
Vacpeak
85 100 115 1130 145 160 175 190 205 220 235 250 265 280
Vac (V)
7.4 turns 8 turns
Figure 6. Theoretical Vo versus Vac with CT = 150pF
Round up to 8 turns to make sure enough voltage at the
auxiliary winding.
H. Design of the Current Sense Circuit
Choose Rcs = 0.68 1. So the current sense resistor losses, PRcs:
D. To determine the output capacitor
As rule of thumb, for 80 W output, start with 100 F,
450 V capacitor.
2
P
1R
I Lpk
Rcs
CS
6
1 0.68 2.894 2 0.949 W
6
E. Calculation of MOSFET conduction losses
A 4A, 500 V MOSFET, MTP4N50E is chosen. The on
resistance, Rds(on) 1.75 @100°C. Therefore, maximum
power MOSFET conduction losses is:
2. Overcurrent protection resistor, ROCP can be
determined with below equation:
1.2 V
ac(LL)
V
omin
1.2
85
1
2
1.75 2.894 1 0.66 W
6
140
R
OCP
2
P
1R
I Lpk 1 (on)max
ds(on)
6
R
I
Lpk
CS
0.68 2.894 9600 Ω
I
205 µA
OCP
Use 10000 resistor. This provide current limit at 3.01 A
versus calculated value of ILpk = 2.894 A.
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AND8016/D
80 W, Universal Input, Follower Boost Variable Output Voltage Regulation Level Operation Power Factor
Correction Circuit Part List
Index
Value
Comment
Index
Value
Comment
C1
0.63 F@600 V
Filtering Capacitor
R6
22 @0.25 W
Aux Winding Resistor
C2
680 nF
Pin 2 Vcontrol Capacitor
R7
100 K@2 W
Start–up Resistor
C3
150 pF
Pin 3 Oscillator Capacitor
D1
1N5406
Input Diode
C4
100 F@50 V
Aux Capacitor, E–Cap
D2
1N5406
Input Diode
C5
100 F@450 V
Output Capacitor, E–Cap
D3
1N5406
Input Diode
C6
1 nF@50 V
Feedback Filtering Capacitor
D4
1N5406
Input Diode
R1
0.68 @2 W
Current Sense Resistor
D5
1N4937
Aux Winding Diode
R2
10 [email protected] W
OCP Sensing Resistor
D6
MUR460
Boost Diode
R3
1 [email protected] W
Feedback Resistor
D7
1N5245
Aux 15 V Zener Diode
R4
1 [email protected] W
Feedback Resistor
Q1
MTP4N50E
Power MOSFET
R5
10 @0.25 W
Gate Resistor
L1*
0.235 mH
Inductor
* E 20/10/6, N67 Material from EPCOS
Primary – 71 turns of # 23 AWG, Secondary – 8 turns of # 23 AWG.
Gap length 0.865 mm total for a primary inductance LP of 0.235 mH.
D1
D3
D2
D4
R6
D5
R7
C1
L1
+
D7
C4
D5
1
8
2
7
+
C5
R5
Q1
MC33260
C2
R2
3
6
4
5
C3
R1
R3
R4
C6
Figure 7. 80 W Universal Input, Follower Boost Variable Output Voltage Regulation Level Operation Power Factor
Correction Circuit
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AND8016/D
Design Table for Universal Input, Follower Boost Variable Output Voltage Regulation Level Operation Power
Factor Correction
Po
25
50
75
100
125
150
200
(Watts)
LP
0.752
376
0.251
0.188
0.150
0.102
0.094
(mH)
Co
33
68
100
100
150
150
220
(F)
RCS
2
1
0.68
0.5
0.39
0.33
0.25
ROCP
10000
10000
10000
9100
9100
9100
9100
Cin
0.22
0.63
0.63
1.0
1.0
1.0
1.0
(F)
CT
0.162
0.162
0.162
0.162
0.162
0.162
0.162
(nF)
Q
MTD2N50E
Dout
MUR160
Din
1N4007
MTP4N50E
MTP8N50E
MUR460
1N5406
1N5406
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AND8016/D
Notes
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AND8016/D
Greenline is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: [email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
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AND8016/D
AND8123/D
Power Factor Correction
Stages Operating in Critical
Conduction Mode
Prepared by: Joel Turchi
ON Semiconductor
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APPLICATION NOTE
Basics of the Critical Conduction Mode
Critical conduction mode (or border line conduction
mode) operation is the most popular solution for low power
applications. Characterized by a variable frequency control
scheme in which the inductor current ramps to twice the
desired average value, ramps down to zero, then
immediately ramps positive again (refer to Figures 2 and 4),
this control method has the following advantages:
• Simple Control Scheme: The application requires few
external components.
• Ease of Stabilization: The boost keeps a first order
converter and there is no need for ramp compensation.
• Zero Current Turn On: One major benefit of critical
conduction mode is the MOSFET turn on when the
diode current reaches zero. Therefore the MOSFET
switch on is lossless and soft and there is no need for
a low trr diode.
On the other hand, the critical conduction mode has some
disadvantages:
• Large peak currents that result in high dl/dt and rms
currents conducted throughout the PFC stage.
• Large switching frequency variations as detailed in
the paper.
This paper proposes a detailed and mathematical analysis
of the operation of a critical conduction mode Power factor
Corrector (PFC), with the goal of easing the PFC stage
dimensioning. After some words on the PFC specification
and a brief presentation of the main critical conduction
schemes, this application note gives the equations necessary
for computing the magnitude of the currents and voltages
that are critical in the choice of the power components.
INTRODUCTION
The IEC1000−3−2 specification, usually named Power
Factor Correction (PFC) standard, has been issued with the
goal of minimizing the Total Harmonic Distortion (THD) of
the current that is drawn from the mains. In practice, the
legislation requests the current to be nearly sinusoidal and in
phase with the AC line voltage.
Active solutions are the most effective means to meet the
legislation. A PFC pre−regulator is inserted between the
input bridge and the bulk capacitor. This intermediate stage
is designed to output a constant voltage while drawing a
sinusoidal current from the line. In practice, the step−up (or
boost) configuration is adopted, as this type of converter is
easy to implement. One can just notice that this topology
requires the output to be higher than the input voltage. That
is why the output regulation level is generally set to around
400 V in universal mains conditions.
Diode Bridge
PFC Stage
Power Supply
+
AC
Line
+ Bulk
Capacitor
Controller
IN
LOAD
−
Figure 1. Power Factor Corrected Power Converter
PFC boost pre−converters typically require a coil, a diode and a Power Switch. This stage also needs a Power Factor Correction
controller that is a circuit specially designed to drive PFC pre−regulators. ON Semiconductor has developed three controllers
(MC33262, MC33368 and MC33260) that operate in critical mode and the NCP1650 for continuous mode applications.
One generally devotes critical conduction mode to power factor control circuits below 300 W.
 Semiconductor Components Industries, LLC, 2003
September, 2003 − Rev. 1
1
Publication Order Number:
AND8123/D
AND8123/D
Diode Bridge
Diode Bridge
+
L
Icoil
+
Icoil
L
Vin
+
Vin
IN
Vout
IN
−
−
The power switch is ON
The power switch is OFF
The coil current flows through the diode. The coil
voltage is (Vout −Vin ) and the coil current linearly decays
with a (Vout −Vin )/L slope.
The power switch being about zero, the input
voltage is applied across the coil. The coil current
linearly increases with a (Vin /L) slope.
Coil
Current
Vin/L
(Vout−Vin)/L
Critical Conduction Mode:
Next current cycle starts as
soon as the core is reset.
Icoil_pk
Figure 2. Switching Sequences of the PFC Stage
levels of the output voltage. The error amplifier
bandwidth is set low so that the error amplifier output
reacts very slowly and can be considered as a constant
within an AC line period.
• The controller multiplies the shaping information by
the error amplifier output voltage. The resulting product
is the desired envelope that as wished, is sinusoidal, in
phase with the AC line and whose amplitude depends
on the amount of power to be delivered.
• The controller monitors the power switch current.
When this current exceeds the envelope level, the PWM
latch is reset to turn off the power switch.
• Some circuitry detects the core reset to set the PWM
latch and initialize a new MOSFET conduction phase
as soon as the coil current has reached zero.
Consequently, when the power switch is ON, the current
ramps up from zero up to the envelope level. At that
moment, the power switch turns off and the current ramps
down to zero (refer to Figures 2 and 4). For simplicity of the
drawing, Figure 4 only shows 8 “current triangles”.
Actually, their frequency is very high compared to the AC
line one. The input filtering capacitor and the EMI filter
averages the “triangles” of the coil current, to give:
In critical discontinuous mode, a boost converter presents
two phases (refer to Figure 2):
• The on−time during which the power switch is on. The
inductor current grows up linearly according to a slope
(Vin/L) where Vin is the instantaneous input voltage and
L the inductor value.
• The off time during which the power switch is off. The
inductor current decreases linearly according to the
slope (Vout−Vin)/L where Vout is the output voltage.
This sequence terminates when the current equals zero.
Consequently, a triangular current flows through the coil.
The PFC stage adjusts the amplitude of these triangles so
that in average, the coil current is a (rectified) sinusoid (refer
to Figure 4). The EMI filter (helped by the 100 nF to 1.0 F
input capacitor generally placed across the diodes bridge
output), performs the filtering function.
The more popular scheme to control the triangles
magnitude and shape the current, forces the inductor peak
current to follow a sinusoidal envelope. Figure 3
diagrammatically portrays its operation mode that could be
summarized as follows:
• The diode bridge output being slightly filtered, the
input voltage (Vin) is a rectified sinusoid. One pin of
the PFC controller receives a portion of Vin. The
voltage of this terminal is the shaping information
necessary to build the current envelope.
• An error amplifier evaluates the power need in response
to the error it senses between the actual and wished
Icoil T Icoil_pk
2
(eq. 1)
where <Icoil>T is the average of one current triangle
(period T) and Icoil_pk is the peak current of this triangle.
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2
AND8123/D
As Icoil_pk is forced to follow a sinusoidal
envelop (k*Vin), where k is a constant modulated
by the error amplifier, <Icoil> T is also sinusoidal
Icoil T k * Vin 2
k * 2 * Vac * sin(t)
.
2
As
a
result, this scheme makes the AC line current sinusoidal.
PFC Stage
Vin
L1
D1
Bulk
Capacitor
Input
Filtering
Capacitor
AC Line
+
C1
X1
R7
Current Sensing
Resistor
PWM Latch
Zero Current
Detection
S
Output Buffer
+
−
Current
Envelope
Q
R
Current Sense
Comparator
R1
R2
C2
Multiplier
Error
Amplifier
−
+
R3
Vref
R4
Figure 3. Switching Sequences of the PFC Stage
The controller monitors the input and output voltages and using this information and a multiplier, builds a sinusoidal envelope. When the
sensed current exceeds the envelope level, the Current Sense Comparator resets the PWM latch and the power switch turns off. Once
the core has reset, a dedicated block sets the PWM latch and a new MOSFET conduction time starts.
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3
AND8123/D
Peak
Icoil_pk
Average (<Icoil>T)
Inductor Current
(Icoil)
Tac/2
T
(Tac is the
AC line period)
MOSFET
DRIVE
Figure 4. Coil Current
During the power switch conduction time, the current ramps up from zero up to the envelope level. At that
moment, the power switch turns off and the current ramps down to zero. For simplicity of the drawing,
only 8 “current triangles” are shown. Actually, their frequency is very high compared to the AC line one.
One can note that a simple calculation would show that the on−time is constant over the sinusoid: ton 2 * L * Pin and
Vac2
that the switching frequency modulation is brought by the off−time that equals:
toff 2 * 2 * L *
2 * Vac * sin(t)
Pin * sin(t) ton *
Vac * (Vout 2 * Vac * sin(t))
Vout 2 * Vac * sin(t)
(eq. 2)
That is why the MC33260 developed by ON Semiconductor
does not incorporate a multiplier inputting a portion of the
rectified AC line to shape the coil current. Instead, this part
forces a constant on−time to achieve in a simplest manner, the
power factor correction.
Main Equations
• The power switch off time (toff). During this second
phase, the coil current flows through the output diode
and feeds the output capacitor and the load. The diode
voltage being considered as null when on, the voltage
across the coil becomes negative and equal to
(Vin−Vout). The coil current decreases then linearly with
the slope ((Vout−Vin)/L) from (Icoil_pk) to zero, as
follows:
Switching Frequency
As already stated, the coil current consists of two phases:
• The power switch conduction time (ton). During this
time, the input voltage applies across the coil and the
current increases linearly through the coil with a
(Vin/L) slope:
Icoil(t) Vin * t
L
(eq. 3)
This phase ends when the conduction time (ton) is
complete that is when the coil current has reached its peak
value (Icoil_pk). Thus:
Icoil_pk Vin * ton
L
L * Icoil_pk
Vin
(eq. 6)
This phase ends when Icoil reaches zero, then the off−time
is given by the following equation:
toff (eq. 4)
The conduction time is then given by:
ton Icoil(t) Icoil_pk Vout Vin * t
L
L * Icoil_pk
Vout Vin
(eq. 7)
The total current cycle (and then the switching period, T)
is the sum of ton and toff. Thus:
(eq. 5)
T ton toff L * Icoil_pk *
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4
Vout
(eq. 8)
Vin * (Vout Vin)
AND8123/D
20
As shown in the next paragraph (equation 15), the coil
peak current can be expressed as a function of the input
power and the AC line rms voltage as follows:
Icoil_pk 2 * 2 * Pin * sin(t) , where is the AC
Vac
T 2 * 2 * L * Pin * sin(t)
Vac
Vout
*
2 * Vac * sin(t) * (Vout Vin)
f / f(200W)
line angular frequency. Replacing Icoil_pk by this
expression in equation (8) leads to:
(eq. 9)
This equation simplifies:
0
T 2 * L * Pin * Vout
Vac2 * (Vout Vin)
(eq. 10)
2 * Vac * sin(t)
Vac2
1
Vout
2 * L * Pin 2
working point (load and AC line rms voltage).
1
2 * Vac * sin(t)
Vout
100
150
200
This plot sketches the switching frequency variations versus the
input power in a normalized form where f(200 W) = 1. The
switching frequency is multiplied by 20 when the power is 10 W.
In practice, the PFC stage propagation delays clamp the
switching frequency that could theoretically exceed several
megaHertz in very light load conditions. The MC33260 minimum
off−time limits the no load frequency to around 400 kHz.
(eq. 11)
that only varies versus the
• One term 2 * L Vac
* Pin 50
Figure 6. Switching Frequency vs. the Input Power
(at the Sinusoid top)
This equation shows that the switching frequency
consists of:
• A modulation factor
0
Pin (W)
The switching frequency is the inverse of the switching
period. Consequently:
f
10
1.5
that
makes the switching frequency vary within the AC line
sinusoid.
The following figure illustrates the switching frequency
variations versus the AC line amplitude, the power and
within the sinusoid.
1.0
sin (t)
0.5
2.50
f
2.00
0
0
1.0
2.0
3.0
f / f(90)
t
Figure 7. Switching Frequency Over the AC Line
Sinusoid @ 230 Vac
1.50
This plot gives the switching variations over the AC line sinusoid
at Vac = 230 V and Vout = 400 V, in a normalized form where f
is taken equal to 1 at the AC line zero crossing. The switching
frequency is approximately divided by 5 at the top of the
sinusoid.
1.00
0.50
80
110
140
170
200
Vac, (V)
230
260
290
Figure 5. Switching Frequency Over the AC Line
RMS Voltage (at the Sinusoid top)
The figure represents the switching frequency variations versus
the line rms voltage, in a normalized form where f(90) = 1. The
plot drawn for Vout = 400 V, shows large variations (200% at Vac =
180 V, 60% at Vac = 270 V). The shape of the curve tends to
flatten if Vout is higher. However, the minimum of the switching
frequency is always obtained at one of the AC line extremes
(VacLL or VacHL where VacLL and VacHL are respectively, the
lowest and highest Vac levels).
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5
AND8123/D
1.5
Provided that the AC line current results from the
averaging of the coil current, one can deduct the following
equation:
1.0
lin(t) Icoil T sin (t)
Icoil_pk 2 * 2 * lac * sin(t)
0
0
1.0
(eq. 13)
where <Icoil>T is the average of the considered coil current
triangle over the switching period T and Icoil_pk is the
corresponding peak.
Thus, the peak value of the coil current triangles follows
a sinusoidal envelope and equals:
f
0.5
Icoil_pk
2
2.0
Since the PFC stage forces the power factor close to 1, one
can use the well known relationship linking the average
input power to the AC line rms current and rms voltage
( Pin Vac * lac) and the precedent equation leads to:
3.0
t
Figure 8. Switching Frequency Over the AC Line
Sinusoid @ 90 Vac
Icoil_pk 2 * 2 * Pin * sin(t)
Vac
This plot shows the same characteristic but for Vac = 90 V.
Similarly to what was observed in Figure 5 (f versus Vac), the
higher the difference between the output and input voltages,
the flatter the switching frequency shape.
(eq. 15)
The coil current peak is maximum at the top of the
sinusoid where sin(
t) 1. This maximum value,
(Icoil_pk)H, is then:
Finally, the switching frequency dramatically varies
within the AC line and versus the power. This is probably the
major inconvenience of the critical conduction mode
operation. This behavior often makes tougher the EMI
filtering. It also can increase the risk of generating
interference that disturb the systems powered by the PFC
stage (for instance, it may produce some visible noise on the
screen of a monitor).
In addition, the variations of the frequency and the high
values it can reach (up to 500 kHz) practically prevent the
use of effective tools to damp EMI and reduce noise like
snubbing networks that would generate too high losses.
One can also note that the frequency increases when the
power diminishes and when the input voltage increases. In
light load conditions, the switching period can become as
low as 2.0 s (500 kHz). All the propagation delays within
the control circuitry or the power switch reaction times are
no more negligible, what generally distorts the current
shape. The power factor is then degraded.
The switching frequency variation is a major limitation of
the system that should be reserved to application where the
load does not vary drastically.
(Icoil_pk)H 2 * 2 * Pin Vac
(eq. 16)
From this equation, one can easily deduct that the peak
coil current is maximum when the required power is
maximum and the AC line at its minimum voltage:
Icoil_max 2 * 2 * Pin max
VacLL
(eq. 17)
where <Pin>max is the maximum input power of the
application and VacLL the lowest level of the AC line
voltage.
Coil RMS Current
The rms value of a current is the magnitude that squared,
gives the dissipation produced by this current within a 1.0 resistor. One must then compute the rms coil current by:
• First calculating the “rms current” within a switching
period in such a way that once squared, it would give
the power dissipated in a 1.0 resistor during the
considered switching period.
• Then the switching period being small compared to the
input voltage cycle, regarding the obtained expression
as the instantaneous square of the coil current and
averaging it over the rectified sinusoid cycle, to have
the squared coil rms current.
This method will be used in this section.
As above explained, the current flowing through the
coil is:
• (IM(t) Vin * tL Icoil_pk * tton) during the
MOSFET on−time, when 0<t<ton.
Coil Peak and RMS Currents
Coil Peak Current
As the PFC stage makes the AC line current sinusoidal and
in phase with the AC line voltage, one can write:
lin(t) 2 * lac * sin(t)
(eq. 14)
(eq. 12)
where Iin(t) is the instantaneous AC line current and Iac its
rms value.
•
(ID(t) Icoil_pk−(Vout−Vin) * tL Icoil_pk * (T t)
(T ton) ) during the diode conduction time, that is,
when ton<t<T.
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6
AND8123/D
Therefore, the rms value of any coil current triangle over the corresponding switching period T, is given by the following
equation:
(Icoil)rms T 1*
T
2
T
2
Icoil_pk * t
* dt Icoil_pk * T t * dt
ton
T ton
ton
0
ton
(eq. 18)
Solving the integrals, it becomes:
(Icoil)rms T (eq. 19)
1*
T
The precedent simplifies as follows:
(Icoil)rms T 1 * Icoil_pk2 * ton (T ton) * ( Icoil_pk3)
3
T
3 * Icoil_pk
Rearrangement of the terms leads to:
(Icoil)rms T Icoil_pk *
1 * ton T ton
3
3
T
(Icoil)rms T Icoil_pk
3
(eq. 22)
Replacing the coil peak current by its expression as a
function of the average input power and the AC line rms
voltage (equation 15), one can write the following equation:
Pin * sin(t)
23 * Vac
(eq. 20)
gives the resistive losses at this given Vin. Now to have the
rms current over the rectified AC line period, one must not
integrate <(Icoil)rms>T but the square of it, as we would
have proceeded to deduct the average resistive losses from
the dissipation over one switching period. However, one
must not forget to extract the root square of the result to
obtain the rms value.
As the consequence, the coil rms current is:
(eq. 21)
Calculating the term under the root square sign, the
following expression is obtained:
(Icoil)rms T 2 *
3
Icoil_pk * TTtonT 3 Icoil_pk * TT ton
ton
Icoil_pk2 ton3
(T ton)
*
*
3
3 * Icoil_pk
ton2
(Icoil)rms (eq. 24)
2 *
Tac
Tac2
0
(Icoil)rms T 2 * dt
where Tac = 2*/ is the AC line period (20 ms in Europe,
16.66 ms in USA). The PFC stage being fed by the rectified
AC line voltage, it operates at twice the AC line frequency.
That is why, one integrates over half the AC line period
(Tac/2).
(eq. 23)
This equation gives the equivalent rms current of the coil
over one switching period, that is, at a given Vin. As already
stated, multiplying the square of it by the coil resistance,
Substitution of equation (23) into the precedent equation leads to:
(Icoil)rms 2 *
Tac
Tac2
0
2*
Pin * sin(t),
23 * Vac
2
* dt
Icoil(rms) 2 * Pin 3
Vac
that is, the rms
value of a sinusoidal current whose magnitude is
(2 *
(eq. 25)
Therefore:
This equation shows that the coil rms current is the rms
value of: 2 *
2 * Pin * sin(t)
3
Vac
Pin ). The rms value of such a sinusoidal
23 * Vac
current is well known (the amplitude divided by 2).
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7
(eq. 26)
AND8123/D
• The output voltage is considered as a constant. The
Switching Losses
The switching losses are difficult to determine with
accuracy. They depend of the MOSFET type and in
particular of the gate charge, of the controller driver
capability and obviously of the switching frequency that
varies dramatically in a critical conduction mode operation.
However, one can make a rough estimation if one assumes
the following:
•
output voltage ripple being generally less than 5% the
nominal voltage, this assumption seems reasonable.
The switching times (t and tFR, as defined in
Figure 9), are considered as constant over the sinusoid.
Dissipated Power:
(IMOSFET * Vdrain)
tFR
IMOSFET
Vdrain
t
Figure 9. Turn Off Waveforms
(eq. 27)
Figure 9 represents a turn off sequence. One can observe
three phases:
• During approximately the second half of the gate
voltage Miller plateau, the drain−source voltage
increases linearly till it reaches the output voltage.
• During a short time that is part of the diode forward
recovery time, the MOSFET faces both maximum
voltage and current.
• The gate voltage drops (from the Miller plateau) below
the gate threshold and the drain current ramps down
to zero.
psw Vout * 2Icoil_pk * t−tTFR Vout * Icoil_pk * tFRT
where: t and tFR are the switching times portrayed by
Figure 9 and T is the switching period.
Equation (8) gives an expression linking the coil peak
current and the switching period of the considered current
cycle (triangle): T L * Icoil_pk
Vout
*
.
Vin
Vout Vin
Substitution of equation (8) into the equation (27) leads
to:
“t” of Figure 9 represents the total time of the three phases,
“tFR’’ the second phase duration.
Therefore, one can write:
psw http://onsemi.com
8
Vin * (Vout Vin) * (t tFR)
2*L
(eq. 28)
AND8123/D
(eq. 29)
This equation shows that the switching losses over a
switching period depend of the instantaneous input voltage,
the difference between the instantaneous output and input
voltages, the switching time and the coil value. Let’s
calculate the average losses (<psw>) by integrating psw
over half the AC line period:
Rearranging the terms, one obtains:
psw t tFR
*
2*L
2 *
Tac
psw 2 *
Tac
Tac2
Vin * Vout * dt
0
Vout being considered as a constant, one can easily
solve this equation if one remembers that the input
voltage average value is (2 * 2 * Vac) and that
(Vac2 2 *
Tac
Tac2
Vin2 * dt). Applying this, it becomes:
•
0
(eq. 31)
2 *
Tac
Tac2
Vin2 * dt
0
(eq. 30)
Q3 being not always specified, instead, one can take
the sum of Q1 with half the Miller plateau gate charge
(Q2/2). Knowing the drive capability of the circuit,
one can deduct the turn off time (t = Q3/Idrive or t =
[Q1 + (Q2/2)]/Idrive).
In a first approach, tFR can be taken equal to the diode
forward recovery time.
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
Vin * (Vout Vin) * (t tFR)
* dt
2*L
12
Or in a simpler manner:
2 * (t tFR) * Vac2
Vout psw *
2 * Vac 4
*L
(eq. 32)
The coil inductance (L) plays an important role: the losses
are inversely proportional to this value. It is simply because
the switching frequency is also inversely proportional to L.
This equation also shows that the switching losses are
independent of the power level. One could have easily
predict this result by simply noting that the switching
frequency increased when power diminished.
Equation (32) also shows that the lower the ratio
(Vout/Vac), the smaller the MOSFET switching losses. That
is because the “Follower Boost” mode that reduces the
difference between the output and input voltages, lowers the
switching frequency. In other words, this technique enables
the use of a smaller coil for the same switching frequency
range and the same switching losses.
For instance, the MC33260 features the “Follower Boost”
operation where the pre−converter output voltage stabilizes
at a level that varies linearly versus the AC line amplitude.
This technique aims at reducing the gap between the output
and input voltages to optimize the boost efficiency and
minimize the cost of the PFC stage 1.
How to extract t and tFR?
• The best is to measure them.
• One can approximate t as the time necessary to extract
the gate charge Q3 of the MOSFET (refer to Figure 10).
QT
VDS
9
VGS
6
Q2
Q1
3
ID = 2.3 A
TJ = 25°C
Q3
0
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t tFR
2 * 2 * Vac * Vout
psw *
Vac2
2*L
Tac2
QT, TOTAL GATE CHARGE (nC)
Figure 10. Typical Total Gate Charge Specification
of a MOSFET
One must note that the calculation does not take into
account:
• The energy consumed by the controller to drive the
MOSFET (Qcc*Vcc*f), where Qcc is the MOSFET
gate charge necessary to charge the gate voltage to Vcc,
Vcc the driver supply voltage and f the switching
frequency.
• The energy dissipated because of the parasitic
capacitors of the PFC stage. Each turn on produces an
abrupt voltage change across the parasitic capacitors of
the MOSFET drain−source, the diode and the coil. This
results in some extra dissipation across the MOSFET
(1/2*Cparasitic*V2*f), where Cparasitic is the
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9
AND8123/D
considered parasitic capacitor and V the voltage
change across it.
1
Power MOSFET Conduction Losses
As portrayed by Figure 4, the coil current is formed by
high frequency triangles. The input capacitor together with
the input RFI filter integrates the coil current ripple so that
the resulting AC line current is sinusoidal.
During the on−time, the current rises linearly through the
power switch as follows:
Refer to MC33260 data sheet for more details at
http://www.onsemi.com/.
However, equation (32) should give a sufficient first
approach approximation in most applications where the two
listed sources of losses play a minor role. Nevertheless, the
losses produced by the parasitic capacitors may become
significant in light load conditions where the switching
frequency gets high. As always, bench validation is key.
Icoil(t) Vin * t
L
(eq. 33)
where Vin is the input voltage (Vin 2 * Vac * sin(t) ), L
is the coil inductance and t is the time.
During the rest of the switching period, the power switch is off. The conduction losses resulting from the power dissipated
by Icoil during the on−time, one can calculate the power during the switching period T as follows:
ton
pT 1 *
T
ton
Ron * Icoil(t)2 * dt 1 *
T
0
where Ron is the MOSFET on−time drain source resistor,
ton is the on−time.
Solving the integral, equation (34) simplifies as follows:
(eq. 34)
One can calculate the duty cycle (d = ton/T) by:
•
2 ton
2
3
pT Ron * Vin * t2 * dt 1 * Ron * Vin * ton
3
T
L
L
T
0
As the coil current reaches its peak value at the end of the
on−time, Icoil_pk Vin * tonL and the precedent equation
can be rewritten as follows:
pT 1 * Ron * Icoil_pk2 * ton
3
T
• Either noting that the off−time (toff) can be expressed as
(eq. 35)
0
2
Ron * Vin * t * dt
L
a function of ton (refer to equation 2) and substituting
this equation into (T = ton + Toff),
Or considering that the critical conduction mode being
at the border of the continuous conduction mode
(CCM), the expression giving the duty−cycle in a CCM
boost converter applies.
Both methods lead to the same following result:
d ton 1 Vin
T
Vout
(eq. 36)
(eq. 37)
Substitution of equation (37) into equation (36) leads to:
One can recognize the traditional equation permitting to
calculate the MOSFET conduction losses in a boost or a
pT 1 * Ron * Icoil_pk2 * 1 Vin
3
Vout
flyback ( 1 * Ron * Ipk2 * d, where Ipk is the peak current and
3
(eq. 38)
One can note that the coil peak current (Icoil_pk) that
follows a sinusoidal envelop, can be written as follows:
d, the MOSFET duty cycle).
Icoil_pk 2 * 2 * Pin * sin(t) (refer to equation 15).
Vac
Replacing Vin and Icoil_pk by their sinusoidal expression, respectively (2 * Vac * sin(t) ) and (2 * 2 * Pin * sin(t) ),
Vac
equation (38) becomes:
2 * Vac * sin(t)
2
pT 1 * Ron * 2 * 2 * Pin * sin(t) * 1 3
Vout
Vac
That is in a more compact form:
2 * Vac
2
pT 8 * Ron * Pin * sin 2(t) * sin 3(t)
3
Vout
Vac
(eq. 39)
(eq. 40)
Equation (40) gives the conduction losses at a given Vin voltage. This equation must be integrated over the rectified AC line
sinusoid to obtain the average losses:
2
p Tac 8 * Ron * Pin * 2 *
3
Vac
Tac
Tac2
0
sin 2(t) http://onsemi.com
10
2 * Vac
* sin 3(t)
Vout
* dt
(eq. 41)
AND8123/D
If the average value of sin2(t) is well known (0.5), the
calculation of <sin3(t)> requires few trigonometry
remembers:
•
sin 2() •
sin() * cos() sin( ) sin( )
2
Combining the two precedent formulas, one can obtain:
1 cos(2)
2
sin 3(t) 3 * sin(t) sin(3t)
4
4
(eq. 42)
Substitution of equation 42) into equation (41) leads:
2
p Tac 8 * Ron * Pin * 2 *
3
Tac
Vac
Tac2
0
sin(t)2 Solving the integral, it becomes:
2 * Vac
3 * 2 * Vac
* sin(t) * sin(3t)
4 * Vout
4 * Vout
2 * Vac 2
2
3 * 2 * Vac 2
p Tac 8 * Ron * Pin * 1 * *
2
3
Vac
4 * Vout
4 * Vout 3
Equation (44) simplifies as follows:
2
8 * 2 * Vac
p Tac 4 * Ron * Pin * 1 3
3 * Vout
Vac
This formula shows that the higher the ratio (Vac/Vout),
the smaller the MOSFET conduction losses. That is why the
“Follower Boost” mode that reduces the difference between
the output and input voltages, enables to reduce the
MOSFET size.
For instance, the MC33260 features the “Follower Boost”
operation where the pre−converter output voltage stabilizes
at a level that varies linearly versus the AC line amplitude.
This technique aims at reducing the gap between the output
and input voltages to optimize the boost efficiency and
minimize the cost of the PFC stage2.
By the way, one can deduct from this equation the rms
current ((IM)rms) flowing through the power switch
knowing that p Tac Ron * (IM)2rms :
(IM)rms 2 * Pin *
3
Vac
1
8 * 2 * Vac
3 * Vout
* dt
(eq. 44)
(eq. 45)
The MC33260 monitors the whole coil current by
monitoring the voltage across a resistor inserted between
ground and the diodes bridge (negative sensing – refer to
Figure 15). The circuit utilizes the current information for
both the overcurrent protection and the core reset detection
(also named zero current detection). This technique brings
two major benefits:
• No need for an auxiliary winding to detect the core
reset. A simple coil is sufficient in the PFC stage.
• The MC33260 detects the in−rush currents that may
flow at start−up or during some overload conditions and
prevents the power switch from turning on in that
stressful condition. The PFC stage is significantly safer.
Some increase of the power dissipated by the current
sense resistor is the counter part since the whole current is
sensed while circuits like the MC33262 only monitor the
power switch current.
(eq. 46)
Dissipation of the Current Sense Resistor in MC33262
Like Circuits
Dissipation within the Current Sense Resistor
PFC controllers monitor the power switch current either
to perform the shaping function or simply to prevent it from
being excessive. That is why a resistor is traditionally placed
between the MOSFET source and ground to sense the power
switch current.
2
(eq. 43)
Since the same current flows through the current sense
resistor and the power switch, the calculation is rather easy.
One must just square the rms value of the power switch
current (IM)rms calculated in the previous section and
multiply the result by the current sense resistance.
Refer to MC33260 data sheet for more details at
http://www.onsemi.com/.
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11
AND8123/D
Doing this, one obtains:
2
8 * 2 * Vac
pRs 262 4 * Rs * Pin * 1 3
3 * Vout
Vac
(eq. 47)
where <pRs>262 is the power dissipated by the current sense resistor Rs.
Dissipation of the Current Sense Resistor in MC33260
Like Circuits
current at the switching period level and then to integrate the
obtained result over the AC line sinusoid.
As portrayed by Figure 4, the coil discharges during the
off time. More specifically, the current decays linearly
through the diode from its peak value (Icoil_pk) down to
zero that is reached at the end of the off−time. Taking the
beginning of the off−time as the time origin, one can then
write:
In this case, the current sense resistor Rs derives the whole
coil current. Consequently, the product of Rs by the square
of the rms coil current gives the dissipation of the current
sense resistor:
pRs 260 Rs * (Icoil(rms) )2
(eq. 48)
where Icoil(rms) is the coil rms current that as expressed by
Icoil(t) Icoil_pk * toff−t
toff
equation (26), equals: Icoil(rms) 2 * Pin .
3
Vac
Similarly to the calculation done to compute the coil rms
current, one can calculate the “diode rms current over one
switching period”:
Consequently:
2
(eq. 49)
pRs 260 4 * Rs * Pin 3
Vac
(eq. 50)
Id(rms)T Id(rms)T 2 *
pRs 262 pRs 260 1 0.85 * Vm (eq. 51)
Vout
(eq. 57)
Pin * toff * sin(t)
23 * Vac
T
(eq. 58)
In addition, one can easily show that toff and T are linked
by the following equation:
where Vm is the AC line amplitude.
2 * Vac * sin(t)
toff T * Vin T *
Vout
Vout
Average and RMS Current through the Diode
The diode average current can be easily computed if one
notes that it is the sum of the load and output capacitor
currents:
(eq. 59)
Consequently, equation (58) can be changed into:
(eq. 52)
Id(rms)T Then, in average:
3
2 * 2 * 2 Pin *
* sin(t) (eq. 60)
3
Vac * Vout
This equation gives the equivalent rms current of the
diode over one switching period, that is, at a given Vin. As
already stated in the Coil Peak and RMS Currents section,
the square of this expression must be integrated over a
rectified sinusoid period to obtain the square of the diode
rms current.
Therefore:
(eq. 53)
Id Iload ICout Iload ICout At the equilibrium, the average current of the output
capacitor must be 0 (otherwise the capacitor voltage will be
infinite). Thus:
Id Iload Pout
Vout
3toff* T * Icoil_pk
Substitution of equation (15) that expresses Icoil_pk, into
the precedent equation leads to:
If one considers that (8/3 ) approximately equals 0.85,
the precedent equation simplifies:
Id Iload ICout
(eq. 56)
Solving the integral, one obtains the expression of the
“rms diode current over one switching period”:
One obtains:
toff
2
Id(rms)2T 1 * Icoil_pk * toff−t * dt
T 0
toff
Comparison of the Losses Amount in the Two Cases
Let’s calculate the ratios: pRs 262 pRs 260 .
8 * 2 * Vac
pRs 262 pRs 260 1 3 * Vout
(eq. 55)
(eq. 54)
The rms diode current is more difficult to calculate.
Similarly to the computation of the rms coil current for
instance, it is necessary to first compute the squared rms
Tac2
Id(rms)2 2 *
Tac
http://onsemi.com
12
0
(eq. 61)
8 * 2 Pin 2
*
* sin 3(t) * dt
3
Vac * Vout
AND8123/D
Similarly to the Power MOSFET Conduction Losses section, the integration of (sin3 (t)) requires some preliminary
trigonometric manipulations:
sin 3(t) sin(t) * sin 2(t) sin(t) *
1 cos(2t)
12 * sin(t) 12 * sin(t) * cos(2t)
2
And :
sin(t) * cos(2t) 1 * (sin(−t) sin(4t) )
2
Then :
sin 3(t) 3 * sin(t) 1 * sin(3t)
4
4
Consequently, equation (61) can change into:
Tac2
Id(rms)2 2 *
Tac
One can now solve the integral and write:
0
3 * sin(t) sin(3t)
8 * 2
Pin2
*
*
* dt
4
3
4
Vac * Vout
(eq. 62)
16 * 2 Pin 2 3 * (cos(0) cos(Tac2) ) cos(3Tac2) cos(30)
Id(rms)2 *
*
12
4
3 * Tac Vac * Vout
As (
* Tac 2), we have:
cos()−1
3 * (1− cos() )
16 * 2
Pin2
Id(rms)2 *
*
3
Vac * Vout
12 * Tac
4 * Tac
One can simplify the equation replacing the cosine
elements by their value:
(eq. 63)
(eq. 64)
Thus:
(eq. 71)
16 * 2 Pin 2
(eq. 65)
Id(rms)2 *
* 6 1
3
Vac * Vout 8 * 12 * Ic(rms)2 I1(rms)2 I2(rms)2 4 *
Tac
Tac2
I1 * I2 * dt
0
The square of the diode rms current simplifies as follows:
32 * 2 Pin 2
Id(rms)2 *
9 * Vac * Vout
PFC Stage
(eq. 66)
L
Finally, the diode rms current is given by:
Id(rms) 4 *
3
2 * 2
* Pin Vac * Vout
Vin
I1
Load
DRV
As shown by Figure 11, the capacitor current results from
the difference between the diode current (I1) and the current
absorbed by the load (I2):
One knows the first term (I1(rms)2). This is the diode rms
current calculated in the previous section. The second and
third terms are dependent of the load. One cannot compute
them without knowing the characteristic of this load.
Anyway, the second term (I2(rms)2) is generally easy to
calculate once the load is known. Typically, this is the rms
current absorbed by a downstream converter. On the other
hand, the third term is more difficult to determine as it
depends on the relative occurrence of the I1 and I2 currents.
As the PFC stage and the load (generally a switching mode
power supply) are not synchronized, this term even seems
impossible to predict. One can simply note that this term
tends to decrease the capacitor rms current and
consequently, one can deduct that:
(eq. 68)
Tac2
(I1 I2)2 * dt
(eq. 69)
0
Rearranging (I1−I2)2 leads to:
Ic(rms)2 2 *
Tac
Tac2
Power
Switch
Figure 11. Output Capacitor Current
Thus, the capacitor rms current over the rectified AC line
period, is the rms value of the difference between I1 and I2
during this period. As a consequence:
Ic(rms)2 2 *
Tac
I2
Ic
(eq. 67)
Output Capacitor RMS Current
Ic(t) I1(t) I2(t)
Vout
D
(eq. 70)
[I12 I22 (2 * I1 * I2)] * dt
0
Ic(rms) I1(rms)2 I2(rms)2
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(eq. 72)
AND8123/D
Substitution of equation (67) that gives the diode rms
current into the precedent equation leads to:
Ic(rms) Pin 2
329 ** 2* *
I2(rms)2
Vac * Vout
where I2(rms) is the load rms current.
(eq. 73)
If the load is resistive, I2 = Vout/R where R is the load resistance and equation (71) changes into:
2
Ic(rms)2 1(rms)2 Vout 4 *
Tac
R
Tac2
0
1 * Vout * dt
R
(eq. 74)
Thus, the capacitor squared rms current is:
2 2 * Vout
Ic(rms)2 Id(rms)2 Vout
* Id R
R
(eq. 75)
2
32 * 2 Pin 2
*
Vout 2 * Vout * Pout
Ic(rms)2 Vout
R
R
9 * Vac * Vout
(eq. 76)
As Pout = Vout2/R, the precedent equation simplifies as follows:
Ic(rms) 2
32 * 2 Pin 2
*
Vout
9 * Vac * Vout
R
You may find a more friendly expression in the literature:
(eq. 77)
This explanation assumes that the energy that is fed by the
PFC stage perfectly matches the energy drawn by the load
over each switching period so that one can consider that the
capacitive part of the bulk has a constant voltage and that
only the ESR creates some ripple.
In fact, there is an additional low frequency ripple which
is inherent to the Power Factor Correction. The input current
and voltage being sinusoidal, the power fed by the PFC stage
has a squared sinusoid shape. On the other hand, the load
generally draws a constant power. As a consequence, the
PFC pre−converter delivers an amount of power that
matches the load demand in average only. The output
capacitor compensates the lack (excess) of input power by
supplying (storing) the part of energy necessary for the
instantaneous matching. Figures 13 and 14 sketch this
behavior.
Ic(rms) I2 , where I2 is the load current. This equation is
2
an approximate formula that does not take into account the
switching frequency ripple of the diode current. Only the
low frequency current that generates the low frequency
ripple of the bulk capacitor (refer to the next section) is
considered (this expression can easily be found by using
equation (88) and computing Ibulk Cbulk * dVoutdt ).
Equation (77) takes into account both high and low
frequency ripples.
Output Voltage Ripple
The output voltage (or bulk capacitor voltage) exhibits
two ripples.
The first one is traditional to Switch Mode Power
Supplies. This ripple results from the way the output is fed
by current pulses at the switching frequency pace. As bulk
capacitors exhibit a parasitic series resistor (ESR – refer to
Figure 12), they cannot fully filter this pulsed energy source.
More specifically:
• During the on−time, the PFC MOSFET conducts and
no energy is provided to the output. The bulk capacitor
feeds the load with the current it needs. The current
together with the ESR resistor of the bulk capacitor
form a negative voltage –(ESR*I2), where I2 is the
instantaneous load current,
• During the off−time, the diode derives the coil current
towards the output and the current across the ESR
becomes ESR*(Id−I2), where Id is the instantaneous
diode current.
PFC Stage
Id
Vin
I2
Load
Ic
Driver
ESR
Bulk
Capacitor
Figure 12. ESR of the Output Capacitor
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AND8123/D
400 V
Vout (5 V/div)
*Pin (40 W/div)
Load Power (100 W)
Vin (100 V/div)
0V
Figure 13. Output Voltage Ripple
The dashed black line represents the power that is absorbed by the load. The PFC stage delivers a power that has a squared
sinusoid shape. As long as this power is lower than the load demand, the bulk capacitor compensates by supplying part of the
energy it stores. Consequently the output voltage decreases. When the power fed by the PFC pre−converter exceeds the load
consumption, the bulk capacitor recharges. The peak of the PFC power is twice the load demand.
Vout (5 V/div)
400 V
Ic (200 mA/div)
0A
Vin (100 V/div)
0V
Figure 14. Output Voltage Ripple
The output voltage equals its average value when the input voltage is minimum and maximum. The output voltage is lower than
its average value during the rising phase of the input voltage and higher during the input voltage decay. Similarly to the input
power and voltage, the frequency of the capacitor current (represented in the case of a resistive load) is twice the AC line one.
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AND8123/D
In this calculation, one does not consider the switching
ripple that is generally small compared to the low frequency
ripple. In addition, the switching ripple depends on the load
current shape that cannot be predicted in a general manner.
As already discussed, the average coil current over a
switching period is:
lin 2 * Pin * sin(t)
Vac
The instantaneous input power (averaged over the
switching period) is the product of the input voltage
(2 * Vac * sin(
t) ) by Iin. Consequently:
Pin 2 * Pin * sin 2(t)
(eq. 79)
In average over the switching period, the bulk capacitor
receives a charge current ( * PinVout) , where is the PFC
stage efficiency, and supplies the averaged load current
I2 * Pin Vout. Applying the famous
“capacitor formula” I C * dVdt, it becomes:
(eq. 78)
* Pin I2 Cbulk * dVout
Vout
dt
Substitution of equation (79) into equation (80) leads to:
(eq. 81)
2
* Pin * sin(2t)
Vout
1
Vout Cbulk * * Vout 2
(eq. 84)
dVout 1 * 2 * * Pin * sin 2(t) * Pin Vout
Vout
dt
Cbulk
Rearranging the terms of this equation, one can obtain:
* Pin Vout * dVout * 2 * sin 2(t) 1 (eq. 82)
dt
Cbulk
d(Vout2)
2 * Vout * dVout and that
Noting that
dt
dt
cos(2t) 1−2 * sin 2(t), one can deduct the square of the
(eq. 80)
Thus:
(eq. 85)
Vout Vout Vout output voltage from the precedent equation:
* Pin * sin(2t)
1 Cbulk
* * Vout 2
Where Vout is the instantaneous output voltage ripple.
Equation (85) can be rearranged as follows:
− * Pin Vout2 Vout 2 * sin(2t) (eq. 83)
Cbulk * where <Vout> is the average output voltage.
Dividing the terms of the precedent equations by the
square of the average output voltage, it becomes:
Vout Vout *
1
(eq. 86)
* Pin * sin(2t)
1
Cbulk * * Vout 2
One can simplify this equation considering that the output voltage ripple is small compared to the average output voltage
(fortunately, it is generally true). This leads to say that the term
words, that
1
* Pin * sin(2t)
Cbulk
is small compared to 1. Thus, one can write that:
* * Vout 2
* Pin * sin(2t)
Pin * sin(2t)
1 Cbulk
11*
2
2
* * Vout Cbulk * * Vout 2
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16
* Pin * sin(2t)
1
Cbulk * * Vout 2
is nearly zero or in other
(eq. 87)
AND8123/D
Conclusion
Substitution of equation (86) into equation (87), leads to
the simplified ripple expression that one can generally find
in the literature:
Compared to traditional switch mode power supplies, one
faces an additional difficulty when trying to predict the
currents and voltages within a PFC stage: the sinusoid
modulation. This is particularly true in critical conduction
mode where the switching ripple cannot be neglected. As
proposed in this paper, one can overcome this difficulty by:
• First calculating their value within a switching period,
• Then the switching period being considered as very
small compared to the AC line cycle, integrating the
result over the sinusoid period.
The proposed theoretical analysis helps predict the stress
faced by the main elements of the PFC stages: coil,
MOSFET, diode and bulk capacitor, with the goal of easing
the selection of the power components and therefore, the
PFC implementation. Nevertheless, as always, it cannot
replace the bench work and the reliability tests necessary to
ensure the application proper operation.
− * Pin * sin(2t)
(eq. 88)
2 * Cbulk * * Vout The maximum ripple is obtained when (sin(2
t) −1)
and minimum when (sin(2t) 1) . Thus, the peak−to−peak
Vout ripple that is the difference of these two values is:
(Vout)pk−pk * Pin (eq. 89)
Cbulk * * Vout And:
Vout Vout (Vout)pk−pk
* sin(2t) (eq. 90)
2
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AND8123/D
Peak Coil Current:
Icoil_pk 2 * 2 * Pin * sin(t)
Vac
Switching Frequency:
f
Maximum Peak Current:
Icoil_max 2 * 2 * Pin max
VacLL
2 * Vac * sin(t)
Vac2
1
Vout
2 * L * Pin Switching Losses:
psw RMS Coil Current:
Icoil(rms) 2 * Pin 3
Vac
2 * (t tFR) * Vac2
Vout *
2 * Vac 4
*L
Conduction Losses:
2
Pon 4 * Ron * Pin *
3
Vac
1
8 * 2 * Vac
3 * Vout
Average Diode Current:
Id Iload Pout
Vout
RMS Diode Current:
Id(rms) 4 *
3
2 *2 * Pin Vac * Vout
L1
D6
CONTROLLER
M1
AC Line
Iload
Vout
+
C1
LOAD
R7
R5
Capacitor Low Frequency Ripple:
(Vout)pk−pk MC33260 like Current Sense Resistor (Rs = R5)
Dissipation:
RMS Capacitor Current:
2
pRs 260 4 * Rs * Pin 3
Vac
Ic(rms) MC33262 like Current Sense Resistor (Rs = R7)
Dissipation:
2
pRs 262 4 * Rs * Pin *
3
Vac
Vac: AC line rms voltage
VacLL: Vac lowest level
: AC line angular frequency
<Pin>: Average input power
<Pin>max: Maximum pin level
* Pin Cbulk * * Vout 8 * 2 * Vac
1
3 * Vout
32 * 2 * Pin 2 Iload(rms) 2
9 * * Vac * Vout
If load is resistive:
Vout: Output voltage
Pout: Output power
Iload: Load current
Iload(rms): RMS load current
: Efficiency
Figure 15. Summary
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Ic(rms) 2
32 * 2 Pin 2
*
Vout
R
9 * Vac * Vout
Ron: MOSFET on resistance
t, tFR: Switching times (see Switching
Losses section and Figure 10)
Cbulk = C1: Bulk capacitor value
Rs: Current sense resistance
L: Coil inductance
AND8123/D
Notes
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AND8123/D
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AND8123/D