SR202A 1. General Description The SR202A is a timing controller for small panel TFT-LCD. It provides horizontal and vertical control timing to TFT-LCD source and gate drivers. Built-in vertical synchronization detection circuit generates vertical synchronization signal internally without the extra components. Built-in phase lock loop sub-function with external VCO and low pass filter produces system clock which synchronizes input composite synchronization signal. SR202A also provides 8 different zoom in/zoom out display modes for 2 different display resolutions. 2. Features z z z z z z z z z z z Programmable resolution mode. Master clock frequency: 30 MHz max. Built-in vertical sync. detection to omit the external sync. separator. Supply voltage: +5.0V or +3.3V. Shift clock signals for the source driver (3-φ Clock). Line inversion driving scheme. Support NTSC/PAL TV system. Provides control timings for source and gate drivers. Provides flip and mirror scan control. Built-in zoom in/zoom out display mode selection. 48 pins LQFP. 3. Block Diagram Rev.2.1 - 1/15 - 0755-89812241 SR202A 4. Pin Assignment Rev.2.1 - 2/15 - 41 0755-89812241 SR202A 5. Pin Description Pin no. Symbol I/O 1 NVCOM O Inverter output of VCOM 2 HZ_OUT O Zoom in control signal 3 OEH O Source driver output enable control signal 4 OEV O Gate driver output enable control signal I Test pin O Odd/even field output 5 MODE (1) 6 FIELD 7 GND 8 MOD_OUT 9 10 RES STVD Description Ground O Simultaneous/sequential sampling control setting of LCD. I Resolution mode setting pin RES=”H”, 1440 resolution mode RES=”L”, 1200 resolution mode O Start pulse for gate driver. (1) STVD is “HiZ”, when UDC=”L” (2) STVD is ”Output”, when UDC=”H” O Start pulse for gate driver. (1) STVU is ”HiZ”, when UDC=”H” (2) STVU is ”Output”, when UDC=”L” 11 STVU 12 VCC Power for internal circuit STHL O Start pulse for source driver. (1) STHL is ”HiZ”, when LRC=”H” (2) STHL is ”Output”, when LRC=”L” 13 14 STHR O Start pulse for source driver. (1) STHR is ”HiZ”, when LRC=”L” (2) STHR is ”Output”, when LRC=”H” 15 PDO O Phase detector output 16 CKV O Shift clock for gate driver 17 CPH1 O Shift clock φ1 for source driver 18 CPH2 O Shift clock φ2 for source driver 19 CPH3 O Shift clock φ3 for source driver 20 ZX1 (2) I Zoom in/out modes setting pin ZX2 (2) I Zoom in/out modes setting pin 22 ZX3 (2) I Zoom in/out modes setting pin 23 GND Ground 24 VCC2 Power for I/O pad 25 VCO_CLK_OUT O Inverted system clock signal output 26 VCO_CLK_IN I System clock input. It connects with external VCO and low pass filter circuits to generate system clock which synchronizes input composite synchronization signal 21 Rev.2.1 - 3/15 - 0755-89812241 SR202A 27 DVS O Negative polarity vertical synchronization signal output 28 DS O Dual scan mode vertical duplication control signal 29 HWRESETZ I Active low global reset signal input 30 VS I Negative polarity vertical synchronization signal input which is from the external synchronization separator circuits Pin no. Symbol I/O Description 31 UDC_INV 32 Z1_MODE (1) (1) O UDC inverted signal output I Test pin I Test pin 33 DS_EN 34 DHS O Horizontal synchronization signal output with negative polarity 35 CVS I Composite synchronization signal input with positive polarity 36 GND Ground 37 UDC I Up / Down scan setting pin (1) Normal scan, when UDC=”L” (2) Reverse scan, when UDC=”H” 38 VZ_MODE (1) I Test pin 39 LRC I Left / Right scan setting pin (1) Normal scan, LRC=”L” (2) Reverse scan, LRC=”H” 40 LRC_INV O LRC inverted signal output 41 VS_DET O Test pin VS detection setting pin (1) VS is from external detection , when EXT_VS=”H” (2) VS is from internal detection , when EXT_VS=”L” 42 EXT_VS I 43 NPC I/O Video signal input format setting pin; pull-up for normal operation. 44 VCOM O Toggling signal for common electrode generation circuits 45 EXT_NPC I NPC I/O setting pin (1) NPC is “Output”, when EXT_NPC =”L” (2) NPC is “Input”, when EXT_NPC =”H” 46 HS_REF_FBO O Reference signal output for phase lock loop operation 47 HS_REF_FBI I Reference signal input for phase lock loop operation 48 VCC Power for internal circuit Note:(1) These test pins should be set “OPEN” for normal operation. Rev.2.1 - 4/15 - 0755-89812241 SR202A (2) Zoom in/out display mode setting: Display Mode Full Zoom1 zoomWide1 Normal Rev.2.1 ZX1 H L H L ZX2 H H L L ZX3 Display Characteristics (4:3 aspect-ratio input signal) Remark H Input signals are displayed on full screen.(To display 4:3 signal on 16:9 screen) H Central 176 lines of input signals are displayed on full screen. (Vertically extension, zoom factor =4/3). H Central 176 lines of input signals are displayed on full screen. (Vertically extension and different horizontal timing scaling). H Input signal(4:3) are displayed on center 75% screen.(4:3 aspect-ratio). - 5/15 - 0755-89812241 SR202A Display Mode Zoom2 Wide ZoomWide2 Zoom3 Rev.2.1 ZX1 H L H L ZX2 H H L L ZX3 Display Characteristics (4:3 aspect-ratio input signal) Remark L Lower 205 lines of input signals are displayed on full screen.(Zoom factor=8/7, vertically offset extension). L Input signals are displayed on full screen.(Different horizontal timing scaling). L Lower 205 lines of input signal are displayed on full screen. (Vertically extension and different horizontal timing scaling). L Center 205 lines of input signal are displayed on full screen. (Vertically extension, zoom factor=8/7). - 6/15 - 0755-89812241 SR202A 6. DC Characteristics 6.1 Absolute maximum ratings: Parameter Symbol Rating Units Power supply VCC,VCC2 -0.3 to 6.0 V Input voltage VIN -0.3 to VCC2 +0.3 V Output voltage VOUT -0.3 to VCC2 +0.3 V Storage temperature TSTG -40 to 125 ºC 6.2 Recommended operating conditions: Parameter Symbol Min. Typ. Max. Units Power supply VCC,VCC2 3.0 5.0 5.5 V Input voltage VIN 0 - VCC V Operating temperature TOPR TBD - 85 ºC Symbol Condition Min Typ Max Units Input low current IIL No pull-up or pull-down -1 - 1 μA Input high current IIH No pull-up or pull-down -1 - 1 μA Tri-state leakage current IOZ -10 - 10 μA Input capacitance CIN - 3 - pF COUT 3 - 6 pF 6.3 Electrical Characteristics: Parameter Output capacitance Logic input low voltage VIL CMOS - - 0.3VCC2 V VSI(1) CMOS - TBD - V VIH CMOS 0.7VCC2 - - V Schmitt input high voltage VSIH(1) CMOS - TBD - V Output low voltage VOL (2) IOL=4mA - - 0.2VCC2 V Output high voltage VOH(3) IOH=-4mA 0.8VCC2 - - V Input pull up/down resistance RI VIL= 0V or VIH= VCC2 40 - 100 KΩ Schmitt input low voltage Logic input high voltage Note:(1) HWRESETZ, VCO_CLK_IN, VS, CVS, HS_REF_FBI. (2)VOL is 0.3VCC2 when VCC2 = 3V (3)VOH is 0.7VCC2 when VCC2 = 3V Rev.2.1 - 7/15 - 0755-89812241 SR202A 6.4 Current consumption for 5 Volts operating: Parameter Symbol Full Chip Current Consumption IIN Conditions Min. Typ. Max. Units Vcc=+5.0V, fOSC = 23.2 MHz - 14 21.5 mA Vcc=+5.0V, fOSC = 29.1 MHz - 16 23.5 mA 7. AC Characteristics 7.1 1440 mode a. Input signal characteristics PARAMETER Symbol Min. Typ. Max. Unit. tOSC 33 34 35 ns tH 61.5 63.5 65.5 us CVS pulse width tCVS 4 4.7 5.4 us CVS rising time tCr - - 700 ns CVS falling time tCf - - 300 ns VS pulse width tVS 1 3 5 tH VS rising time tVr - - 700 ns VS falling time tVf - - 1.5 us NTSC - 262.5 - line PAL - 312.5 - line Symbol Min. Typ. Max. Unit. Rising time tr - - 10 ns Falling time tf - - 10 ns Clock high and low level pulse width tCPH - 3 - tOSC Clock pulse duty tCWH 40 50 60 % tC12, tC23, tC31 - tCPH/3 - ns STH setup time tSUH - tCPH/2 - tCPH STH pulse width tSTH - 1 - tCPH DHS pulse width tHS - 46 - tCPH OEH pulse width tOEH - 12 - tCPH Sample & hold disable time tDIS1 - 80 - tCPH OEV pulse width tOEV - 46 - tCPH CKV pulse width tCKV - 37 - tCPH HS_REF_FBO period tCP - 1 - tH tWCP - 1/2 - tH DHS-OEH time t1 - 34 - tCPH DHS-CKV time t2 - 28 - tCPH VCO_CLK_IN period CVS period Horizontal field lines per b. Output signal characteristics PARAMETER 3-φ clock phase difference HS_REF_FBO pulse duty Rev.2.1 - 8/15 - 0755-89812241 SR202A DHS-OEV time t3 - 8 - tCPH DHS-HS_REF_FBO time t4 - 32 - tCPH STV setup time tSUV - 16 - tCPH STV pulse width tSTV - 1 - tH NTSC tVS1 - 19 - tH PAL tVS1 - 27 - tH Symbol Min. Typ. Max. Unit. tOSC 40.3 41.6 43 ns tH 61.5 63.5 65.5 us CVS pulse width tCVS 4 4.7 5.4 us CVS rising time tCr - - 700 ns CVS falling time tCf - - 300 ns VS pulse width tVS 1 3 5 tH VS rising time tVr - - 700 ns VS falling time tVf - - 1.5 us NTSC - 262.5 - line PAL - 312.5 - line Symbol Min. Typ. Max. Unit. tr - - 10 ns tf - - 10 ns Clock high and low level pulse width(2) tCPH - 3 - tOSC Clock pulse duty tCWH 40 50 60 % tC12, tC23, tC31 - tCPH/3 - ns STH setup time tSUH - tCPH/2 - tCPH STH pulse width tSTH - 1 - tCPH DHS pulse width tHS - 36 - tCPH OEH pulse width tOEH - 9 - tCPH Sample & hold disable time tDIS1 - 61 - tCPH OEV pulse width tOEV - 40 - tCPH CKV pulse width tCKV - 50 - tCPH HS_REF_FBO period tCP - 1 - tH tWCP - 1/2 - tH DVS-STV time Note:(1) For all of the logic signals. (2) CPH1~3. (3) When ZX1, ZX2, ZX3 are all Hi. 7.2 1200 mode a. Input signal characteristics PARAMETER VCO_CLK_IN period CVS period Horizontal field lines per b. Output signal characteristics PARAMETER Rising time (1) (1) Falling time 3-φlock phase difference HS_REF_FBO pulse WIDTH Rev.2.1 - 9/15 - 0755-89812241 SR202A DHS-OEH time t1 - 27 - tCPH DHS-CKV time t2 - 14 - tCPH DHS-OEV time t3 - 12 - tCPH DHS-HS_REF_FBO time t4 - 26 - tCPH STV setup time tSUV - 8 - tCPH STV pulse width tSTV - 1 - tH NTSC tVS1 - 19 - tH PAL tVS1 - 27 - tH DVS-STV Note:(1) For all of the logic signals. (2) CPH1~3. (3) When ZX1, ZX2, ZX3 are all Hi. 7.3 Zoom in/out display mode 7.3.1 1440 mode Zoom mode Horizontal Display Start Vertical Display Start L 12.94us 33H L L 12.98us 45H L H L 12.98us 19H H H L 12.94us 45H L L H 8.83us 19H H L H 12.98us 48H L H H 12.94us 48H H H H 12.94us 19H From falling edge of DHS to rising edge of STHL(R) From falling edge of DVS to rising edge of STVU(D) Horizontal Display Start Vertical Display Start ZX1 ZX2 ZX3 L L H Remark 7.3.2 1200 mode Zoom mode ZX1 ZX2 ZX3 L L L 12.59us 33H H L L 12.65us 45H L H L 12.65us 19H H H L 12.59us 45H L L H 8.65us 19H H L H 12.65us 48H L H H 12.59us 48H H H H 12.59us 19H From falling edge of DHS to rising edge of STHL(R) From falling edge of DVS to rising edge of STVU(D) Remark Rev.2.1 - 10/15 - 0755-89812241 SR202A 8. Waveform 8.1 VCO_CLK, STHL(R) and CPH1~3 timing waveform Rev.2.1 - 11/15 - 0755-89812241 SR202A 8.2 CVS and horizontal control timing waveform 8.3 CVS and vertical shift clock timing waveform Rev.2.1 - 12/15 - 0755-89812241 SR202A 8.4 CVS and vertical control timing waveform Rev.2.1 - 13/15 - 0755-89812241 SR202A 9 Application circuit 14a 13ay 12ax 11a 10b 9c 4c 5cx 6mh 7vcc 8vss b15 2bx 3cy 6vdd 1by U4 4053 VSY VB VB1 R75 2 1 - O U10 NJM2107F G + V 5 V5 R157 68K Rev.2.1 4.7K R159 C64 104 - 14/15 - CKV PDO 15 STHR 14 STHL 13 10K R74 100 R145 7 6 5 100 R143 4 2 P5 1 100 R144 V5 C60 100p 5 10K VCOM C41 10U 7 CO1 C47 10U V5 104 C42 1M R161 R160 100 VR VG VB V5 P4 R108 100 R142 100 3 6 RV14 10K 47P C66 RL1 P3 P5 P10 P11 P6 P7 P8 P3 8 +5V HS-REF-FBI 9 1K R107 R106 R163 2.7K R162 100 C67 104 4.7K R158 16 17 CPH1 18 CPH2 19 CPH3 21 20 ZX2 L15 1.5UH P26/0.5 10 8 102 C65 4 HF 11 RV13 U7 JRC3414A 3 3 HZ -10V +15V P2 P1 P9 UDI P4 VCOM 100 2 R98 2.7K -10V M2X355 DH2 RV15 R105 100 JP5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 12 1 R95 24K 100 CSC8806A P13 P12 R102 10K R101 1M 82K C57 104 R104 100 RL1 UDI P14 ZX1 22 GND 23 R? R/L 1K R103 100 C54 560P P11 P10 P1 P2 10K U/D V5 P14/2 HZ-OUT NVCOM 48 37 V5 NS-REF-FBO V5 GND 14 46 R100 2.7K 47 GND EXT-NPC CVS 36 12 OEH VCOM 35 DHS 45 R971K 11 13 34 OEV 44 CSY R?1K DS-EN FRP GND 33 NPC 10 HSY FIELD MODE 43 SYS GND GND ZI-MODE EXT-VS R94 100 8 UDC-INV 32 VR1 SR202A VS 31 42 R/L1 9 30 100 R96 MOD-OUT VS-DET U/D1 RESET UDC 7 VSY R93 100 RES LRC-INV VG1 5 6 DS 29 4 STVD 41 R DVS 40 3 104 27 C40 28 R59 10K +5V STVU LRC G R76 R77 R78 U3 VCO-IN VZ-MODE 2 VCO-OUT 26 R35 100 39 B 38 VB1 1 ZX3 25 V5 JP3 +5V 24 R60 R63 R66 R70 R71 R72 R73 10K 10K 10K 100 100 100 100 R86 22K 4 VG P14 P12 P13 V5 3K R155 P8 R156 10K HZ HF VR 3 P9 C2 E2 XN4501 Q4 A1015 1 2 P7 C1 B2 P6 E1 B1 V5 4 R153 150K U8 VR1 5 V5 C63 102 6 180K R154 15K R89 C53 105 V5 R88 15K V5 R92 39K R91 10K V5 R90 15K VG1 CSY R87 10K -10V R151 20K R148 20K T V5 10K R149 0755-89812241 10k R150 R152 10K S D F SR202A 10. Packages Outline(Unit:μm)： 10.1:LQFP48 Rev.2.1 - 15/15 - 0755-89812241