TLV3201 TLV3202 www.ti.com SBOS561A – MARCH 2012 – REVISED JUNE 2012 40-ns, microPOWER, Push-Pull Output Comparators Check for Samples: TLV3201, TLV3202 FEATURES DESCRIPTION • • The TLV3201 and TLV3202 are single- and dualchannel comparators that offer the ultimate combination of high-speed (40 ns) and low-power consumption (40 µA), all in extremely small packages with features such as rail-to-rail inputs, low offset voltage (1 mV), and large output drive current. The devices are also very easy to implement in a wide variety of applications where response time is critical. 1 2 • • • • • • Low Propagation Delay: 40 ns Low Quiescent Current: 40 µA per Channel Input Common-Mode Range Extends 200 mV Beyond Either Rail Low Input Offset Voltage: 1 mV Push-Pull Outputs Supply Range: +2.7 V to +5.5 V Industrial Temperature Range: –40°C to +125°C Small Packages: SC70-5, SOT23-5, SOIC-8, MSOP-8 The TLV320x family is available in single (TLV3201) and dual (TLV3202) channel versions, both with push-pull outputs. The TLV3201 is available in SOT23-5 and SC70-5 packages. The TLV3202 is available in SOIC-8 and MSOP-8 packages. All devices are specified for operation across the expanded industrial temperature range of –40°C to +125°C. APPLICATIONS • • • • • Inspection Equipment Test and Measurement High-Speed Sampling Systems Telecom Portable Communications RELATED PRODUCTS DEVICE D AND DGK PACKAGES SOIC-8 AND MSOP-8 (TOP VIEW) DESCRIPTION TLV3011 5-µA (max) open-drain, 1.8-V to 5.5-V with integrated voltage reference in 1.5-mm × 1.5-mm micro-sized packages TLV3012 5-µA (max) push-pull, 1.8-V to 5.5-V with integrated voltage reference in micro-sized packages TLV3501 4.5-ns, rail-to-rail, push-pull comparator in microsized packages LMV7235 75-ns, 65-µA, 2.7-V to 5.5-V, rail-to-rail input comparator with open-drain output REF3333 30-ppm/°C drift, 3.9-µA, SOT23-3, SC70-3 voltage reference DCK AND DBV PACKAGES SC70-5 AND SOT23-5 (TOP VIEW) 1OUT 1 8 VCC 1IN- 2 7 2OUT 1IN+ 3 6 2IN- GND 4 5 2IN+ OUT 1 GND 2 IN+ 3 5 VCC 4 IN- 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TLV3201 TLV3202 SBOS561A – MARCH 2012 – REVISED JUNE 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD (2) PACKAGE DESIGNATOR PACKAGE MARKING ORDERING NUMBER SOT23-5 DBV RAI TLV3201AIDBV SC70-5 DCK SDP TLV3201AIDCK SOIC-8 D TL3202 TLV3202AID MSOP-8 DGK VUDC TLV3202AIDGK TLV3201 TLV3202 (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and printed circuit board (PCB) design guidelines are available at www.ti.com/sc/package. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE UNIT 7 V –0.5 to (VCC) + 0.5 V ±10 mA 100 mA Operating temperature range –55 to +125 °C Storage temperature range, Tstg –65 to +150 °C +150 °C Supply voltage Signal input terminals Voltage (2) Current (2) Output short circuit (3) Junction temperature, TJ Electrostatic discharge (ESD) ratings TLV3201 Human body model (HBM) 2000 V Electrostatic discharge (ESD) ratings TLV3202 Human body model (HBM) 1000 V (1) (2) (3) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal. Short-circuit to ground. Copyright © 2012, Texas Instruments Incorporated TLV3201 TLV3202 www.ti.com SBOS561A – MARCH 2012 – REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS: VCC = 5.0 V At TA = +25°C and VCC = 5.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX 1 5 UNIT OFFSET VOLTAGE VCM = VCC / 2 VIO Input offset voltage dVOS/dT Input offset voltage drift TA = –40°C to +125°C PSRR Power-supply rejection ratio VCM = VCC / 2, VCC = 2.5 V to 5.5 V TA = –40°C to +125°C 1 65 Input hysteresis mV 6 mV 10 μV/°C 85 dB 1.2 mV INPUT BIAS CURRENT IIB IIO VCM = VCC / 2 Input bias current 1 TA = –40°C to +125°C VCM = VCC / 2 Input offset current 1 TA = –40°C to +125°C 50 pA 5 nA 50 pA 2.5 nA INPUT VOLTAGE RANGE VCM Common-mode voltage range TA = –40°C to +125°C CMRR Common-mode rejection ratio –0.2 V < VCM < 5.2 V (VEE) – 0.2 60 (VCC) + 0.2 70 V dB INPUT IMPEDANCE Common-mode 1013 || 2 Ω || pF Differential 1013 || 4 Ω || pF SWITCHING CHARACTERISTICS Low to high tpd Input overdrive = 20 mV, CL = 15 pF 47 50 ns Input overdrive = 100 mV, CL = 15 pF 43 50 ns TA = –40°C to +125°C Propagation delay time High to low 55 ns Input overdrive = 20 mV, CL = 15 pF 45 50 ns Input overdrive = 100 mV, CL = 15 pF 42 50 ns 55 ns TA = –40°C to +125°C Propagation delay skew Propagation delay matching (TLV3202) Input overdrive = 20mV, CL = 15 pF High to low, Low to High 2 Input overdrive = 20 mV, CL = 15 pF ns 5 ns tr Rise time 10% to 90% 2.9 ns tf Fall time 10% to 90% 3.7 ns ISINK = 4 mA 175 OUTPUT VOL From lower rail Voltage output swing VOH From upper rail TA = –40°C to +125°C ISOURCE = 4 mA 120 TA = –40°C to +125°C ISC sinking 40 TA = –40°C to +125°C ISC Short-circuit current (per comparator) ISC sourcing 52 TA = –40°C to +125°C 190 mV 225 mV 140 mV 170 mV 48 mA See Typical Curve mA 60 mA See Typical Curve mA POWER SUPPLY VCC IQ Specified voltage Quiescent current 2.7 40 TA = –40°C to +125°C 5.5 V 50 μA 65 μA TEMPERATURE Specified range –40 +125 °C Storage range –65 +150 °C Copyright © 2012, Texas Instruments Incorporated 3 TLV3201 TLV3202 SBOS561A – MARCH 2012 – REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS: VCC = 2.7 V At TA = +25°C and VCC = 2.7 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX 1 5 UNIT OFFSET VOLTAGE VCM = VCC / 2 VIO Input offset voltage dVOS/dT Input offset voltage drift TA = –40°C to +125°C PSRR Power-supply rejection ratio VCM = VCC / 2, VCC = 2.5 V to 5.5 V TA = –40°C to +125°C 1 65 Input hysteresis mV 6 mV 10 μV/°C 85 dB 1.2 mV INPUT BIAS CURRENT IIB IIO VCM = VCC / 2 Input bias current 1 TA = –40°C to +125°C VCM = VCC / 2 Input offset current 1 TA = –40°C to +125°C 50 pA 5 nA 50 pA 2.5 nA INPUT VOLTAGE RANGE VCM Common-mode voltage range TA = –40°C to +125°C CMRR Common-mode rejection ratio –0.2 V < VCM < 2.9 V (VEE) – 0.2 56 (VCC) + 0.2 68 V dB INPUT IMPEDANCE Common-mode 1013 || 2 Ω || pF Differential 1013 || 4 Ω || pF SWITCHING CHARACTERISTICS Low to high tpd Input overdrive = 20 mV, CL = 15 pF 47 50 ns Input overdrive = 100 mV, CL = 15 pF 42 50 ns TA = –40°C to +125°C Propagation delay time High to low 55 ns Input overdrive = 20 mV, CL = 15 pF 40 50 ns Input overdrive = 100 mV, CL = 15 pF 38 50 ns 55 ns TA = –40°C to +125°C Propagation delay skew Propagation delay matching (TLV3202) Input overdrive = 20mV, CL = 15 pF High to low, Low to High 2 Input overdrive = 20 mV, CL = 15 pF ns 5 ns tr Rise time 10% to 90% 4.8 ns tf Fall time 10% to 90% 5.2 ns ISINK = 4 mA 230 OUTPUT VOL From lower rail Voltage output swing VOH From upper rail TA = –40°C to +125°C ISOURCE = 4 mA 210 TA = –40°C to +125°C ISC sinking 13 TA = –40°C to +125°C ISC Short-circuit current (per comparator) ISC sourcing 15 TA = –40°C to +125°C 260 mV 325 mV 250 mV 350 mV 19 mA See Typical Curve mA 21 mA See Typical Curve mA POWER SUPPLY VCC IQ Specified voltage Quiescent current 2.7 36 TA = –40°C to +125°C 5.5 V 46 μA 60 μA TEMPERATURE 4 Specified range –40 +125 °C Storage range –65 +150 °C Copyright © 2012, Texas Instruments Incorporated TLV3201 TLV3202 www.ti.com SBOS561A – MARCH 2012 – REVISED JUNE 2012 THERMAL INFORMATION TLV3201 THERMAL METRIC (1) TLV3202 DBV (SOT23) DCK (SC70) D (SOIC) DGK (MSOP) 5 PINS 5 PINS 8 PINS 8 PINS 201.9 θJA Junction-to-ambient thermal resistance 237.8 281.9 146.3 θJCtop Junction-to-case (top) thermal resistance 108.7 97.6 97.2 92.5 θJB Junction-to-board thermal resistance 64.1 68.3 84.2 123.3 ψJT Junction-to-top characterization parameter 12.1 2.6 45.5 23.0 ψJB Junction-to-board characterization parameter 63.3 67.3 83.7 121.6 θJCbot Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. PIN CONFIGURATIONS D AND DGK PACKAGES SOIC-8 AND MSOP-8 (TOP VIEW) DCK AND DBV PACKAGES SC70-5 AND SOT23-5 (TOP VIEW) 1OUT 1 8 VCC 1IN- 2 7 2OUT 1IN+ 3 6 2IN- GND 4 5 2IN+ OUT 1 GND 2 IN+ 3 5 VCC 4 IN- PIN DESCRIPTIONS: D, DGK NAME NO. DESCRIPTION 1IN– 2 Negative input, comparator 1 1IN+ 3 Positive input, comparator 1 1OUT 1 Output, comparator 1 2IN– 6 Negative input, comparator 2 2IN+ 5 Positive input, comparator 2 2OUT 7 Output, comparator 2 GND 4 Negative supply, ground VCC 8 Positive supply NAME NO. DESCRIPTION OUT 1 Output GND 2 Negative supply, ground IN+ 3 Positive input VCC 5 Positive supply IN– 4 Negative input PIN DESCRIPTIONS: DCK, DBV Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 5 TLV3201 TLV3202 SBOS561A – MARCH 2012 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, VCC = +5 V, and input overdrive (VOD) = 20 mV, unless otherwise noted. HYSTERESIS DISTRIBUTION 30 Pecentage of Amplifiers (%) 27 24 21 18 15 12 9 6 3 Offset Voltage (mV) 3 2.8 2.6 2.4 2 2.2 1.8 1.6 1.4 1 1.2 OFFSET VOLTAGE vs COMMON-MODE VOLTAGE 6 5 Typical Units Shown 5 VCC = 2.7 V 5 Typical Units Shown Offset Voltage (mV) 4 1 0 −1 −2 3 2 1 0 −1 −3 −2 −4 −3 5 20 35 50 65 Temperature (°C) 80 95 −4 −0.5 110 125 0 0.5 1 1.5 2 Common−Mode Voltage (V) G002 Figure 3. 2.5 3 G003 Figure 4. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE OFFSET VOLTAGE vs POWER SUPPLY 6 5 VCC = 5.5 V 5 Typical Units Shown Offset Voltage (mV) 3 3 2 1 0 −1 2 1 0 −1 −2 −2 −3 −3 −4 −4 −0.5 0 8 Typical Units Shown 4 4 Offset Voltage (mV) 0.8 OFFSET VOLTAGE vs TEMPERATURE −5 −40 −25 −10 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Common−Mode Voltage (V) 5 5.5 6 −5 2.5 G004 Figure 5. 6 0.6 Figure 2. 2 5 G001 Figure 1. 3 Offset Voltage (mV) 0.4 0 Hysteresis (mV) G000 5 4 0.2 0 −5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Pecentage of Amplifiers (%) OFFSET VOLTAGE DISTRIBUTION 26 24 22 20 18 16 14 12 10 8 6 4 2 0 3 3.5 4 4.5 Supply Voltage (V) 5 5.5 G005 Figure 6. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 TLV3201 TLV3202 www.ti.com SBOS561A – MARCH 2012 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VCC = +5 V, and input overdrive (VOD) = 20 mV, unless otherwise noted. COMMON-MODE REJECTION RATIO AND POWERSUPPLY REJECTION RATIO vs TEMPERATURE INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs TEMPERATURE 110 10000 Input Bias Current (pA) CMRR and PSRR (dB) 100 90 80 70 CMRR at VCC = 2.7 V CMRR at VCC = 5.0 V PSRR 60 50 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 − IB + IB IOS 1000 100 10 1 0.1 −50 110 125 −25 0 G006 25 50 Temperature (°C) 75 100 125 G002 Figure 8. INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE 30 25 20 15 10 5 0 −5 −10 −15 −20 −25 −30 20 + IB − IB IOS VS=2.7V + IB − IB IOS VS= 5.5V 15 Input Bias Current (pA) Input Bias Current (pA) Figure 7. 10 5 0 −5 −10 −15 0.0 0.5 1.0 1.5 2.0 Common−Mode Input Voltage (V) −20 2.5 0 1 G006 2 3 4 Common−Mode Input Voltage (V) Figure 9. G006 Figure 10. QUIESCENT CURRENT DISTRIBUTION QUIESCENT CURRENT vs SUPPLY VOLTAGE 65 35 30 Quiescent Current (µA) Pecentage of Amplifiers (%) 5 25 20 15 10 55 −40°C 25°C 125°C 45 35 25 5 15 2.5 Supply Current (µA) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 0 3 3.5 4 4.5 Supply Voltage (V) 5 5.5 G018 G000 Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 7 TLV3201 TLV3202 SBOS561A – MARCH 2012 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VCC = +5 V, and input overdrive (VOD) = 20 mV, unless otherwise noted. QUIESCENT CURRENT vs SWITCHING FREQUENCY SHORT-CIRCUIT CURRENT vs TEMPERATURE 90 ISC, Source: VCC = 5 V ISC, Sink: VCC = 5 V ISC, Sink: VCC = 2.7 V ISC, Source: VCC = 2.7 V Short Circuit Current (mA) 80 70 60 50 40 30 20 10 −40 −15 10 Figure 13. Sourcing Current 4.9 3.7 −40°C 25°C 75°C 125°C Output Voltage (V) VCC = 2.7 V 2.5 1.3 −40°C 25°C 75°C 125°C 0.1 −1.1 −2.3 −3.5 −4.7 Sinking Current 0 5 10 Output Current (mA) 15 −5.9 20 Sinking Current 0 10 G015 40 60 80 20 30 40 Output Current (mA) 50 60 G017 Figure 16. PROPAGATION DELAY RISING EDGE Input Voltage (mV) 3 Output: VOD = 20 mV 2.6 Input: VOD = 20 mV 2.1 Output: VOD = 100 mV 1.7 Input: VOD = 100 mV 1.3 0.9 0.4 0 −0.4 −0.9 −1.3 −1.7 −2.1 −2.6 −3 100 120 140 160 180 200 220 Time (ns) Output Voltage (V) Input Voltage (mV) VCC = 5.5 V 140 120 100 80 60 40 20 0 −20 −40 −60 −80 −100 −120 −140 20 40 60 G000 80 3 2.6 2.1 1.7 1.3 0.9 0.4 0 −0.4 −0.9 −1.3 Output: VOD = 20 mV −1.7 Input: VOD = 20 mV Output: VOD = 100 mV −2.1 Input: VOD = 100 mV −2.6 −3 100 120 140 160 180 200 220 240 Time (ns) Output Voltage (V) Output Voltage (V) Sourcing Current Figure 17. 8 G014 OUTPUT VOLTAGE vs OUTPUT CURRENT PROPAGATION DELAY FALLING EDGE 20 110 125 5.9 Figure 15. 140 120 100 80 60 40 20 0 −20 −40 −60 −80 −100 −120 −140 85 Figure 14. OUTPUT VOLTAGE vs OUTPUT CURRENT 2.8 2.4 2 1.6 1.2 0.8 0.4 0 −0.4 −0.8 −1.2 −1.6 −2 −2.4 −2.8 35 60 Temperature (°C) G019 Figure 18. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 TLV3201 TLV3202 www.ti.com SBOS561A – MARCH 2012 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VCC = +5 V, and input overdrive (VOD) = 20 mV, unless otherwise noted. PROPAGATION DELAY vs INPUT OVERDRIVE PROPAGATION DELAY vs TEMPERATURE 100 50 PDHL: 5 V PDLH: 5 V PDHL: 2.7 V PDLH: 2.7 V 80 70 60 50 40 30 20 10 0 46 44 42 40 38 36 34 32 20 30 40 50 60 70 Input Overdrive (mV) 80 90 30 −40 −25 −10 100 5 G003 80 95 110 125 G017 Figure 20. PROPAGATION DELAY vs COMMON-MODE VOLTAGE PROPAGATION DELAY vs COMMON-MODE VOLTAGE 60 VCC= 2.7V Falling Edge Rising Edge VCC= 5.5V 58 PROPAGATION DELAY (ns) 58 56 54 52 50 48 46 44 42 Falling Edge Rising Edge 56 54 52 50 48 46 44 42 40 −0.2 0.2 0.6 1 1.4 1.8 2.2 Common−Mode Input Voltage (V) 2.6 40 −0.2 2.9 0.4 1 G017 1.6 2.2 2.8 3.4 4 4.6 Common−Mode Input Voltage (V) Figure 21. PROPAGATION DELAY vs SUPPLY VOLTAGE 58 G017 PROPAGATION DELAY vs CAPACITIVE LOAD 60 PDLH:Vod = 20 mV PDHL:Vod = 20 mV PDLH:Vod = 50 mV PDHL:Vod = 50 mV Falling Edge Rising Edge Propagation Delay (ns) 56 54 52 50 48 46 44 55 45 42 40 2.5 5.2 5.7 Figure 22. 60 Propagation Delay (ns) 20 35 50 65 Temperature (°C) Figure 19. 60 PROPAGATION DELAY (ns) Falling Edge Rising Edge 48 Propagation Delay (ns) Propagation Delay (ns) 90 VCC= 5.5 V 3 3.5 4 4.5 Supply Voltage (V) 5 5.5 35 0 G005 Figure 23. 25 50 Capacitive Load (pF) 75 100 G024 Figure 24. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 9 TLV3201 TLV3202 SBOS561A – MARCH 2012 – REVISED JUNE 2012 www.ti.com APPLICATION INFORMATION The TLV3201 and TLV3202 are single- and dual-supply (respectively), push-pull comparators featuring 40 ns of propagation delay on only 40 µA of supply current. This combination of fast response time and minimal power consumption make the TLV3201 and TLV3202 excellent comparators for portable, battery-powered applications as well as fast-switching threshold detection such as pulse-width modulation (PWM) output monitors and zerocross detection. COMPARATOR INPUTS The TLV3201 and TLV3202 are rail-to-rail input comparators, with an input common-mode range that exceeds the supply rails by 200 mV for both positive and negative supplies. The devices are specified from 2.7 V to 5.5 V, with room temperature operation from 2.5 V to 5.5 V. The TLV3201 and TLV3202 are designed to prevent phase inversion when the input pins exceed the supply voltage. Figure 25 shows the TLV320x response when input voltages exceed the supply, resulting in no phase inversion. 5 Output Voltage Input Voltage 4 3 Voltage (V) 2 1 0 −1 −2 −3 −4 −5 0 20 40 60 80 100 120 140 160 180 200 Time (ns) G000 Figure 25. No Phase Inversion: Comparator Response to Input Voltage (Prop Delay Included) The electrostatic discharge (ESD) protection input structure of two back-to-back diodes and 1-kΩ series resistors are used to limit the differential input voltage applied to the precision input of the comparator by clamping input voltages that exceed VCC beyond the specified operating conditions. If potential overvoltage conditions that exceed absolute maximum ratings are present, the addition of external bypass diodes and resistors is recommended, as shown in Figure 26. Large differential voltages greater than the supply voltage should be avoided to prevent damage to the input stage. 1 kW Clamp +In Core -In 1 kW Figure 26. TLV3201 equivalent input structure 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 TLV3201 TLV3202 www.ti.com SBOS561A – MARCH 2012 – REVISED JUNE 2012 EXTERNAL HYSTERESIS The TLV3201 and TLV3202 have a hysteresis transfer curve (shown in Figure 27) that is a function of the following three components: • VTH: the actual set voltage or threshold trip voltage • VOS: the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip point at which the comparator must respond in order to change output states. • VHYST: internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise. VTH + VOS - VHYST VTH + VOS VTH + VOS + VHYST Figure 27. TLV3201 Hysteresis Transfer Curve Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 11 TLV3201 TLV3202 SBOS561A – MARCH 2012 – REVISED JUNE 2012 www.ti.com Inverting Comparator With Hysteresis The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator supply voltage (VCC), as shown in Figure 28. When VIN at the inverting input is less than VA, the output voltage is high (for simplicity assume VO switches as high as VCC). The three network resistors can be represented as R1 || R3 in series with R2. The lower input trip voltage (VA1) is defined by Equation 1: R2 VA1 = VCC ´ (R1 || R3) + R2 (1) When VIN is greater than [VA × (VIN > VA)], the output voltage is low, very close to ground. In this case, the three network resistors can be presented as R2 || R3 in series with R1. The upper trip voltage (VA2) is defined by Equation 2: R2 || R3 VA2 = VCC ´ R1 + (R2 || R3) (2) The total hysteresis provided by the network is defined by Equation 3: DVA = VA1 - VA2 (3) +VCC +5 V R1 1 MW VIN 5V RLOAD 100 kW VA VO VA2 VA1 0V 1.67 V R3 1 MW R2 1 MW VO High +VCC R1 VIN 3.33 V VO Low +VCC R3 R1 VA1 VA2 R2 R2 R3 Figure 28. TLV3201 in Inverting Configuration with Hysteresis 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 TLV3201 TLV3202 www.ti.com SBOS561A – MARCH 2012 – REVISED JUNE 2012 Noninverting Comparator with Hysteresis A noninverting comparator with hysteresis requires a two-resistor network, as shown in Figure 29, and a voltage reference (VREF) at the inverting input. When VIN is low, the output is also low. For the output to switch from low to high, VIN must rise up to VIN1. VIN1 is calculated by Equation 4: VREF VIN1 = R1 ´ ´ VREF (4) R2 When VIN is high, the output is also high. In order for the comparator to switch back to a low state, VIN must equal VREF before VA is again equal to VREF. VIN can be calculated by Equation 5: VREF (R1 + R2) - VCC ´ R1 VIN2 = (5) R2 The hysteresis of this circuit is the difference between VIN1 and VIN2, as defined by Equation 6. R1 DVIN = VCC ´ R2 (6) +VCC +5 V VREF +2.5 V VO VA VIN RLOAD R1 330 kW R2 1 MW VO High +VCC VO Low VIN1 R2 R1 VA = VREF VA = VREF R1 R2 5V VO VIN2 VIN1 0V 1.675 V 3.325 V VIN VIN2 Figure 29. TLV3201 in Noninverting Configuration with Hysteresis CAPACITIVE LOADS The TLV3201 and TLV3202 feature a push-pull output. When the output switches, there is a direct path between VCC and ground, causing increased output sinking or sourcing current during the transition. Following the transition the output current decreases and supply current returns to 40 µA, thus maintaining low power consumption. Under reasonable capacitive loads, the TLV3201 and TLV3202 maintain specified propagation delay (see the Typical Characteristics), but excessive capacitive loading under high switching frequencies may increase supply current, propagation delay, or induce decreased slew rate. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 13 TLV3201 TLV3202 SBOS561A – MARCH 2012 – REVISED JUNE 2012 www.ti.com CIRCUIT LAYOUT The TLV3201 and TLV3202 are fast-switching, high-speed comparators and require high-speed layout considerations. For best results, the following layout guidelines should be maintained: 1. Use a printed circuit board (PCB) with a good, unbroken low-inductance ground plane. 2. Place a decoupling capacitor (0.1-μF ceramic, surface-mount capacitor) as close as possible to VCC. 3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback around the comparator. Keep inputs away from the output. 4. Solder the device directly to the PCB rather than using a socket. 5. For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less) placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some degradation to propagation delay when the impedance is low. The topside ground plane runs between the output and inputs. 6. The ground pin ground trace runs under the device up to the bypass capacitor, shielding the inputs from the outputs. APPLICATIONS CIRCUITS One of the benefits of ac coupling a single-supply comparator circuit is that it can block dc offsets induced by ground-loop offsets that could potentially produce either a false trip or a common-mode input violation. Figure 30 shows the TLV3201 configured as an ac-coupled comparator. Figure 30. TLV3201 Configured as an AC-Coupled Comparator 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 TLV3201 TLV3202 www.ti.com SBOS561A – MARCH 2012 – REVISED JUNE 2012 Figure 31 shows a single-supply current monitor configured as a difference amplifier with a gain of 50. The OPA320 was chosen for this circuit because of its gain bandwidth (20 MHz), which allows higher speed triggering and monitoring of the current across the shunt resistor followed by the fast response of the TLV3201. Figure 31. TLV3201 and OPA320 Configured as a Fast-Response Output Current Monitor Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 15 TLV3201 TLV3202 SBOS561A – MARCH 2012 – REVISED JUNE 2012 www.ti.com Figure 32 shows the TMP20 and TLV3201 designed as a high-speed temperature switch. The TMP20 is an analog output temperature sensor where output voltage decreases with temperature. The comparator output is tripped when the output reaches a critical trip threshold. Figure 32. TLV3201 and TMP20 Configured as a Precision Analog Temperature Switch 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 TLV3201 TLV3202 www.ti.com SBOS561A – MARCH 2012 – REVISED JUNE 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (March 2012) to Revision A Page • Changed product status from Production Data to Mixed Status .......................................................................................... 1 • Added dual channel device ................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV3201 TLV3202 17 PACKAGE OPTION ADDENDUM www.ti.com 2-Jul-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TLV3201AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV3201AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV3201AIDCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV3201AIDCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV3202AID PREVIEW SOIC D 8 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV3202AIDGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV3202AIDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV3202AIDR PREVIEW SOIC D 8 2500 Green (RoHS & no Sb/Br) Samples (Requires Login) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 2-Jul-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV3201AIDBVR Package Package Pins Type Drawing SPQ SOT-23 3000 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 9.0 Pack Materials-Page 1 3.23 B0 (mm) K0 (mm) P1 (mm) 3.17 1.37 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV3201AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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