TI CC2541

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TI德州仪器无线链接产品数据手册
CC2541
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最终解释权。
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信驰达简介
信驰达科技（RF-star）是一家集合方案设计功能和核心器件供应的专业本地电子元器件分销商，专注低功
耗射频 LPRF 和低功耗 MCU 领域，公司成立于 2010年，作为中国区唯一具有美国 TI 公司授予的 LPRF
Product Reseller 和 Third Party 双重资质的公司，一直引领着 LPRF 技术在国内的推广和应用，是国内唯一
一家可提供 LPRF 软硬件产品、技术支持、解决方案和核心元器件供应一条龙服务的专业化公司；
公司在美国新泽西州、中国深圳、上海、北京、天津、无锡、长沙、成都、重庆设有研发中心和办事处，
拥有资深的技术研发团队和销售团队以及 SMT 生产工厂。
无线射频器件用于低于1GHz 和2.4GHz 频段、ANT、蓝牙(Bluetooth)、低功耗蓝牙、射频识别（RFID）、
PurePath 无线音频、ZigBee、IEEE802.15.4、Zigbee RF4CE、6LoWPAN、Wi-Fi 的射频集成电路( RF IC )
和专有协议。
产品市场应用：ZigBee 无线传感网络，各种数据采集及遥测监控 (含数据, 语音,图像等),可应用于安防、
医疗、能源、水力、电力、交通监控、防盗，无线自动抄表；仪器仪表远程数据遥测、工业无线遥控；消防安
全自动报警、煤矿安全监控及人员定位；汽车防盗、胎压检测，四轮定位；无线键盘、鼠标、打印机、游戏
杆、遥控玩具、机器人等广泛的领域。适用于合乎全世界免费频段 315MHz、433 MHz、470MHz、868
MHz、915 MHz、2.4GHz，符合 FCC、CE、SGS、RoHs 认证规范,产品和信誉受到国内外顾客的一致好
评。
RF-star 将一如既往，为客户提供更多、更好的产品，更具优势的技术服务，良好的商务服务，和更完善
的物流服务。RF-star 将跨上一个新的平台，获得更大的发展空间。 RF-star 将继续本着“务实、诚信、学习、
创新”的专业精神，团结一致、奋勇开拓、锐意进取，为成为全球 无线射频技术绝对第一之产品、服务及解决
方案提供者，把科技与客户联系在一起，为供应链注入动力，并提供卓越的投资回报而不懈努力。
如果您在产品开发过程中发现技术难题以及高频困扰，竭诚欢迎来电洽询。我们将为您提供技术支持和解
决方案，让您能更快把产品推向市场。
我们深信射频技术将会得到迅速的发展与普及，我们愿意分享多年来在射频行业积累的经验与教训，为无
线的明天做出贡献。专业源于专注，科技铸就未来。
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CC2541
2.4GHz蓝牙 ™低
低能耗和私有片载系统
特性
1
•
23
•
•
•
射频
– 2.4GHz蓝牙符合低能耗规范和私有的 RF 片载
系统
– 支持 250kbps，
，500kbps，
，1Mbps，
，2Mbps 的
数据速率
– 出色的链路预算，不使用外部前段而支持长距离
应用
– 高达 0dBm 的可编程输出功率
– 出色的接收器灵敏度（1Mbps 时为 94dBm）
），可选择性，和阻挡性能
– 适合于针对符合世界范围内的无线电频率调节系
统：ETSI EN 300 328 和 EN 300 440 2 类
（欧洲），FCC CFR47 15 部分（美国），和
ARIB STD-T66（
（日本）
布局
– 极少的外部组件
– 提供参考设计
– 6mm × 6mm 方形扁平无引脚 (QFN)-40 封装
– 与 CC2540 引脚兼容 （当不使用 USB 或者 I2C
时）
低功率
– 工作模式 RX 低至：17.9mA
– 工作模式 TX (0 dBm)：
：18.2mA
– 功率模式 1（
（4µs 唤醒）：270µs
– 功率模式 2（
（睡眠定时器打开）：1µs
– 功率模式 3（
（外部中断）：0.5µs
– 宽泛的电源电压范围 (2V - 3.6V)
工作模式下TPS62730兼
兼容低功率
– RX 低至：14.7mA（
（3V 电源）
– TX (0 dBm)：
：14.3 mA（
（3V 电源）
空格
空格
空格
空格
空格
•
•
•
空格
微控制器
– 具有代码预取功能的高性能和低功率 8051 微控
制器内核
– 系统内可编程闪存，128 或者 256 KB
– 在所有功率模式下具有保持功能的 8KB RAM
– 支持硬件调试
– 扩展基带自动化，包括自动确认和地址解码
– 所有功率模式中对所有相关寄存器的保持
外设
– 功能强大的 5 通道直接内存访问 (DMA)
– 通用定时器（1 个 16 位，2 个 8 位）
– 红外 (IR) 生成电路
– 具有捕捉功能的 32kHz 睡眠定时器
– 精确数字接收到的数字信号强度指示器 (RSSI)
支持
– 电池监视器和温度感应器
– 含 8 通道和可配置分辨率的 12 位模数转换器
(ADC)
– 高级加密标准 (AES) 安全协处理器
– 2 个功能强大的支持几个串行协议的通用异步接
收发器 (UART)
– 23 个通用 I/O 引脚
(21 × 4mA，
，2 × 20mA)
– I2C 接口
– 2 个具有 LED 驱动功能的 I/O 引脚
– 安全装置定时器
– 集成的高性能比较器
开发工具
– CC2541 评估模块工具包 (CC2541EMK)
– CC2541 小型开发工具包 (CC2541DK-MINI)
– SmartRF™ 软件
– 提供 IAR 嵌入式 Workbench™
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ZigBee is a registered trademark of ZigBee Alliance.
is a trademark of ~Bluetooth SIG, Inc..
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CC2541
软件特性
•
符合针对单模式蓝牙低能耗 (BLE) 解决方案的符合
蓝牙4.0 协议的堆栈
– 完全功率优化堆栈，包括控制器和主机
– GAP - 中心设备，外设，或者广播器（包括
组合角色）
– 属性协议 (ATT) / 通用属性配置文件
(GATT) – 客户端和服务器
– 对称式对多重处理 (SMP) - AES-128 加密和
解密
– L2CAP
– 示例应用和配置文件
– 针对 GAP 中心和外围作用的一般应用
– 距离临近，加速计，简单关键字，和电池
GATT 服务
– BLE 软件栈内支持更多应用
– 多重配置选项
– 单芯片配置，允许应用运行在 CC2541 上
– 用于运行在一个外部微处理器上的网络处理
器接口
– BTool - 用于评估、开发和测试的视窗
(Windows) PC 应用
应用范围
•
•
•
•
•
•
2.4GHz蓝牙低能耗系统
私有的 2.4 GHz 系统
人机接口器件（键盘，鼠标，遥控）
体育和休闲设备
移动电话附件
消费类电子产品
含有TPS62730的
的 CC2541
•
•
•
•
•
•
•
TPS62730是
是一款具有旁通模式的 2MHz 降压转换
器
延长电池寿命高达 20%
在所有工作模式下减少的电流
30nA 旁通模式电流以支持低功率模式
RF 性能并未改变
小型封装允许小型解决方案尺寸
CC2541 可控
说明
CC2541 是一款针对蓝牙低能耗以及私有 2.4GHz 应用
的功率优化的真正片载系统 (SoC) 解决方案。 它使得
使用低总体物料清单成本建立强健网络节点成为可能。
CC2541 将领先 RF 收发器的出色性能和一个业界标准
的增强型 8051 MCU、系统内可编程闪存存储器、8kB
RAM 和很多其它功能强大的特性和外设组合在一起。
CC2541 非常适合应用于需要超低能耗的系统。 这由
多种不同的运行模式指定。 运行模式间较短的转换时
间进一步使低能耗变为可能。
如果 CC2540 上的 USB 未启用并且 CC2541 上的
I2C/ 额外 I/O 未启用，那么 CC2541 与 CC2540 在
6mm x 6mm 方形扁平无引脚 (QFN) 40 封装内引脚兼
容。 与 CC2540 相比，CC2541 提供更低 RF 流耗。
CC2541 没有 CC2540 所具有的 USB 接口，并在 TX
模式中提供较低的最大输出功率。 CC2541 还增加了
1 个 HW I2C 接口。
CC2541 与 CC2533 优化 RF4CE IEEE 802.15.4 SoC
引脚兼容。
CC2541 有 2 个不同的版本：分别具有 128kB 和
256kB 闪存的的 CC2541F128/F256。
CC2541 的方框图请参见Figure 1。
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CC2541
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
RESET
XOSC_Q2
WATCHDOG TIMER
XOSC_Q1
CLOCK MUX and
CALIBRATION
32.768-kHz
CRYSTAL OSC
P2_4
P2_3
P2_2
DEBUG
INTERFACE
P2_1
DCOUPL
POWER-ON RESET
BROWN OUT
32-MHZ
CRYSTAL OSC
HIGH SPEED
RC-OSC
SFR bus
RESET_N
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
SLEEP TIMER
POWER MGT. CONTROLLER
32-kHz
RC-OSC
P2_0
PDATA
P1_7
P1_6
P1_5
RAM
SRAM
FLASH
FLASH
XRAM
8051 CPU
CORE
IRAM
P1_4
SFR
MEMORY
ARBITRATOR
P1_3
P1_2
UNIFIED
DMA
P1_1
P1_0
IRQ
CTRL
ANALOG COMPARATOR
P0_4
P0_3
P0_2
P0_1
P0_0
FIFOCTRL
OP-
DS ADC
AUDIO / DC
Radio Arbiter
P0_5
I/O CONTROLLER
P0_6
AES
ENCRYPTION
and
DECRYPTION
Link Layer Engine
2
I C
SCL
SFR bus
DEMODULATOR
SDA
1-KB SRAM
RADIO
REGISTERS
SYNTH
P0_7
FLASH CTRL
MODULATOR
USART 1
RECEIVE
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
FREQUENCY
SYNTHESIZER
USART 0
TRANSMIT
TIMER 3 (8-bit)
TIMER 4 (8-bit)
RF_P RF_N
DIGITAL
ANALOG
MIXED
Figure 1. Block Diagram
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CC2541
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage
MIN
MAX
UNIT
–0.3
3.9
V
–0.3
VDD + 0.3 ≤ 3.9
V
10
dBm
125
°C
All pins, excluding pins 25 and 26, according to human-body
model, JEDEC STD 22, method A114
2
kV
All pins, according to human-body model, JEDEC STD 22,
method A114
1
kV
500
V
All supply pins must have the same voltage
Voltage on any digital pin
Input RF level
Storage temperature range
ESD (2)
–40
According to charged-device model, JEDEC STD 22, method
C101
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
CAUTION: ESD sesnsitive device. Precautions should be used when handling the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Operating ambient temperature range, TA
NOM
MAX
UNIT
–40
85
°C
2
3.6
V
Operating supply voltage
ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V,
1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, and 0.1% BER
PARAMETER
Icore
Iperi
Core current consumption
Peripheral current consumption
(Adds to core current Icore for each
peripheral unit activated)
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TEST CONDITIONS
MIN
TYP MAX UNIT
RX mode, standard mode, no peripherals active, low MCU
activity
17.9
RX mode, high-gain mode, no peripherals active, low MCU
activity
20.2
TX mode, –20 dBm output power, no peripherals active, low
MCU activity
16.8
TX mode, 0 dBm output power, no peripherals active, low
MCU activity
18.2
Power mode 1. Digital regulator on; 16-MHz RCOSC and 32MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD and
sleep timer active; RAM and register retention
270
Power mode 2. Digital regulator off; 16-MHz RCOSC and 32MHz crystal oscillator off; 32.768-kHz XOSC, POR, and sleep
timer active; RAM and register retention
1
mA
Power mode 3. Digital regulator off; no clocks; POR active;
RAM and register retention
0.5
Low MCU activity: 32-MHz XOSC running. No radio or
peripherals. Limited flash access, no RAM access.
6.7
Timer 1. Timer running, 32-MHz XOSC used
90
Timer 2. Timer running, 32-MHz XOSC used
90
Timer 3. Timer running, 32-MHz XOSC used
60
Timer 4. Timer running, 32-MHz XOSC used
70
Sleep timer, including 32.753-kHz RCOSC
0.6
ADC, when converting
1.2
µA
mA
μA
mA
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CC2541
GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKE-UP AND TIMING
Power mode 1 → Active
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of 16-MHz RCOSC
4
μs
Power mode 2 or 3 → Active
Digital regulator off, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of regulator and 16-MHz RCOSC
120
μs
Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC,
with 32-MHz XOSC OFF
500
μs
μs
Active → TX or RX
RX/TX turnaround
With 32-MHz XOSC initially on
180
Proprietary auto mode
130
BLE mode
150
μs
RADIO PART
RF frequency range
Programmable in 1-MHz steps
Data rate and modulation format
2 Mbps, GFSK, 500-kHz deviation
2 Mbps, GFSK, 320-kHz deviation
1 Mbps, GFSK, 250-kHz deviation
1 Mbps, GFSK, 160-kHz deviation
500 kbps, MSK
250 kbps, GFSK, 160-kHz deviation
250 kbps, MSK
2379
2496
MHz
RF RECEIVE SECTION
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Receiver sensitivity
Saturation
Co-channel rejection
In-band blocking rejection
Frequency error tolerance
(1)
Symbol rate error
tolerance (2)
–90
dBm
BER < 0.1%
–1
dBm
dB
Wanted signal at –67 dBm
–9
±2 MHz offset, 0.1% BER, wanted signal –67 dBm
–2
±4 MHz offset, 0.1% BER, wanted signal –67 dBm
36
±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm
41
dB
Including both initial tolerance and drift. Sensitivity better than –67dBm,
250 byte payload. BER 0.1%
–300
300
kHz
Maximum packet length. Sensitivity better than–67dBm, 250 byte
payload. BER 0.1%
–120
120
ppm
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER
Receiver sensitivity
Saturation
BER < 0.1%
Co-channel rejection
Wanted signal at –67 dBm
±2 MHz offset, 0.1% BER, wanted signal –67 dBm
In-band blocking rejection
–86
dBm
–7
dBm
–12
dB
–1
±4 MHz offset, 0.1% BER, wanted signal –67 dBm
34
±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm
39
dB
Frequency error tolerance (1)
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250 byte payload. BER 0.1%
–300
300
kHz
Symbol rate error
tolerance (2)
Maximum packet length. Sensitivity better than –67 dBm, 250 byte
payload. BER 0.1%
–120
120
ppm
(1)
(2)
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
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CC2541
RF RECEIVE SECTION (continued)
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
1 Mbps, GFSK, 250-kHz Deviation, Bluetooth low energy Mode, 0.1% BER
Receiver sensitivity (3) (4)
High-gain mode
–94
Standard mode
–88
dBm
Saturation (4)
BER < 0.1%
5
dBm
Co-channel rejection (4)
Wanted signal –67 dBm
–6
dB
±1 MHz offset, 0.1% BER, wanted signal –67 dBm
–2
±2 MHz offset, 0.1% BER, wanted signal –67 dBm
26
±3 MHz offset, 0.1% BER, wanted signal –67 dBm
34
In-band blocking rejection (4)
>6 MHz offset, 0.1% BER, wanted signal –67 dBm
Out-of-band blocking
rejection (4)
33
Minimum interferer level < 2 GHz (Wanted signal –67 dBm)
–21
Minimum interferer level [2 GHz, 3 GHz] (Wanted signal –67 dBm)
–25
Minimum interferer level > 3 GHz (Wanted signal –67 dBm)
Intermodulation (4)
Frequency error tolerance
Symbol rate error
tolerance (6)
Including both initial tolerance and drift. Sensitivity better than -67dBm,
250 byte payload. BER 0.1%
Maximum packet length. Sensitivity better than –67 dBm, 250 byte
payload. BER 0.1%
dBm
–7
Minimum interferer level
(5)
dB
–36
dBm
–250
250
kHz
–80
80
ppm
1 Mbps, GFSK, 160-kHz Deviation, 0.1% BER
Receiver sensitivity (7)
Saturation
BER < 0.1%
Co-channel rejection
Wanted signal 10 dB above sensitivity level
In-band blocking rejection
–91
dBm
0
dBm
–9
dB
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
2
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
24
±3-MHz offset, 0.1% BER, wanted signal -–67 dBm
27
>6-MHz offset, 0.1% BER, wanted signal –67 dBm
32
Frequency error tolerance (5)
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
Symbol rate error
tolerance (6)
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
dB
–200
200
kHz
–80
80
ppm
500 kbps, MSK, 0.1% BER
Receiver sensitivity (7)
Saturation
Co-channel rejection
In-band blocking rejection
–99
dBm
0
dBm
Wanted signal –67 dBm
–5
dB
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
20
BER < 0.1%
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
27
>2-MHz offset, 0.1% BER, wanted signal –67 dBm
28
Frequency error tolerance
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
Symbol rate error tolerance
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
(3)
(4)
(5)
(6)
(7)
dB
–150
150
kHz
–80
80
ppm
The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standard
mode.
Results based on standard-gain mode.
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
Results based on high-gain mode.
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CC2541
RF RECEIVE SECTION (continued)
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
–98
dBm
250 kbps, GFSK, 160 kHz Deviation, 0.1% BER
Receiver sensitivity
(8)
Saturation
BER < 0.1%
0
dBm
Co-channel rejection
Wanted signal -67 dBm
–3
dB
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
23
In-band blocking rejection
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
28
>2-MHz offset, 0.1% BER, wanted signal –67 dBm
29
Frequency error tolerance (9)
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
Symbol rate error
tolerance (10)
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
dB
–150
150
kHz
–80
80
ppm
250 kbps, MSK, 0.1% BER
Receiver sensitivity
(11)
–99
dBm
0
dBm
Wanted signal -67 dBm
–5
dB
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
20
Saturation
BER < 0.1%
Co-channel rejection
In-band blocking rejection
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
29
>2-MHz offset, 0.1% BER, wanted signal –67 dBm
30
Frequency error tolerance
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
Symbol rate error tolerance
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
dB
–150
150
kHz
–80
80
ppm
ALL RATES/FORMATS
Spurious emission in RX.
Conducted measurement
f < 1 GHz
–67
dBm
Spurious emission in RX.
Conducted measurement
f > 1 GHz
–57
dBm
(8)
(9)
(10)
(11)
Results based on standard-gain mode.
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
Results based on high-gain mode.
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CC2541
RF TRANSMIT SECTION
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
PARAMETER
TEST CONDITIONS
Output power
Programmable output power
range
MIN
TYP
Delivered to a single-ended 50-Ω load through a balun using
maximum recommended output power setting
0
Delivered to a single-ended 50-Ω load through a balun using
minimum recommended output power setting
–20
MAX
UNIT
dBm
Delivered to a single-ended 50-Ω load through a balun using
minimum recommended output power setting
f < 1 GHz
20
dB
–52
dBm
Spurious emission conducted f > 1 GHz
–48
dBm
measurement
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
Differential impedance as seen from the RF port (RF_P and RF_N)
toward the antenna
Optimum load impedance
Ω
70 +j30
Designs with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LC
resonator in front of the antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connect
both from the signal trace to a good RF ground.
CURRENT CONSUMPTION WITH TPS62730
Measured on Texas Instruments CC2541 TPA62730 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz,
1 Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy Mode, 1% BER (1)
PARAMETER
Current consumption
TEST CONDITIONS
MIN
TYP
RX mode, standard mode, no peripherals active, low MCU activity, MCU
at 1 MHz
14.7
RX mode, high-gain mode, no peripherals active, low MCU activity, MCU
at 1 MHz
16.7
TX mode, –20 dBm output power, no peripherals active, low MCU activity,
MCU at 1 MHz
UNIT
mA
13.1
TX mode, 0 dBm output power, no peripherals active, low MCU activity,
MCU at 1 MHz
(1)
MAX
14.3
0.1% BER maps to 30.8% PER
32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
MAX
32
Crystal frequency accuracy
requirement (1)
ESR
TYP
Equivalent series resistance
UNIT
MHz
–40
40
ppm
6
60
Ω
C0
Crystal shunt capacitance
1
7
pF
CL
Crystal load capacitance
10
16
pF
Start-up time
Power-down guard time
(1)
0.25
The crystal oscillator must be in power down for a guard
time before it is used again. This requirement is valid for
all modes of operation. The need for power-down guard
time can vary with crystal type and load.
3
ms
ms
Including aging and temperature dependency, as specified by [1]
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CC2541
32.768-kHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
TYP
MAX
UNIT
40
ppm
130
kΩ
32.768
Crystal frequency accuracy requirement (1)
–40
kHz
ESR
Equivalent series resistance
40
C0
Crystal shunt capacitance
0.9
2
pF
CL
Crystal load capacitance
12
16
pF
Start-up time
0.4
(1)
s
Including aging and temperature dependency, as specified by [1]
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
Calibrated frequency (1)
32.753
Frequency accuracy after calibration
±0.2%
Temperature coefficient (2)
(1)
(2)
(3)
(4)
UNIT
kHz
0.4
%/°C
3
%/V
2
ms
Supply-voltage coefficient (3)
Calibration time
MAX
(4)
The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.
Frequency drift when temperature changes after calibration
Frequency drift when supply voltage changes after calibration
When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is set to 0.
16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
Frequency
(1)
TEST CONDITIONS
MIN
TYP
16
Uncalibrated frequency accuracy
±18%
Calibrated frequency accuracy
±0.6%
MAX
UNIT
MHz
Start-up time
10
μs
Initial calibration time (2)
50
μs
(1)
(2)
The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.
When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC_PD is set to 0.
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CC2541
RSSI CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Useful RSSI range (1)
RSSI offset (1)
Reduced gain by AGC algorithm
64
High gain by AGC algorithm
64
Reduced gain by AGC algorithm
79
High gain by AGC algorithm
99
Absolute uncalibrated accuracy (1)
dB
dBm
±6
dB
1
dB
Step size (LSB value)
All Other Rates/Formats
Useful RSSI range (1)
RSSI offset (1)
Standard mode
64
High-gain mode
64
Standard mode
98
High-gain mode
107
Absolute uncalibrated accuracy (1)
dBm
±3
dB
1
dB
Step size (LSB value)
(1)
dB
Assuming CC2541 EM reference design. Other RF designs give an offset from the reported value.
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
At ±1-MHz offset from carrier
Phase noise, unmodulated carrier
TYP
MAX
UNIT
–109
At ±3-MHz offset from carrier
–112
At ±5-MHz offset from carrier
–119
dBc/Hz
ANALOG TEMPERATURE SENSOR
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
Output
MIN
TYP
Initial accuracy without calibration
UNIT
12-bit
4.5
mv/°C
1
0.1 V
Temperature coefficient
Voltage coefficient
MAX
1480
Measured using integrated ADC, internal band-gap voltage
reference, and maximum resolution
±10
°C
Accuracy using 1-point calibration
±5
°C
Current consumption when enabled
0.5
mA
COMPARATOR CHARACTERISTICS
TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2541 reference designs, post-calibration.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
Common-mode maximum voltage
VDD
Common-mode minimum voltage
–0.3
Input offset voltage
Offset vs temperature
Offset vs operating voltage
UNIT
V
1
mV
16
µV/°C
4
mV/V
Supply current
230
nA
Hysteresis
0.15
mV
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CC2541
CHARACTERISTICS
ADC
TA = 25°C and VDD = 3 V
PARAMETER
0
VDD
V
VDD
V
Effective number of bits
Total harmonic distortion
Simulated using 4-MHz clock speed
197
kΩ
Peak-to-peak, defines 0 dBFS
2.97
V
Single-ended input, 7-bit setting
5.7
Single-ended input, 9-bit setting
7.5
Single-ended input, 10-bit setting
9.3
Single-ended input, 12-bit setting
10.3
Differential input, 7-bit setting
6.5
Differential input, 9-bit setting
8.3
Differential input, 10-bit setting
10
Differential input, 12-bit setting
11.5
12-bit setting, clocked by RCOSC
10.9
0–20
Single ended input, 12-bit setting, –6 dBFS (1)
–75.2
Differential input, 12-bit setting, –6 dBFS (1)
–86.6
kHz
dB
70.2
Differential input, 12-bit setting (1)
79.3
Single-ended input, 12-bit setting, –6 dBFS (1)
78.8
Differential input, 12-bit setting, –6 dBFS (1)
88.9
Common-mode rejection ratio
Differential input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
>84
dB
Crosstalk
Single ended input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
>84
dB
Offset
Midscale
–3
mV
Differential nonlinearity
Integral nonlinearity
12-bit setting, mean (1)
0.05
(1)
0.9
12-bit setting, maximum (1)
13.3
12-bit setting, maximum
12-bit setting, mean, clocked by RCOSC
12-bit setting, max, clocked by RCOSC
Signal-to-noise-and-distortion
LSB
4.6
10
LSB
29
Single ended input, 7-bit setting (1)
35.4
Single ended input, 9-bit setting (1)
46.8
Single ended input, 10-bit setting (1)
57.5
Single ended input, 12-bit setting (1)
66.6
Differential input, 7-bit setting (1)
40.7
Differential input, 9-bit setting (1)
51.6
Differential input, 10-bit setting (1)
61.8
Differential input, 12-bit setting (1)
70.8
7-bit setting
Conversion time
dB
0.68%
12-bit setting, mean (1)
(1)
9.7
7-bit setting, both single and differential
Gain error
SINAD
(–THD+N)
bits
Single-ended input, 12-bit setting (1)
Signal to nonharmonic ratio
INL
V
0
Useful power bandwidth
DNL
UNIT
VDD
VDD is voltage on AVDD5 pin
(1)
0
MAX
External reference voltage
10-bit setting, clocked by RCOSC
CMRR
TYP
External reference voltage differential VDD is voltage on AVDD5 pin
Full-scale signal
THD
MIN
VDD is voltage on AVDD5 pin
Input resistance, signal
ENOB (1)
TEST CONDITIONS
Input voltage
dB
20
9-bit setting
36
10-bit setting
68
12-bit setting
132
μs
Measured with 300-Hz sine-wave input and VDD as reference.
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CC2541
ADC CHARACTERISTICS (continued)
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
Power consumption
MAX
UNIT
1.2
Internal reference VDD coefficient
mA
4
Internal reference temperature
coefficient
Internal reference voltage
mV/V
0.4
mV/10°C
1.15
V
CONTROL INPUT AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32
MHz
System clock, fSYSCLK
tSYSCLK = 1/ fSYSCLK
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
16
RESET_N low duration
See item 1, Figure 2. This is the shortest pulse that is recognized as
a complete reset pin request. Note that shorter pulses may be
recognized but do not lead to complete reset of all modules within the
chip.
1
µs
Interrupt pulse duration
See item 2, Figure 2.This is the shortest pulse that is recognized as
an interrupt request.
20
ns
RESET_N
1
2
Px.n
T0299-01
Figure 2. Control Input AC Characteristics
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CC2541
SPI AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
t1
TEST CONDITIONS
SCK period
SCK duty cycle
MIN
Master, RX and TX
250
Slave, RX and TX
250
Master
TYP MAX
UNIT
ns
50%
Master
63
Slave
63
t2
SSN low to SCK
t3
SCK to SSN high
t4
MOSI early out
Master, load = 10 pF
t5
MOSI late out
Master, load = 10 pF
t6
MISO setup
Master
90
ns
t7
MISO hold
Master
10
ns
Master
63
Slave
63
ns
ns
7
ns
10
ns
SCK duty cycle
Slave
t10
MOSI setup
Slave
35
ns
t11
MOSI hold
Slave
10
ns
t9
MISO late out
Slave, load = 10 pF
Operating frequency
50%
ns
95
Master, TX only
8
Master, RX and TX
4
Slave, RX only
8
Slave, RX and TX
4
ns
MHz
SCK
t2
t3
SSN
t4
D0
MOSI
t6
MISO
X
t5
X
D1
t7
D0
X
T0478-01
Figure 3. SPI Master AC Characteristics
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CC2541
SCK
t2
t3
SSN
t8
D0
MISO
X
t10
MOSI
X
t9
D1
t11
D0
X
T0479-01
Figure 4. SPI Slave AC Characteristics
DEBUG INTERFACE AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
MHz
fclk_dbg
Debug clock frequency (see Figure 5)
t1
Allowed high pulse on clock (see Figure 5)
35
ns
t2
Allowed low pulse on clock (see Figure 5)
35
ns
t3
EXT_RESET_N low to first falling edge on debug clock (see
Figure 7)
167
ns
t4
Falling edge on clock to EXT_RESET_N high (see Figure 7)
83
ns
t5
EXT_RESET_N high to first debug command (see Figure 7)
83
ns
t6
Debug data setup (see Figure 6)
2
ns
t7
Debug data hold (see Figure 6)
4
ns
t8
Clock-to-data delay (see Figure 6)
Load = 10 pF
30
ns
Time
DEBUG_ CLK
P2_2
t1
t2
1/fclk_dbg
T0436-01
Figure 5. Debug Clock – Basic Timing
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CC2541
Time
DEBUG_ CLK
P2_2
RESET_N
t3
t4
t5
T0437-01
Figure 6. Debug Enable Timing
Time
DEBUG_ CLK
P2_2
DEBUG_DATA
(to CC2541)
P2_1
DEBUG_DATA
(from CC2541)
P2_1
t6
t8
t7
Figure 7. Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
Input capture pulse duration
TEST CONDITIONS
Synchronizers determine the shortest input pulse that can be
recognized. The synchronizers operate at the current system
clock rate (16 MHz or 32 MHz).
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MIN
1.5
TYP
MAX
UNIT
tSYSCLK
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CC2541
DC CHARACTERISTICS
TA = 25°C, VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Logic-0 input voltage
Logic-1 input voltage
UNIT
0.5
V
2.4
V
Logic-0 input current
Input equals 0 V
–50
50
nA
Logic-1 input current
Input equals VDD
–50
50
nA
I/O-pin pullup and pulldown resistors
20
Logic-0 output voltage, 4- mA pins
Output load 4 mA
Logic-1 output voltage, 4-mA pins
Output load 4 mA
Logic-0 output voltage, 20- mA pins
Output load 20 mA
Logic-1 output voltage, 20-mA pins
Output load 20 mA
kΩ
0.5
2.5
V
0.5
2.5
V
V
V
DEVICE INFORMATION
PIN DESCRIPTIONS
The CC2541 pinout is shown in Figure 8 and a short description of the pins follows.
DVDD1
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3 / OSC32K_Q2
P2_4 / OSC32K_Q1
40
39
38
37
36
35
34
33
32
AVDD6
DCOUPL
CC2541
RHA Package
(Top View)
GND
1
31
30
R_BIAS
SCL
2
29
AVDD4
SDA
3
28
AVDD1
NC
4
27
AVDD2
P1_5
5
26
RF_N
P1_4
6
25
RF_P
P1_3
7
24
AVDD3
P1_2
8
23
XOSC_Q2
P1_1
9
22
14
15
16
17
18
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
19
P0_0
13
21
20
XOSC_Q1
AVDD5
RESET_N
12
P0_7
10
11
P1_0
DVDD2
GND
Ground Pad
NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.
Figure 8. Pinout Top View
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CC2541
PIN DESCRIPTIONS
PIN NAME
AVDD1
PIN
28
PIN TYPE
Power (analog)
DESCRIPTION
2-V–3.6-V analog power-supply connection
AVDD2
27
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD3
24
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD4
29
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD5
21
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD6
31
Power (analog)
2-V–3.6-V analog power-supply connection
DCOUPL
40
Power (digital)
1.8-V digital power-supply decoupling. Do not use for supplying external circuits.
DVDD1
39
Power (digital)
2-V–3.6-V digital power-supply connection
DVDD2
10
Power (digital)
2-V–3.6-V digital power-supply connection
GND
1
Ground pin
Connect to GND
GND
—
Ground
The ground pad must be connected to a solid ground plane.
NC
4
Unused pins
Not connected
P0_0
19
Digital I/O
Port 0.0
P0_1
18
Digital I/O
Port 0.1
P0_2
17
Digital I/O
Port 0.2
P0_3
16
Digital I/O
Port 0.3
P0_4
15
Digital I/O
Port 0.4
P0_5
14
Digital I/O
Port 0.5
P0_6
13
Digital I/O
Port 0.6
P0_7
12
Digital I/O
Port 0.7
P1_0
11
Digital I/O
Port 1.0 – 20-mA drive capability
P1_1
9
Digital I/O
Port 1.1 – 20-mA drive capability
P1_2
8
Digital I/O
Port 1.2
P1_3
7
Digital I/O
Port 1.3
P1_4
6
Digital I/O
Port 1.4
P1_5
5
Digital I/O
Port 1.5
P1_6
38
Digital I/O
Port 1.6
P1_7
37
Digital I/O
Port 1.7
P2_0
36
Digital I/O
Port 2.0
P2_1/DD
35
Digital I/O
Port 2.1 / debug data
P2_2/DC
34
Digital I/O
Port 2.2 / debug clock
P2_3/
OSC32K_Q2
33
Digital I/O, Analog I/O
Port 2.3/32.768 kHz XOSC
P2_4/
OSC32K_Q1
32
Digital I/O, Analog I/O
Port 2.4/32.768 kHz XOSC
RBIAS
30
Analog I/O
External precision bias resistor for reference current
RESET_N
20
Digital input
Reset, active-low
RF_N
26
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P
25
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
SCL
2
I2C clock or digital I/O
Can be used as I2C clock pin or digital I/O. Leave floating if not used. If grounded
disable pull up
SDA
3
I2C clock or digital I/O
Can be used as I2C data pin or digital I/O. Leave floating if not used. If grounded
disable pull up
XOSC_Q1
22
Analog O
32-MHz crystal oscillator pin 1
XOSC_Q2
23
Analog O
32-MHz crystal oscillator pin 2
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CC2541
BLOCK DIAGRAM
A block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given.
RESET
XOSC_Q2
WATCHDOG TIMER
XOSC_Q1
CLOCK MUX and
CALIBRATION
32.768-kHz
CRYSTAL OSC
P2_4
P2_3
P2_2
DEBUG
INTERFACE
P2_1
DCOUPL
POWER-ON RESET
BROWN OUT
32-MHZ
CRYSTAL OSC
HIGH SPEED
RC-OSC
SFR bus
RESET_N
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
SLEEP TIMER
POWER MGT. CONTROLLER
32-kHz
RC-OSC
P2_0
PDATA
P1_7
P1_5
RAM
SRAM
FLASH
FLASH
XRAM
8051 CPU
CORE
P1_6
IRAM
P1_4
SFR
MEMORY
ARBITRATOR
P1_3
P1_2
UNIFIED
DMA
P1_1
P1_0
IRQ
CTRL
ANALOG COMPARATOR
P0_4
P0_3
P0_2
P0_1
P0_0
FIFOCTRL
OP-
DS ADC
AUDIO / DC
Radio Arbiter
P0_5
I/O CONTROLLER
P0_6
AES
ENCRYPTION
and
DECRYPTION
Link Layer Engine
2
I C
SCL
SFR bus
DEMODULATOR
SDA
1-KB SRAM
RADIO
REGISTERS
SYNTH
P0_7
FLASH CTRL
MODULATOR
USART 1
RECEIVE
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
FREQUENCY
SYNTHESIZER
USART 0
TRANSMIT
TIMER 3 (8-bit)
TIMER 4 (8-bit)
RF_P RF_N
DIGITAL
ANALOG
MIXED
Figure 9. CC2541 Block Diagram
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CC2541
BLOCK DESCRIPTIONS
A block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given.
CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access
of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is
responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The SFR bus is drawn conceptually in Figure 9 as a common bus that connects all hardware peripherals to the
memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio
register bank, even though these are indeed mapped into XDATA memory space.
The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The SRAM is
an ultralow-power SRAM that retains its contents even when the digital part is powered off (power mode 2 and
mode 3).
The 128/256 KB flash block provides in-circuit programmable non-volatile program memory for the device, and
maps into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise
programming. See User Guide for details on the flash controller.
A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be
located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers,
ADC interface, etc.) can be used with the DMA controller for efficient operation by performing data transfers
between a single SFR or XREG address and flash/SRAM.
Each CC2541 contains a unique 48-bit IEEE address that can be used as the public device address for a
Bluetooth device. Designers are free to use this address, or provide their own, as described in the Bluetooth
specfication.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced even if the
device is in a sleep mode (power modes 1 and 2) by bringing the CC2541 back to the active mode.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to erase or program the entire flash memory, control which oscillators
are enabled, stop and start execution of the user program, execute instructions on the 8051 core, set code
breakpoints, and single-step through instructions in the code. Using these techniques, it is possible to perform incircuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects
to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.
The sleep timer is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or an
internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except power mode
3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power mode 1
or mode 2.
A built-in watchdog timer allows the CC2541 to reset itself if the firmware hangs. When enabled by software,
the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.
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Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the
output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
Timer 2 is a 40-bit timer. It has a 16-bit counter with a configurable timer period and a 24-bit overflow counter
that can be used to keep track of the number of periods that have transpired. A 40-bit capture register is also
used to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which
transmission ends. There are two 16-bit output compare registers and two 24-bit overflow compare registers that
can be used to give exact timing for start of RX or TX to the radio or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 and USART 1 are each configurable as either an SPI master/slave or a UART. They provide double
buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex
applications. Each USART has its own high-precision baud-rate generator, thus leaving the ordinary timers free
for other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly instead
of using some oversampling scheme, and are thus well-suited for high data rates.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-kHz,
respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. The
inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a singleended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC can
automate the process of periodic sampling or conversion over a sequence of channels.
The I2C module provides a digital peripheral connection with two pins and supports both master and slave
operation. I2C support is compliant with the NXP I2C specification version 2.1 and supports standard mode (up to
100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit device addressing modes are supported, as well as
master and slave modes.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin
interrupt.
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CC2541
TYPICAL CHARACTERISTICS
RX CURRENT
vs
TEMPERATURE
TX CURRENT
vs
TEMPERATURE
19
19.5
19
Current (mA)
18.5
Current (mA)
TX Power Setting = 0 dBm
VCC = 3 V
1 Mbps GFSK 250 kHz
Standard Gain Setting
Input = −70 dBm
VCC = 3 V
18
17.5
17
−20
0
20
40
Temperature (°C)
60
17
−40
80
0
20
40
Temperature (°C)
Figure 10.
Figure 11.
RX SENSITIVITY
vs
TEMPERATURE
TX POWER
vs
TEMPERATURE
60
80
G002
4.0
TX Power Setting = 0 dBm
VCC = 3 V
1 Mbps GFSK 250 kHz
Standard Gain Setting
VCC = 3 V
2.0
Level (dBm)
−86
−88
−90
0.0
−2.0
−92
−40
−20
0
20
40
Temperature (°C)
60
−4.0
−40
80
−20
0
G003
20
40
Temperature (°C)
Figure 12.
Figure 13.
RX CURRENT
vs
SUPPLY VOLTAGE
TX CURRENT
vs
SUPPLY VOLTAGE
20
60
80
G004
20
1 Mbps GFSK 250 kHz
Standard Gain Setting
Input = −70 dBm
TA = 25°C
19.5
19
18.5
18
17.5
18.5
18
17.5
17
17
16.5
16.5
2
2.2
2.4
2.6
2.8
3
Voltage (V)
Figure 14.
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3.2
3.4
TX Power Setting = 0 dBm
TA = 25°C
19.5
Current (mA)
19
16
−20
G001
−84
Level (dBm)
18
17.5
16.5
−40
Current (mA)
18.5
3.6
G005
16
2
2.2
2.4
2.6
2.8
3
Voltage (V)
3.2
3.4
3.6
G006
Figure 15.
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CC2541
TYPICAL CHARACTERISTICS (continued)
RX SENSITIVITY
vs
SUPPLY VOLTAGE
TX POWER
vs
SUPPLY VOLTAGE
−84
4
2
Level (dBm)
−86
Level (dBm)
TX Power Setting = 0 dBm
TA = 25°C
1 Mbps GFSK 250 kHz
Standard Gain Setting
TA = 25°C
−88
−90
−92
−2
2
2.2
2.4
2.6
2.8
3
Voltage (V)
3.2
3.4
−4
3.6
2
G007
2.2
2.4
2.6
2.8
3
Voltage (V)
Figure 16.
Figure 17.
RX SENSITIVITY
vs
FREQUENCY
TX POWER
vs
FREQUENCY
−84
3.2
3.4
3.6
G008
4
1 Mbps GFSK 250 kHz
Standard Gain Setting
TA = 25°C
VCC = 3 V
−88
TX Power Setting = 0 dBm
TA = 25°C
VCC = 3 V
2
Level (dBm)
−86
Level (dBm)
0
0
−90
−2
−92
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
G009
−4
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
G010
Figure 18.
Figure 19.
Table 1. Output Power (1) (2)
TXPOWER Setting
(1)
(2)
Typical Output Power (dBm)
0xE1
0
0xD1
–2
0xC1
–4
0xB1
–6
0xA1
–8
0x91
–10
0x81
–12
0x71
–14
0x61
–16
0x51
–18
0x41
–20
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz. See SWRU191 for
recommended register settings.
1 Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy mode, 1% BER
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CC2541
Table 2. Output Power and Current Consumption
Typical Output Power (dBm)
Typical Current Consumption
(mA) (1)
Typical Current Consumption
With TPS62730 (mA) (2)
0
18.2
14.3
–20
16.8
13.1
(1)
(2)
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc =
2440 MHz. See SWRU191 for recommended register settings.
Measured on Texas Instruments CC2541 TPS62730 EM reference design with TA = 25°C, VDD = 3 V
and fc = 2440 MHz. See SWRU191 for recommended register settings.
TYPICAL CURRENT SAVINGS WHEN USING TPS62730
Current Consumption TX 0 dBm
0
25
40
25
40
DC/DC OFF
DC/DC OFF
35
DC/DC ON
35
20
Current Savings
Current Savings
30
20
10
15
Current (mA)
25
15
Current Savings (%)
Current (mA)
30
25
15
20
10
15
10
10
5
5
5
0
Current Savings (%)
DC/DC ON
20
Current Consumption RX SG
CLKCONMOD 0xBF
2.1
2.4
2.7
3
Supply (V)
3.3
3.6
Figure 20. Current Savings in TX at Room
Temperature
0
5
0
2.1
2.4
2.7
3
Supply (V)
3.3
3.6
0
Figure 21. Current Savings in RX at Room
Temperature
The application note (SWRA365) has information regarding the CC2541 and TPS62730 combo board and the
current savings that can be achieved using the combo board.
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CC2541
APPLICATION INFORMATION
Few external components are required for the operation of the CC2541. A typical application circuit is shown in
Figure 22.
Optional 32-kHz Crystal
(1)
C331
2-V to 3.6-V Power Supply
XTAL2
C401
SCL
3
SDA
4
NC
5
P1_5
6
P1_4
7
P1_3
8
P1_2
9
P1_1
P2_1 35
P2_2 34
P2_0 36
P1_7 37
P1_6 38
AVDD6 31
R301
RBIAS 30
AVDD4 29
Antenna
(50 W)
AVDD1 28
AVDD2 27
RF_N 26
CC2541
RF_P 25
DIE ATTACH PAD
AVDD3 24
XOSC_Q2 23
XOSC_Q1 22
19 P0_0
18 P0_1
17 P0_2
16 P0_3
14 P0_5
15 P0_4
12 P0_7
13 P0_6
11 P1_0
10 DVDD2
20 RESET_N
2
P2_4/XOSC32K_Q1 32
GND
P2_3/XOSC32K_Q2 33
1
DVDD1 39
DCOUPL 40
C321
AVDD5
21
XTAL1
Power Supply Decoupling Capacitors are Not Shown
Digital I/O Not Connected
C221
C231
(1) 32-kHz crystal is mandatory when running the BLE protocol stack in low-power modes, except if the link layer is in
the standby state (Vol. 6 Part B Section 1.1 in [1]).
NOTE: Different antenna alternatives will be provided as reference designs.
Figure 22. CC2541 Application Circuit
Table 3. Overview of External Components (Excluding Supply Decoupling Capacitors)
Component
Description
C401
Decoupling capacitor for the internal 1.8-V digital voltage regulator
R301
Precision resistor ±1%, used for internal biasing
Value
1 µF
56 kΩ
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2541EM,
for recommended balun.
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CC2541
Crystal
An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystal
oscillator. See 32-MHz CRYSTAL OSCILLATOR for details. The load capacitance seen by the 32-MHz crystal is
given by:
1
CL =
+ Cparasitic
1
1
+
C221 C231
(1)
XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the 32.768-kHz
crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low sleep-current
consumption and accurate wake-up times are needed. The load capacitance seen by the 32.768-kHz crystal is
given by:
1
CL =
+ Cparasitic
1
1
+
C321 C331
(2)
A series resistor may be used to comply with the ESR requirement.
On-Chip 1.8-V Voltage Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C401) for stable operation.
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
References
1. Bluetooth® Core Technical Specification document, version 4.0
http://www.bluetooth.com/SiteCollectionDocuments/Core_V40.zip
2. CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee® Applications/CC2541 System-onChip Solution for 2.4-GHz Bluetooth low energy Applications (SWRU191)
3. Current Savings in CC254x Using the TPS62730 (SWRA365).
Additional Information
Texas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and standardbased wireless applications for use in industrial and consumer applications. Our selection includes RF
transceivers, RF transmitters, RF front ends, and System-on-Chips as well as various software solutions for the
sub-1- and 2.4-GHz frequency bands.
In addition, Texas Instruments provides a large selection of support collateral such as development tools,
technical documentation, reference designs, application expertise, customer support, third-party and university
programs.
The Low-Power RF E2E Online Community provides technical support forums, videos and blogs, and the chance
to interact with fellow engineers from all over the world.
With a broad selection of product solutions, end application possibilities, and a range of technical support, Texas
Instruments offers the broadest low-power RF portfolio. We make RF easy!
The following subsections point to where to find more information.
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CC2541
Texas Instruments Low-Power RF Web Site
•
•
•
Forums, videos, and blogs
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E2E interaction
Join us today at www.ti.com/lprf-forum.
Texas Instruments Low-Power RF Developer Network
Texas Instruments has launched an extensive network of low-power RF development partners to help customers
speed up their application development. The network consists of recommended companies, RF consultants, and
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• RF circuit, low-power RF, and ZigBee® design services
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Need help with modules, engineering services or development tools?
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Low-Power RF eNewsletter
The Low-Power RF eNewsletter keeps you up-to-date on new products, news releases, developers’ news, and
other news and events associated with low-power RF products from TI. The Low-Power RF eNewsletter articles
include links to get more online information.
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Feb-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
CC2541F128RHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CC2541F128RHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CC2541F256RHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CC2541F256RHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
WISDOM FUTURE
WIRELESS WORLD
智慧未来 无线世界
CC2541
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
CC2541F128RHAR
VQFN
RHA
40
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
CC2541F128RHAT
VQFN
RHA
40
250
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
CC2541F256RHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
CC2541F256RHAT
VQFN
RHA
40
250
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
Shenzhen RF-star Technology Co.,Ltd.
TEL: 0755-86329829 FAX:0755-86329413
http://www.szrfstar.com
WISDOM FUTURE
WIRELESS WORLD
智慧未来 无线世界
CC2541
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC2541F128RHAR
VQFN
RHA
40
2500
336.6
336.6
28.6
CC2541F128RHAT
VQFN
RHA
40
250
336.6
336.6
28.6
CC2541F256RHAR
VQFN
RHA
40
2500
336.6
336.6
28.6
CC2541F256RHAT
VQFN
RHA
40
250
336.6
336.6
28.6
Shenzhen RF-star Technology Co.,Ltd.
TEL: 0755-86329829 FAX:0755-86329413
http://www.szrfstar.com
WISDOM FUTURE
WIRELESS WORLD
智慧未来 无线世界
CC2541
Shenzhen RF-star Technology Co.,Ltd.
TEL: 0755-86329829 FAX:0755-86329413
http://www.szrfstar.com
WISDOM FUTURE
WIRELESS WORLD
智慧未来 无线世界
CC2541
Shenzhen RF-star Technology Co.,Ltd.
TEL: 0755-86329829 FAX:0755-86329413
http://www.szrfstar.com
WISDOM FUTURE
WIRELESS WORLD
智慧未来 无线世界
CC2541
Shenzhen RF-star Technology Co.,Ltd.
TEL: 0755-86329829 FAX:0755-86329413
http://www.szrfstar.com
WISDOM FUTURE
WIRELESS WORLD
智慧未来 无线世界
CC2541
重要声明
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TI 保证其所销售的硬件产品的性能符合TI 标准保修的适用规范。仅在TI 保证的范围内 , 且TI 认为有必要时才会使用测试或其它质
量控制技术。除非政府做出了硬性规定 , 否则没有必要对每种产品的所有参数进行测试。
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TI 产品未获得用于关键的安全应用中的授权，例如生命支持应用（在该类应用中一旦TI 产品故障将预计造成重大的人员伤亡），除
非各方官员已经达成了专门管控此类使用的协议。购买者的购买行为即表示，他们具备有关其应用安全以及规章衍生所需的所有专业
技术和知识，并且认可和同意，尽管任何应用相关信息或支持仍可能由TI 提供，但他们将独力负责满足在关键安全应用中使用其产 品及TI
产品所需的所有法律、法规和安全相关要求。此外，购买者必须全额赔偿因在此类关键安全应用中使用TI 产品而对TI 及其 代表造成的损失。
TI 产品并非设计或专门用于军事/航空应用，以及环境方面的产品，除非TI 特别注明该产品属于“军用”或“增强型塑料”产品。只 有TI
指定的军用产品才满足军用规格。购买者认可并同意，对TI 未指定军用的产品进行军事方面的应用，风险由购买者单独承担，
并且独力负责在此类相关使用中满足所有法律和法规要求。
TI 产品并非设计或专门用于汽车应用以及环境方面的产品，除非TI 特别注明该产品符合ISO/TS 16949 要求。购买者认可并同意，
如果他们在汽车应用中使用任何未被指定的产品，TI 对未能满足应用所需要求不承担任何责任。
可访问以下URL 地址以获取有关其它TI 产品和应用解决方案的信息：
产品
应用
数字音频
www.ti.com.cn/audio
通信与电信
www.ti.com.cn/telecom
放大器和线性器件
www.ti.com.cn/amplifiers
计算机及周边
www.ti.com.cn/computer
数据转换器
www.ti.com.cn/dataconverters
消费电子
www.ti.com/consumer-apps
DLP® 产品
www.dlp.com
能源
www.ti.com/energy
DSP - 数字信号处理器
www.ti.com.cn/dsp
工业应用
www.ti.com.cn/industrial
时钟和计时器
www.ti.com.cn/clockandtimers
医疗电子
www.ti.com.cn/medical
接口
www.ti.com.cn/interface
安防应用
www.ti.com.cn/security
逻辑
www.ti.com.cn/logic
汽车电子
www.ti.com.cn/automotive
电源管理
www.ti.com.cn/power
视频和影像
www.ti.com.cn/video
微控制器 (MCU)
www.ti.com.cn/microcontrollers
RFID 系统
www.ti.com.cn/rfidsys
www.deyisupport.com
IMPORTANT NOTICE
OMAP 机动性处理器
www.ti.com/omap
无线连通性
www.ti.com.cn/wirelessconnectivity
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http://www.szrfstar.com