EVALUATION KIT AVAILABLE MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN General Description Features ● Industrial Control Systems/Process Control ● High Precision Great for DC and AC Applications ● 16-Bit Resolution with No Missing Codes ● SNR: 92.6dB ● THD: -105dB at 20kHz ● ±0.5 LSB INL (typ) ● ±0.2 LSB DNL (typ) ● Internal Reference and Reference Buffer Saves Cost and Board Space ● 6ppm/°C typ ● Tiny 12-Pin 3mm x 3mm TDFN Package ● Bipolar ±5V Analog Input Range Saves External Signal Conditioning ● Single-Supply ADC with Low Power ● 5V Analog Supply ● 2.3V to 5V Digital Supply ● 19.5mW at 500ksps ● 1µA Shutdown Mode ● 500ksps Throughput Rate (MAX11166) ● 250ksps Throughput Rate (MAX11167) ● No Pipeline Delay/Latency ● Flexible Industry-Standard Serial Interface Saves I/O Pins ● SPI/QSPI™/MICROWIRE® /DSP-Compatible ● Medical Instrumentation QSPI is a trademark of Motorola, Inc. ● Automatic Test Equipment MICROWIRE is a registered trademark of National Semiconductor Corporation. The MAX11166/MAX11167 16-bit, 500ksps/250ksps, SAR ADCs offer excellent AC and DC performance with true bipolar input range, small size, and internal reference. The MAX11166/MAX11167 measure a Q5V (10VP-P) input range while operating from a single 5V supply. A patented charge-pump architecture allows direct sampling of highimpedance sources. The MAX11166/MAX11167 integrate an optional 5ppm/NC reference with internal buffer, saving the cost and space of an external reference. These ADCs achieve 93dB SNR and -105dB THD. The MAX11166/MAX11167 guarantee 16-bit no-missing codes and Q2 LSB (max) INL. The MAX11166/MAX11167 communicate using an SPIcompatible serial interface at 2.5V, 3V, 3.3V, or 5V logic. The serial interface can be used to daisy-chain multiple ADCs in parallel for multichannel applications and provides a busy indicator option for simplified system synchronization and timing. The MAX11166/MAX11167 are offered in 12-pin, 3mm x 3mm, TDFN packages and are specified over the -40NC to +85NC temperature range. Applications ● Data Acquisition Systems Selector Guide and Ordering Information appear at end of data sheet. For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX11166.related. Typical Operating Circuit 1µF MAX9632 1µF AIN+ AIN- 500pF REF 10µF INTERFACE AND CONTROL 16-BIT ADC MAX11166 MAX11167 DIN DOUT CNVST HOST CONTROLLER CONFIGURATION REGISTER INTERNAL REFERENCE REF BUF AGNDS 19-6445; Rev 0; 8/12 OVDD (2.3V TO 5V) SCLK 50Ω ±5V VDD (5V) REFIO GND 0.1µF MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Absolute Maximum Ratings VDD to GND.............................................................-0.3V to +6V OVDD to GND........ -0.3V to the lower of (VDD + 0.3V) and +6V AIN+ to GND......................................................................... Q7V AIN-, REF, REFIO, AGNDS to GND................ -0.3V to the lower of (VDD + 0.3V) and +6V SCLK, DIN, DOUT, CNVST to GND................ -0.3V to the lower of (VDD + 0.3V) and +6V Maximum Current into Any Pin...........................................50mA Continuous Power Dissipation (TA = +70NC) TDFN (derate 18.2mW/NC above +70NC)...................1349mW Operating Temperature Range............................ -40NC to +85NC Junction Temperature.......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................. +300NC Soldering Temperature (reflow)........................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) TDFN Junction-to-Ambient Thermal Resistance (qJA).......... 59.3NC/ Junction-to-Case Thermal Resistance (qJC)............22.5NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermaltutorial. Electrical Characteristics (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500kHz or 250kHz, VREF = 4.096V; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUT (Note 3) Input Voltage Range AIN+ to AIN-, K = Absolute Input Voltage Range Analog Input CMRR 5.000 4.096 -K x VREF V V AIN+ to GND -(VDD + 0.1) +(VDD + 0.1) AIN- to GND -0.1 +0.1 Acquisition phase -10 Both inputs -20 CMRR Input Leakage Current +K x VREF -77 Input Capacitance dB +0.001 +10 µA +20 mA 15 Input-Clamp Protection Current pF DC ACCURACY (Note 4) Resolution N 16 No Missing Codes Bits 16 Differential Nonlinearity DNL Integral Nonlinearity INL Bits -0.5 +0.2 +0.5 TA = TMIN to TMAX -2.0 ±0.5 +2.0 TA = +25°C to +85°C -1.0 ±0.5 +1.0 Transition Noise 0.5 Gain Error (TMIN to TMAX) ±2 Gain Error Temperature Coefficient ±1 Offset Error (TMIN to TMAX) www.maximintegrated.com ±0.1 LSB LSB LSB ±10 LSB ppm/°C +1.1 mV Maxim Integrated │ 2 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500kHz or 250kHz, VREF = 4.096V; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN Offset Temperature Coefficient TYP MAX ±2.4 UNITS µV/°C Positive Full-Scale Error ±13 LSB Negative Full-Scale Error ±13 LSB Power-Supply Rejection (Note 5) PSR ±3.0 LSB THROUGHPUT SAMPLE RATE Throughput Sample Rate Transient Response MAX11166 0.01 500 MAX11167 0.01 250 Full-scale step 400 ksps ns DYNAMIC SPECIFICATIONS (Note 6) VREF = 2.5V, reference mode 3 Signal-to-Noise Ratio (Note 7) SNR Signal-to-Noise Plus Distortion (Note 7) SINAD Spurious-Free Dynamic Range SFDR fIN = 20kHz fIN = 20kHz VREF = 4.096V, reference mode 3 89.8 91.2 Internal reference, reference mode 0 VREF = 4.096V, reference mode 1 VREF = 2.5V, reference mode 3 VREF = 4.096V, reference mode 3 Internal reference, reference mode 0 VREF = 4.096V, reference mode 1 92.6 dB 92.4 92.5 89.5 90 92.3 dB 91.8 91.4 96 105 Total Harmonic Distortion THD -105 Intermodulation Distortion (Note 8) IMD -115 dB -96 dB dB REFERENCE (Note 7) REF Output Initial Accuracy VREF Reference mode 0 4.092 4.096 REF Output Temperature Coefficient TCREF Reference mode 0 REFIO Output Initial Accuracy VREFIO Reference modes 0 and 2 4.092 TCREFIO Reference modes 0 and 2 ±6 REFIO Output Impedance Reference modes 0 and 2 10 REFIO Input Voltage Range Reference mode 1 3 Reference Buffer Initial Offset Reference Buffer Temperature Coefficient Reference mode 1 -500 REFIO Output Temperature Coefficient Reference mode 1 CEXT Required for reference modes 0 and 1, recommended for reference modes 2 and 3 10 REF Voltage Input Range VREF Reference modes 2 and 3 2.5 www.maximintegrated.com Reference modes 2 and 3 V ±9 ±17 ppm/°C 4.096 4.100 V ±15 ppm/°C kI 4.096 ±6 External Compensation Capacitor REF Input Capacitance 4.100 4.25 V +500 µV ±10 µV/°C µF 4.25 20 V pF Maxim Integrated │ 3 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500kHz or 250kHz, VREF = 4.096V; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL REF Load Current IREF SAMPLING DYNAMICS MIN TYP 6 MHz > 0.2 SINAD > 90dB tACQ UNITS µA 130 -0.1dB point Full-Linear Bandwidth MAX 65 -3dB point Full-Power Bandwidth Acquisition Time CONDITIONS VREF = 4.096V, MAX11167, 250ksps reference modes 2 MAX11166, 500ksps and 3 100 kHz 400 ns Aperture Delay 2.5 ns Aperture Jitter 50 psRMS DIGITAL INPUTS (DIN, SCLK, CNVST) Input Voltage High VIH Input Voltage Low VIL Input Hysteresis 0.7 x VOVDD VHYS Input Capacitance CIN Input Current IIN V 0.3 x VOVDD ±0.05 x VOVDD V 10 VIN = 0V or VOVDD -10 V pF +10 µA DIGITAL OUTPUT (DOUT) Output Voltage High VOH ISOURCE = 2mA Output Voltage Low VOL ISINK = 2mA Three-State Leakage Current VOVDD - 0.4 -10 Three-State Output Capacitance V 0.4 V +10 µA 15 pF POWER SUPPLIES Analog Supply Current IVDD Internal reference mode 5.0 5.8 6.5 External reference mode 3.0 3.5 4.0 6.3 10 0.75 0.85 2.0 0.9 2.3 10 VDD Shutdown Current Interface Supply Current (Note 9) OVDD Shutdown Current Power Dissipation www.maximintegrated.com IOVDD VOVDD = 2.3V VOVDD = 5V VDD = 5V, VOVDD = 2.3V (external reference mode) VDD = 5V, VOVDD = 2.3V (internal reference mode) VDD = 5V, VOVDD = 3.0V (external reference mode) VDD = 5V, VOVDD = 3.0V (internal reference mode) VDD = 5V, VOVDD = 5V (external reference mode) VDD = 5V, VOVDD = 5V (internal reference mode) mA µA mA µA 19 30.5 20.5 mW 32 28 38 Maxim Integrated │ 4 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500kHz or 250kHz, VREF = 4.096V; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER Analog Supply Voltage Interface Supply Voltage SYMBOL MAX UNITS VDD CONDITIONS 4.75 MIN TYP 5.25 V VOVDD 2.3 5.25 V CNVST rising to data MAX11166 available MAX11167 1.35 1.5 2.7 3.0 MAX11166 500 ns MAX11167 1 µs MAX11166 0.002 100 ms MAX11167 0.004 100 ms TIMING (Note 9) Conversion Time tCONV Acquisition Time tACQ Time Between Conversions tCYC CNVST Pulse Width SCLK Period (CS Mode) SCLK Period (Daisy-Chain Mode) SCLK Low Time SCLK High Time SCLK Falling Edge to Data Valid Delay tCNVPW tSCLK tSCLK tSCLKL CS mode 5 VOVDD > 4.5V 14 VOVDD > 2.7V 20 VOVDD > 2.3V 26 VOVDD > 4.5V 16 VOVDD > 2.7V 24 VOVDD > 2.3V tSCLKH tDDO µs ns ns ns 30 5 ns 5 ns VOVDD > 4.5V 12 VOVDD > 2.7V 18 VOVDD > 2.7V 14 VOVDD > 2.3V 23 VOVDD < 2.7V 17 CS Mode 20 ns CNVST Low to DOUT D15 MSB Valid (CS Mode) tEN CNVST High or Last SCLK Falling Edge to DOUT High Impedance tDIS DIN Valid Setup Time from SCLK Falling Edge tSDINSCK DIN Valid Hold Time from SCLK Falling Edge tHDINSCK 0 ns SCLK Valid Setup Time to CNVST Falling Edge tSSCKCNF 3 ns SCLK Valid Hold Time to CNVST Falling Edge tHSCKCNF 6 ns www.maximintegrated.com VOVDD > 4.5V 3.0 VOVDD > 2.7V 5.0 VOVDD > 2.3V ns ns ns 6.0 Maxim Integrated │ 5 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500kHz or 250kHz, VREF = 4.096V; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) Note 2: Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of +25°C and +85°C. Limits below +25°C are guaranteed by design and device characterization. Typical values are not guaranteed. Note 3: See the Analog Inputs and Overvoltage Input Clamps sections. Note 4: See the Definitions section. Note 5: Defined as the change in positive full-scale code transition caused by a Q5% variation in the VDD supply voltage. Note 6: 20kHz sine wave input, -0.05dB below full scale. Note 7:See Table 4 for definition of the reference modes. Note 8:fIN1 = 19.8kHz, fIN2 = 20.2kHz, Each tone at -6.05dB below full scale. Note 9:CLOAD = 65pF on DOUT. Typical Operating Characteristics (Typical values are at TA = +25°C.) 0.1 DNL (LSB) 0.2 0.2 0 -0.2 VDD = 5.0V VOVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VREF = 4.096V -0.4 -0.6 -0.8 1.2 0.4 0 OUTPUT CODE (DECIMAL) INL AND DNL vs. TEMPERATURE VDD SUPPLY CURRENT vs. VDD SUPPLY VOLTAGE VDD = 5.0V VOVDD = 3.3V fSAMPLE = 250ksps VREF = 4.096V MIN DNL MAX DNL -0.4 7.0 TA = +25°C VOVDD = 3.3V fSAMPLE = 250ksps 6.5 6.0 5.5 REF MODE = 0 AND 1 5.0 4.5 MIN INL -40 -15 10 35 TEMPERATURE (°C) www.maximintegrated.com 60 85 0.4 0 -1.2 5.05 4.85 5.15 5.25 4.95 5.05 5.15 MAX11166 toc03 5.25 VDD SUPPLY CURRENT vs. TEMPERATURE VDD = 5.0V VOVDD = 3.3V fSAMPLE = 250ksps 6.5 6.0 5.5 REF MODE = 0 AND 1 5.0 4.5 3.0 VDD (V) 4.75 7.0 3.5 4.95 fSAMPLE = 250ksps VDD = 5.0V VOVDD = 3.3V TA = +25°C VREF = 4.096V VVDD (V) 3.0 4.85 MIN INL -0.4 3.5 4.75 MAX DNL MIN DNL REF MODE = 2 AND 3 4.0 REF MODE = 2 AND 3 4.0 -0.8 MAX INL -0.8 16384 32768 49152 65536 8192 24576 40960 57344 OUTPUT CODE (DECIMAL) 0 -1.2 -0.5 fSAMPLE = 250ksps TA = +25°C VREF = 4.096V VDD = 5.0V VOVDD = 3.3V -0.4 16384 32768 49152 65536 8192 24576 40960 57344 MAX INL 0.8 -0.3 IVDD (mA) 0 -0.2 IVDD (mA) -1.0 0 -0.1 INL AND DNL vs. VDD SUPPLY VOLTAGE 0.8 INL AND DNL (LSB) 0.3 0.4 1.2 MAX11166 toc06 0.4 MAX11166 toc04 INL (LSB) 0.6 DIFFERENTIAL NONLINEARITY vs. CODE MAX11166 toc05 0.8 INL AND DNL (LSB) 0.5 MAX11166 toc02 INTEGRAL NONLINEARITY vs. CODE MAX11166 toc01 1.0 -40 -15 10 35 60 85 TEMPERATURE (°C) Maxim Integrated │ 6 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Typical Operating Characteristics (continued) (Typical values are at TA = +25°C.) 3.75 4.25 4.75 0.2 0 5.25 VOVDD (V) VDD = 5.0V VOVDD = 3.3V 7 6 5 0 85 TA = +25°C REF MODE = 0 4.09604 4.100 -15 35 60 85 VREFIO 4.093 4.85 -0.2 -0.6 5.05 5.15 4.85 4.95 5.05 VDD (V) www.maximintegrated.com 5.15 5.25 OFFSET ERROR vs. TEMPERATURE fSAMPLE = 250ksps VDD = 5.0V VREF = 4.096V 0.2 -0.2 -1.0 4.75 5.25 MIN MEASURED VDD = 5.0V REF MODE = 0 30 DEVICES MEASURED -40 -15 10 35 60 85 TEMPERATURE (°C) 4 2 GAIN ERROR vs. SUPPLY VOLTAGE fSAMPLE = 250ksps TA = +25°C VREF = 4.096V 0 -2 -0.6 4.75 4.092 5.25 GAIN ERROR (LSBs) 0.2 4.95 0.6 OFFSET ERROR (mV) 0.6 MAX11166 toc13 fSAMPLE = 250ksps TA = +25°C VREF = 4.096V 4.25 4.096 VDD (V) 1.0 3.75 4.097 4.095 VREF 4.09594 4.75 OFFSET ERROR vs. SUPPLY VOLTAGE 3.25 MAX MEASURED 4.098 4.094 10 2.75 4.099 4.09596 -40 2.25 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE (REF PIN) TEMPERATURE (°C) OFFSET ERROR (mV) 60 INTERNAL REFERENCE VOLTAGES vs. VDD VOLTAGE IOVDD 1 IOVDD 2 VDD OR VOVDD (V) 4.09598 2 -1.0 35 4.09600 3 1.0 10 3 TEMPERATURE (°C) 4.09602 IVDD 4 0 4.09606 -15 4 1 VREF (V) SHUTDOWN CURRENT (µA) MAX11166 toc10 8 ANALOG AND DIGITAL SHUTDOWN CURRENT vs. TEMPERATURE -40 5 MAX11166 toc12 3.25 MAX11167 AT 10ksps IVDD 6 MAX11166 toc15 2.75 0.6 0.4 MAX11167 AT 10ksps 2.25 MAX11167 AT 250ksps 0.8 MAX11166 toc14 0 1.0 TA = +25°C 7 SHUTDOWN CURRENT (µA) 1.0 0.5 1.2 VDD AND OVDD SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 8 VREF (V) MAX11167 AT 250ksps VDD = 5.0V VOVDD = 3.3V CDOUT = 65pF 1.4 MAX11166 toc11 1.5 MAX11166 toc08 MAX11166 toc07 2.0 TA = +25°C VDD = 5.0V CDOUT = 65pF IOVDD (mA) IOVDD (mA) 2.5 OVDD SUPPLY CURRENT vs. TEMPERATURE MAX11166 toc09 OVDD SUPPLY CURRENT vs. OVDD SUPPLY VOLTAGE -40 -15 10 35 TEMPERATURE (°C) 60 85 -4 4.75 4.85 4.95 5.05 5.15 5.25 VDD (V) Maxim Integrated │ 7 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Typical Operating Characteristics (continued) (Typical values are at TA = +25°C.) -40 -60 -80 -100 -2 10 35 60 -140 85 25 0 4.75 4.85 -140 125 16 17 18 4.95 5.05 5.15 SNR AND SINAD (dB) MAX11166 toc18 20 SNR 92.0 -40 -15 10 35 60 TOTAL HARMONIC DISTORTION vs. TEMPERATURE -106 -107 -108 24 85 THD vs. VDD SUPPLY VOLTAGE -105 23 fIN = 20kHz fSAMPLE = 250ksps VDD = 5.0V VOVDD = 3.3V VREF = 4.096V VIN = -0.1dBFS REF MODE = 3 TEMPERATURE (°C) fIN = 20kHz fSAMPLE = 250ksps TA = +25°C VOVDD = 3.3V VREF = 4.096V VIN = -0.1dBFS REF MODE = 3 22 SINAD VDD (V) -104 21 SNR AND SINAD RATIO vs. TEMPERATURE 92.5 91.5 5.25 19 FREQUENCY (kHz) 93.0 MAX11166 toc19 fIN = 20kHz fSAMPLE = 250ksps TA = +25°C VOVDD = 3.3V VREF = 4.096V VIN = -0.1dBFS REF MODE = 3 92.0 -103 THD (dB) 100 MAX11166 toc21 SNR AND SINAD (dB) SNR SINAD fIN = 20kHz fSAMPLE = 250ksps TA = +25°C VDD = 5.0V VOVDD = 3.3V VREF = 4.096V VIN = -0.1dBFS REF MODE = 3 -104 -105 -106 -107 -108 -109 -109 -110 -111 75 SNR AND SINAD vs. VDD SUPPLY VOLTAGE 92.5 91.5 50 FREQUENCY (kHz) TEMPERATURE (°C) 93.0 -80 MAX11166 toc22 -15 -60 -120 THD (dB) -40 -40 -100 -120 -4 fIN1 = 19838Hz fIN2 = 20235Hz fSAMPLE = 250ksps TA = +25°C VDD = 5.0V VOVDD = 3.3V VREF = 4.096V VIN = -0.1dBFS REF MODE = 3 -20 MAX11166 toc20 0 TWO-TONE IMD PLOT 0 MAX11166 toc17 MAX11166 toc16 2 fIN = 20kHz fSAMPLE = 250ksps TA = +25°C VDD = 5.0V VOVDD = 3.3V VREF = 4.096V VIN = -0.1dBFS REF MODE = 3 SNR = 92.6dB SINAD = 92.5dB THD = -109.5dB -20 MAGNITUDE (dB) GAIN ERROR (LSB) fSAMPLE = 250ksps VDD = 5.0V VREFIO = 4.096V FFT PLOT 0 MAGNITUDE (dB) GAIN ERROR vs. TEMPERATURE 4 4.75 4.85 4.95 5.05 VDD (V) www.maximintegrated.com 5.15 5.25 -110 -40 -15 10 35 60 85 TEMPERATURE (°C) Maxim Integrated │ 8 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Typical Operating Characteristics (continued) (Typical values are at TA = +25°C.) 0.1 13.4 1 10 100 0.01 0.1 -100 -105 MAX11166 toc25 VIN = -0.1dB -110 -115 1 10 -120 100 VIN = -4dB 0 0.1 1.0 10 FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz) THD vs. REFERENCE VOLTAGE CMRR vs. INPUT FREQUENCY OUTPUT NOISE HISTOGRAM WITH INPUT CONNECTED TO GND -40 -108 fSAMPLE = 250ksps TA = +25°C VDD = 5.0V VOVDD = 3.3V VIN = -0.1dBFS REF MODE = 3 fIN = 20kHz www.maximintegrated.com -50 -60 -70 -80 fIN = 1kHz 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 VREF (V) fSAMPLE = 250ksps TA = +25°C VDD = 5.0V VOVDD = 3.3V VREF = 4.096V VAIN+ = VAIN- = ±100mVP-P -90 0.1 1 10 FREQUENCY (kHz) 100 200k NUMBER OF OCCURANCES -104 -120 fSAMPLE = 250ksps TA = +25°C VDD = 5.0V VOVDD = 3.3V VREF = 4.096V VIN = -0.1dBFS REF MODE = 3 14.2 13.8 MAX11166 toc26 0.01 14.6 MAX11166 toc27 82 -116 fSAMPLE = 250ksps TA = +25°C VDD = 5.0V VOVDD = 3.3V VREF = 4.096V REF MODE = 3 -90 THD (dB) fSAMPLE = 250ksps TA = +25°C VDD = 5.0V VOVDD = 3.3V VREF = 4.096V VIN = -0.1dBFS REF MODE = 3 86 84 THD RELATIVE TO FS (dB) ENOB (BITS) 88 -112 THD vs. INPUT FREQUENCY -85 -95 90 -100 15.0 CMRR (dB) SINAD (dB) 92 ENOB vs. INPUT SIGNAL FREQUENCY 150k 100 VAINP = 0V VDD = 5.0V VREF = 4.096V fSAMPLE = 250ksps TA = +25°C MAX11166 toc27 MAX11166 toc23 94 80 15.4 MAX11166 toc24 SIGNAL-TO-NOISE AND DISTORTION RATIO vs. FREQUENCY 100k 50k 0 32765 32767 32769 32771 32768 32770 32766 OUTPUT CODE (DECIMAL) Maxim Integrated │ 9 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Pin Configuration TOP VIEW REF 2 VDD 3 AIN+ 4 AIN- 5 GND 6 12 AGNDS + REFIO 1 MAX11166 MAX11167 EP 11 OVDD 10 DIN 9 SCLK 8 DOUT 7 CNVST TDFN Pin Description PIN NAME I/O FUNCTION 1 REFIO I/O External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to AGNDS. 2 REF I/O External Reference Input/Reference Buffer Decoupling. Bypass to AGNDS in close proximity with a X5R or X7R 10µF 16V chip. See the Layout, Grounding, and Bypassing section. 3 VDD I Analog Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF per PCB. 4 AIN+ I Positive Analog Input 5 AIN- I Negative Analog Input. Connect AIN- to the analog ground plane or to a remote-sense ground. 6 GND I Power-Supply Ground 7 CNVST I Convert Start Input. The rising edge of CNVST initiates conversions. The falling edge of CNVST with SCLK high enables the serial interface. 8 DOUT O Serial Data Output. DOUT will change stated on the falling edge of SCLK. 9 SCLK I Serial Clock Input. Clocks data out of the serial interface when the device is selected. 10 DIN I Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK. 11 OVDD I Digital Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF per PCB. 12 AGNDS I Analog Ground Sense. Zero current reference for the on-board DAC and reference source. Reference for REFIO and REF. — EP — www.maximintegrated.com Exposed Pad. EP is connected internally to GND. Connect to PCB GND. Maxim Integrated │ 10 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Functional Diagram DIN AIN+ AIN- INTERFACE AND CONTROL 16-BIT ADC MAX11166 MAX11167 AGNDS SCLK DOUT CNVST CONFIGURATION REGISTER CONFIGURATION REGISTER VDD OVDD SW2 SW1 INTERNAL REFERENCE 10kΩ REF BUF GND REF B5 0 0 1 1 B4 0 1 0 1 REFERENCE MODE 0 1 2 3 REFERENCE SWITCH STATE SW2 CLOSED CLOSED OPEN OPEN SW1 CLOSED OPEN CLOSED OPEN REFIO Detailed Description The MAX11166/MAX11167 are 16-bit single-channel, pseudo-differential ADCs with maximum throughput rates of 500ksps/250ksps. These ADCs include a precision internal reference that allows for measuring a bipolar input voltage range of Q5V. An external reference can also be applied for input ranges between Q3.05V and Q5.19V. Both inputs (AIN+ and AIN-) are sampled with a pseudodifferential on-chip track-and-hold exhibiting no pipeline delay or latency, making these ADCs ideal for multiplexed applications. The MAX11166/MAX11167 measure a true bipolar voltage of Q5V (10VP-P) and the inputs are protected for up to Q20mA of overrange current. These ADCs are powered from a 4.75 to 5.25V analog supply (VDD) and a separate 2.3V to 5.25V digital supply (OVDD). The MAX11166/ MAX11167 require 500ns/1Fs to acquire the input sample on an internal track-and-hold and then convert the sampled signal to 16 bits of accuracy using an internally clocked converter. Analog Inputs The MAX11166/MAX11167 ADCs consist of a true sampling pseudo-differential input stage with high-impedance, capacitive inputs. The internal T/H circuitry feature a smallsignal bandwidth of about 6MHz to provide 16-bit accu- www.maximintegrated.com rate sampling in 500ns (MAX11166)/1Fs (MAX11167). This allows for accurate sampling of a number of scanned channels through an external multiplexer. THD is optimized for input frequencies of around 20kHz. There is a gradual decrease in THD above this input frequency. See the Typical Operating Characteristics for more details. The MAX11166/MAX11167 can thus convert input signals on AIN+ in the range of -(K O VREF + AIN-) to +(K O VREF + AIN-) where K = 5.000/4.096. AIN+ should also be limited to ±(VDD + 0.1V) for accurate conversions. AIN- has an input range of -0.1V to +0.1V and should be connected to the ground reference of the input signal source. The MAX11162 /MAX11163 performs a true differential sample on inputs between AIN+ and AIN- with good commonmode rejection (see the Typical Operating Circuit). This allows for improved sampling of remote transducer inputs. Many traditional ADCs with single supplies that measure bipolar input signals use resistive divider networks directly on the analog inputs. These networks increase the complexity of the input signal conditioning. However, the MAX11166/MAX11167 include a patented input switch architecture that allows direct sampling of high-impedance sources (> 1MI) below GND without a scaling resistor-divider network. This architecture requires a minimum sample rate of 10Hz to maintain accurate conversions over the designed temperature and supply ranges. Maxim Integrated │ 11 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Overvoltage Input Clamps The MAX11166/MAX11167 include an input clamping circuit that activates when the input voltage at AIN+ is above (VDD + 300mV) or below -(VDD + 300mV). The clamp circuit remains high impedance while the input signal is within the range of Q(VDD + 100mV) and draws little to no current. However, when the input signal exceeds this range the clamps begin to turn on. Consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed the range of Q(VDD + 100mV). To make use of the input clamps, connect a resistor (RS) between the AIN+ input and the voltage source to limit the voltage at the analog input and to ensure the fault current into the devices does not exceed Q20mA. Note that the voltage at the AIN+ input pin limits to approximately 7V during a fault condition so the following equation can be used to calculate the value of RS: RS = VFAULT MAX − 7V 20mA where VFAULTMAX is the maximum voltage that the source produces during a fault condition. Figure 1 and Figure 2 illustrate the clamp circuit voltage current characteristics for a source impedance RS = 1280I. While the input voltage is within the Q(VDD + 300mV) range, no current flows in the input clamps. Once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. 20 15 ICLAMP (mA) Reference Mode 00: ADC reference is provided by the internal bandgap feed out the REFIO pin, noise filtered with an external capacitor on the REFIO pin, then buffered by the internal reference buffer and decoupled with an external capacitor on the REF pin. In this mode the ADC requires no external reference source. Reference Mode 01: ADC reference is provided externally and feeds into the REFIO pin, buffered with the internal reference buffer and decoupled with an external capacitor on the REF pin. This mode is typically used when a common reference source is needed for more than one MAX11166/MAX11167. Reference Mode 10: The internal bandgap is used as a reference source output and feed out the REFIO pin. However, the internal reference buffer is in a shutdown state and the REF pin is high impedance. This state would typically be used to provide a common reference source to a set of external reference buffers for several MAX11166/MAX11167. MAX11167/MAX11168 INPUT CLAMP CHARACTERISTICS 25 RS = 1280I VDD = 5.0V 10 0 AT SOURCE 0 -5 -10 -15 -15 -20 -20 -25 -25 -20 -10 0 10 20 30 40 SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V) Figure 1. Input Clamp Characteristics www.maximintegrated.com AT AN+ INPUT 5 -10 -30 RS = 1280I VDD = 5.0V 15 5 -40 MAX11167/MAX11168 INPUT CLAMP CHARACTERISTICS 20 AT AN+ INPUT 10 -5 The MAX11166/MAX11167 include a standard SPI interface that selects internal or external reference modes of operation through an input configuration register (see the Input Configuration Interface section). The MAX11166/ MAX11167 feature an internal bandgap reference circuit (VREFIO = 4.096V) that is buffered with an internal reference buffer that drives the REF pin. The MAX11166/ MAX11167 configure register allows four combinations of reference configuration. These reference mode are: ICLAMP (mA) 25 Internal/External Reference (REFIO) Configuration AT SOURCE -8 -6 -4 -2 0 2 4 6 8 SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V) Figure 2. Input Clamp Characteristics (Zoom In) Maxim Integrated │ 12 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Reference Mode 11: The internal bandgap reference source as well as the internal reference buffer are both in a shutdown state. The REF pin is in a high-impedance state. This mode would typically be used when an external reference source and external reference buffer is used to drive all MAX11166/MAX11167 parts in a system. Regardless of the reference mode used, the MAX11166/ MAX11167 require a low-impedance reference source on the REF pin to support 16-bit accuracy. When using the internal reference buffer, externally bypass the reference buffer output using at least a 10FF, low-inductance, lowESR capacitor placed as close as possible to the REF pin, thus minimizing additional PCB inductance. When using the internal bandgap reference source, bypass the REFIO pin with a 0.1FF capacitor to ground. If providing an external reference and using the internal reference buffer, drive the REFIO pin directly with an external reference source in the range of 3.0V to 4.25V. Finally, if disabling the MAX11166/MAX11167 internal bandgap reference source and internal reference buffer, drive the REF pin with a reference voltage in the range of 2.5V to 4.25V and place at least a 10FF, low-inductance, low-ESR capacitor placed as close as possible to the REF pin . When using the MAX11166/MAX11167 in external reference mode, it is recommended that an external reference buffer be used. For bypass capacitors on the REF pin, X7R or X5R ceramic capacitors in a 1210 case size or smaller have been found to provide adequate bypass performance. Y5U or Z5U ceramics capacitors are not recommended due to their high voltage and temperature coefficients. Maxim offers a wide range of precision references ideal for 16-bit accuracy. Table 1 lists some of the options recommended. Input Amplifier It is important to match the settling time of the input amplifier to the acquisition time of the MAX11166/MAX11167. The conversion results are accurate when the ADC samples the input signal for an interval longer than the input signal’s worst-case settling time. By definition, settling time is the interval between the application of an input voltage step and the point at which the output signal reaches and stays within a given error band centered on the resulting steady-state amplifier output level. The ADC input sampling capacitor charges during the sampling cycle, referred to as the acquisition period. During this acquisition period, the settling time is affected by the input resistance and the input sampling capacitance. This error can be estimated by looking at the settling of the sample transient on an RC time constant over the acquisition period. Although the MAX11166/MAX11167 are easy to drive, an amplifier buffer is recommended if the source impedance is such that when driving a 500pF capacitor attached to the AIN+ pin, the setting time constant of the source exceeds, tSAMPLE /14 where tSAMPLE is the desired minimum sampling time. Another application where an input amplifier is recommended is when the signal needs scaling in gain or offset to match the ADC’s full-scale input range. An optimum operational amplifier can be selected based on the following requirements: 1) Fast settling time: For multichannel multiplexed applications the driving operational amplifier must be able to settle to 16-bit resolution when a full-scale step is applied during the minimum acquisition time. 2)Low noise: It is important to ensure that the driver amplifier has a low average noise density appropriate for the desired bandwidth of the application. When the MAX11166/MAX11167 are used with its full bandwidth of 6MHz, it is preferable to use an amplifier that will produce an output noise spectral density of less than 6nV/√Hz, to ensure that the overall SNR is not degraded significantly. It is recommended to insert an external RC filter at the MAX11166/MAX11167 Table 1. MAX11166/MAX11167 External Reference Recommendations PART VOUT (V) TEMPERATURE COEFFICIENT (MAX) INITIAL ACCURACY (%) NOISE (0.1Hz TO 10Hz) (µVP-P) PACKAGE MAX6126 2.5, 3, 4.096, 5.0 3 (A), 5 (B) 0.06 1.35 µMAX-8 SO-8 MAX6325 MAX6341 MAX6350 2.5, 4.096, 5.0 1 0.04, 0.02 1.5, 2.4, 3.0 SO-8 www.maximintegrated.com Maxim Integrated │ 13 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN AIN+ input to attenuate out-of-band input noise and preserve the ADCs SNR. The effective RMS noise at the MAX11166/MAX11167 AIN+ input is 64FV, thus additional noise from a buffer circuit should be significantly lower in order to achieve the maximum SNR performance. 1)This is also the code for an overranged analog input (VAIN+ - VAIN- greater than +K x VREF, K = 5.000/4.096). 2) This is also the code for an underranged analog input (VAIN+ - VAIN- less than -K x VREF, K = 5.000/4.096) 3)THD performance: The input buffer amplifier used should have a comparable THD performance with that of the MAX11166/MAX11167 to ensure the THD of the digitized signal is not degraded. FFFF FFFE OUTPUTCODE (hex) Table 2 summarizes the operational amplifiers that are compatible with the MAX11166/MAX11167. The MAX9632 has sufficient bandwidth, low enough noise and distortion to support the full performance of the MAX11166/ MAX11167. The MAX9633 is a dual amp and can support buffering for true pseudo-differential sampling. The MAX44251/MAX44252 have sufficiently low noise and distortion for lower speed, more power-sensitive applications where multiple channels are required. 8001 5 x VREF 4.096 -5 x VREF -FS = 4.096 +FS = LSB = FULL-SCALE TRANSITION +FS - (-FS) 65536 8000 7FFF 7FFE 0001 0000 Transfer Function The ideal transfer characteristic for the MAX11166/ MAX11167 is shown in Figure 3. The precise location of various points on the transfer function are given in Table 3. -FS 0 -FS + 0.5 × LSB +FS - 1.5 × LSB -FS INPUT VOLTAGE (LSB) Figure 3. Bipolar Transfer Function Table 2. List of Recommended ADC Driver Op Amps for MAX11166/MAX11167 INPUT-NOISE DENSITY (nV/√Hz) SMALL-SIGNAL BANDWIDTH (MHz) SLEW RATE (V/µs) THD (dB) ICC (mA) MAX9632 1 55 30 -128 3.9 Low noise, THD at 10kHz MAX9633 3 27 18 -128 3.5 Low noise, dual amp, THD at 10kHz MAX44251 5.9 10 8 -124 1.75 Precision, dual amp, THD at 20kHz MAX44252 5.9 10 8 -124 1.75 Precision, quad amp, THD at 20kHz AMPLIFIER COMMENTS Table 3. Transfer Function Example CODE TRANSITION BIPOLAR INPUT (V) DIGITAL OUTPUT CODE (HEX) FS - 0.5 LSB +4.999771 FFFF - FFFE1 Midscale + 0.5 LSB +0.000076 8000 - 8001 Midscale 0 8000 Midscale - 0.5 LSB -0.000076 7FFF - 8000 FS + 0.5 LSB -4.999924 0000 - 00012 www.maximintegrated.com Maxim Integrated │ 14 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Input Configuration Interface Configuring in CS Mode An SPI interface clocked at up to 50MHz controls the MAX11166/MAX11167. Input configuration data is clocked into the configuration register on the falling edge of SCLK through the DIN pin. The data on DIN is used to program the ADC configuration register. The construct of this register is illustrated in Table 4. The configuration register defines the output interface mode, the reference mode, and the power-down state of the MAX11166/MAX11167. Figure 4 details the timing for loading the input configuration register when the MAX11166/MAX11167 are connected in CS mode (see Figure 6 and Figure 8 for hardware connections). The load process is enabled on the falling edge of CNVST when SCLK is held high. The configuration data is clocked into the configuration register through DIN on the next 8 SCLK falling edges. Pull CNVST high to complete the input configuration register load process. DIN should idle high outside an input configuration register read. Table 4. ADC Configuration Register BIT NAME MODE BIT 7:6 REF 5:4 DEFAULT STATE 00 LOGIC STATE 00 CS Mode, No-Busy Indicator 01 10 CS Mode, with Busy Indicator Daisy-Chain Mode, No-Busy Indicator 11 Daisy-Chain Mode, with Busy Indicator 00 Reference Mode 0. Internal reference and reference buffer are both powered on. 01 Reference Mode 1. Internal reference is turned off, but internal reference buffer powered on. Apply the external reference voltage at REFIO. 10 Reference Mode 2. Internal reference is powered on, but the internal reference buffer is powered off. This mode allows for internal reference to be used with an external reference buffer. 11 Reference Mode 3. Internal reference and reference buffer are both powered off. Apply an external reference voltage at REF. 0 Normal Mode. All circuitry is fully powered up at all times. 1 Static Shutdown. All circuitry is powered down. 0 Reserved, Set to 0 00 SHDN 3 0 Reserved 2:0 0 FUNCTION CNVST tHSCKCNF tSSCKCNF SCLK 0 1 2 3 tHDINSCK DIN B7 4 5 6 7 B2 B1 B0 tSDINSCK B6 B5 B4 B3 Figure 4. Input Configuration Timing in CS Mode www.maximintegrated.com Maxim Integrated │ 15 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN CNVST tHSCKCNF tSSCKCNF SCLK 0 1 2 3 4 tSDINSCK DIN 5 6 7 0 1 2 3 4 5 6 7 B0 B7 B6 B5 B4 B3 B2 B1 B0 tHDINSCK B7 B6 B5 B4 B3 B2 DATA LOADED TO PART B SHIFTED THROUGH PART A B1 DATA LOADED TO PART A Figure 5. Input Configuration Timing in Daisy-Chain Mode Configuring in Daisy-Chain Mode Figure 5 details the configuration register load process when the MAX11166/MAX11167 are connected in a daisy-chain configuration (see Figure 12 and Figure 14 for hardware connections). The load process is enabled on the falling edge of CNVST when SCLK is held high. In daisy-chain mode, the input configuration registers are chained together through DOUT to DIN. Device A’s DOUT will drive device B’s DIN. The input configuration register is an 8-bit, first-in first-out shift register. The configuration data is clocked in N times through 8 O N falling SCLK edges. After the MAX11166/MAX11167 ADCs in the chain are loaded with the configuration byte, pull CNVST high to complete the configuration register loading process. Figure 5 illustrates a configuration sequence for loading two devices in a chain. Data loaded into the configuration register alters the state of the MAX11166/MAX11167 on the next conversion cycle after the register is loaded. However, powering up the internal reference buffer or stabilizing the REFIO pin voltage will take several milliseconds to settle to 16-bit accuracy. Shutdown Mode The SHDN bit in the configuration register forces the MAX11166/MAX11167 into and out of shutdown. Set SHDN to 0 for normal operation. Set SHDN to 1 to shut down all internal circuitry and reset all registers to their default state. Output Interface The MAX11166/MAX11167 can be programmed into one of four output modes; CS modes with and without busy indicator and daisy-chain modes with and without busy www.maximintegrated.com indicator. When operating without busy indication, the user must externally timeout the maximum ADC conversion time before commencing readback. When operating in one of the two busy indication modes, the user can connect the DOUT output of the MAX11166/MAX11167 to an interrupt input on the digital host and use this interrupt to trigger the output data read. Regardless of the output interface mode used, digital activity should be limited to the first half of the conversion phase. Having SCLK or DIN transitions near the sampling instance can also corrupt the input sample accuracy. Therefore, keep the digital inputs quiet for approximately 25ns before and 10ns after the rising edge of CNVST. These times are denoted as tSQ and tHQ in all subsequent timing diagrams. In all interface modes, the data on DOUT is valid on both SCLK edges. However, the input setup time into the receiving digital host will be maximized when data is clocked into that digital host on the falling SCLK edge. Doing so will allow for higher data transfer rates between the MAX11166/MAX11167 and the digital host and consequently higher converter throughput. In all interface modes, it is recommended that the SCLK be idled low to avoid triggering an input configuration write on the falling edge of CNVST. If at anytime the device detects a high SCLK state on a falling edge of CNVST, it will enter the input configuration write mode and will write the state of DIN on the next 8 falling SCLK edges to the input configuration register. In all interface modes, all data bits from a previous conversion must be read before reading bits from a new conversion. When reading out conversion data, if too few SCLK falling edges are provided and all data bits are Maxim Integrated │ 16 MAX11166/MAX11167 not read out, only the remaining unread data bits will be outputted during the next readout cycle. In such an event, the output data in every other readout cycle will appear to have been truncated as only the leftover bits from the previous readout cycle are outputted. This is an indication to the user that there are insufficient SCLK falling edges in a given readout cycle. Table 5 provides a guide to aid in the selection of the appropriate output interface mode for a given application. CS No-Busy Indicator Mode The CS no-busy indicator mode is ideally suited for maximum throughput when a single MAX11166/MAX11167 is connected to a SPI-compatible digital host. The connection diagram is shown in Figure 6, and the corresponding timing is provided in Figure 7. A rising edge on CNVST completes the acquisition, initiates the conversion, and forces DOUT to high impedance. The conversion continues to completion irrespective of the state of CNVST allowing CNVST to be used as a select line for other devices on the board. If CNVST is brought low during a conversion and held low throughout the maximum conversion time, the MSB will be output at the end of the conversion. When the conversion is complete, the MAX11166/ MAX11167 enter the acquisition phase. Drive CNVST low to output the MSB onto DOUT. The remaining data bits are then clocked by subsequent SCLK falling edges. DOUT returns to high impedance after the 16th SCLK falling edge, or when CNVST goes high. 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Table 5. ADC Output Interface Mode Selector Guide MODE TYPICAL APPLICATION AND BENEFITS CS Mode, No-Busy Indicator Single or multiple ADCs connected to SPIcompatible digital host. Ideally suited for maximum throughput. CS Mode, With Busy Indicator Single ADC connected to SPI-compatible digital host with interrupt input. Ideally suited for maximum throughput. Daisy-Chain Mode, No-Busy Indicator Multiple ADCs connected to a SPIcompatible digital host. Ideally suited for multichannel simultaneous sampled isolated applications. Daisy-Chain Mode, With Busy Indicator Multiple ADCs connected to a SPIcompatible digital host with interrupt input. Ideally suited for multichannel simultaneous sampled isolated applications. CONVERT DIGITAL HOST CNVST MAX11166 MAX11167 DOUT DATA IN DIN CONFIG SCLK CLK Figure 6. CS No-Busy Indicator Mode Connection Diagram www.maximintegrated.com Maxim Integrated │ 17 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN CS with Busy Indicator Mode A rising edge on CNVST completes the acquisition, initiates the conversion and forces DOUT to high impedance. The conversion continues to completion irrespective of the state of CNVST allowing CNVST to be used as a select line for other devices on the board. The CS with busy indicator mode is shown in Figure 8 where a single ADC is connected to a SPI-compatible digital host with interrupt input. The corresponding timing is given in Figure 9. tCNVPW CNVST tCYC DIN ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSCKCNF tSCLK tSCLKL tHSCKCNF 1 SCLK 2 3 D15 D14 15 16 tSCLKH tDDO tEN DOUT 14 D13 tDIS D1 D0 Figure 7. CS No Busy Indicator Mode Timing CONVERT OVDD DIGITAL HOST CNVST MAX11166 MAX11167 SCLK 10kΩ DOUT DATA IN IRQ DIN CONFIG CLK Figure 8. CS With Busy Indicator Mode Connection Diagram www.maximintegrated.com Maxim Integrated │ 18 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN tCNVPW CNVST tCYC DIN ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCLK tSSCKCNF tSCLKL tHSCKCNF SCLK 1 2 3 4 15 tDDO DOUT BUSY BIT D15 D14 D13 16 17 tSCLKH tDIS D1 D0 Figure 9. CS With Busy Indicator Mode Timing When the conversion is complete, DOUT transitions from high impedance to a low logic level, signaling to the digital host through the interrupt input that data readback can commence. The MAX11166/MAX11167 then enter the acquisition phase. The data bits are then clocked out, www.maximintegrated.com MSB first, by subsequent SCLK falling edges. DOUT returns to high impedance after the 17th SCLK falling edge or when CNVST goes high, and is then pulled to OVDD through the external pullup resistor. Maxim Integrated │ 19 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Multichannel CS Configuration, Asynchronous or Simultaneous Sampling The multichannel CS configuration is generally used when multiple MAX11166/MAX11167 ADCs are connected to an SPI-compatible digital host. Figure 10 shows the connection diagram example using two MAX11166/MAX11167 devices. Figure 11 shows the corresponding timing. Asynchronous or simultaneous sampling is possible by controlling the CS1 and CS2 edges. In Figure 10, the DOUT bus is shared with the digital host limiting the throughput rate. However, maximum throughput is possible if the host accommodates each ADC’s DOUT pin independently. A rising edge on CNVST completes the acquisition, initiates the conversion and forces DOUT to high impedance. The conversion continues to completion irrespective of the state of CNVST allowing CNVST to be used as a select line for other devices on the board. However, CNVST must be returned high before the minimum conversion time for proper operation so that another conversion is not initiated with insufficient acquisition time and data correctly read out of the device. When the conversion is complete, the MAX11166/ MAX11167 enter the acquisition phase. Each ADC result can be read by bringing its CNVST input low, which consequently outputs the MSB onto DOUT. The remaining data bits are then clocked by subsequent SCLK falling edges. For each device, its DOUT will return to a high-impedance state after the 16th SCLK falling edge or when CNVST goes high. This control allows multiple devices to share the same DOUT bus. CS2 CS1 CNVST CNVST DOUT MAX11166 MAX11167 DEVICE A DIN SCLK DOUT MAX11166 MAX11167 DEVICE B DIN DIGITAL HOST CONFIG SCLK DATA IN CLK Figure 10. Multichannel CS Configuration Diagram www.maximintegrated.com Maxim Integrated │ 20 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN tCNVPW tCNVPW CNVSTA(CS1) tCYC CNVSTB(CS2) DIN tACQ tCONV ACQUISITION CONVERSION tSSCKCNF ACQUISITION SCLK 1 2 tEN DOUT tSCLK tSCLKL tHSCKCNF 3 15 tDDO D15 D14 16 tSCLKH D13 17 18 19 31 tEN tDIS tDIS D1 D0 D15 32 D14 D13 D1 D0 Figure 11. Multichannel CS Configuration Timing Daisy-Chain, No-Busy Indicator Mode The daisy-chain mode with no-busy indicator is ideally suited for multichannel isolated applications that require minimal wiring complexity. Simultaneous sampling of multiple ADC channels is realized on the serial interface where data readback is analogous to clocking a shift register. Figure 12 shows a connection diagram of two MAX11166/MAX11167s configured in a daisy chain. The corresponding timing is given in Figure 13. A rising edge on CNVST completes the acquisition and initiates the conversion. Once a conversion is initiated, it continues to completion irrespective of the state of CNVST. When a conversion is complete, the MSB is presented onto DOUT and the MAX11166/MAX11167 return to the acquisition phase. The remaining data bits are stored within an internal shift register. To read these bits out, CNVST is brought low and each bit is shifted out on subsequent SCLK falling edge. The DIN input of each ADC in the chain is used to transfer conversion data from the previous ADC into the internal shift register of the next ADC, thus allowing for data to be clocked through the multichip chain on each SCLK falling edge. Each ADC in the chain outputs its MSB data first requiring 16 × N clocks to read back N ADCs. www.maximintegrated.com In daisy-chain mode, the maximum conversion rate is reduced due to the increased readback time. For instance, with a 5ns digital host setup time and 3V interface, up to four MAX11166/MAX11167 devices running at a conversion rate of 218ksps can be daisy-chained. Daisy-Chain with Busy Indicator Mode The daisy-chain mode with busy indicator is ideally suited for multichannel isolated applications that require minimal wiring complexity while providing a conversion complete indication that can be used to interrupt a host processor to read data. Simultaneous sampling of multiple ADC channels is realized on the serial interface where data readback is analogous to clocking a shift register. The daisy-chain mode with busy indicator is shown in Figure 14 where three MAX11166/MAX11167s are connected to a SPI-compatible digital host with corresponding timing given in Figure 15. A rising edge on CNVST completes the acquisition and initiates the conversion. Once a conversion is initiated, it continues to completion irrespective of the state of CNVST. When a conversion is complete, the busy indicator is presented onto each DOUT and the MAX11166/MAX11167 return to the acquisition phase. The busy indicator for the Maxim Integrated │ 21 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN last ADC in the chain can be connected to an interrupt input on the digital host. The digital host should insert a 50ns delay from the receipt of this interrupt before reading out data from all ADCs to ensure that all devices in the chain have completed conversion. The DIN input of each ADC in the chain is used to transfer conversion data from the previous ADC into the internal shift register of the next ADC, thus allowing for data to be clocked through the multichip chain on each SCLK falling edge. The total of number of falling SCLKs needed to read back all data from N ADCs is 16 × N + 1 edges, the one additional SCLK falling edge required to clock out the busy mode bit from the host side ADC. The conversion data is stored within an internal shift register. To read these bits out, CNVST is brought low and each bit is shifted out on subsequent SCLK falling edge. CONFIG CONVERT CNVST DIN CNVST MAX11166 MAX11167 DA DOUT MAX11166 MAX11167 DIN DEVICE A DEVICE B SCLK SCLK DIGITAL HOST DB DOUT DATA IN CLK Figure 12. Daisy-Chain, No-Busy Indicator Mode Connection Diagram tCNVPW CNVST tCYC DIN tCONV ACQUISITION tACQ CONVERSION ACQUISITION SCLK 1 2 3 DB15 DB14 tHSCKCNF 14 15 16 17 18 DB1 DB0 DA15 DA14 30 31 32 DA1 DA0 tSCLKH tDDO DOUTB tSSCKCNF tSCLK tSCLKL DB13 Figure 13. Daisy-Chain, No-Busy Indicator Mode Timing www.maximintegrated.com Maxim Integrated │ 22 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN CONFIG CONVERT CNVST DIN MAX11166 MAX11167 CNVST DA DOUT DIN CNVST MAX11166 MAX11167 DOUT DB DIN DC MAX11166 DOUT MAX11167 DEVICE A DEVICE B DEVICE C SCLK SCLK SCLK DIGITAL HOST DATA IN IRQ CLK Figure 14. Daisy-Chain Mode with Busy Indicator Connection Diagram tCNVPW CNVST tCYC DIN tCONV ACQUISITION tACQ ACQUISITION CONVERSION SCLK 1 2 3 4 tSSCKCNF tSCLK tSCLKH 15 tDDO 16 17 18 19 31 32 33 34 35 47 tHSCKCNF 48 49 DA1 DA10 tSCLKL DOUTA = DINB BUSY DA15 DA14 DA13 BIT DA1 DA0 DOUTB = DINC BUSY DB15 DB14 DB13 BIT DB1 DB0 DA15 DA14 DA1 DA0 DOUTC BUSY DC15 DC14 DC13 BIT DC1 DC0 DB15 DB14 DB1 DB0 DA15 DA14 Figure 15. Daisy-Chain Mode with Busy Indicator Timing www.maximintegrated.com Maxim Integrated │ 23 MAX11166/MAX11167 In daisy-chain mode, the maximum conversion rate is reduced due to the increased readback time. For instance, with a 5ns digital host setup time and 3V interface, up to four MAX11166/MAX11167 devices running at a conversion rate of 217ksps can be daisy-chained on a 3-wire port. Layout, Grounding, and Bypassing For best performance, use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. Connect the GND and AGNDS pins on the MAX11166/MAX11167 to this ground plane. Keep the ground return to the power-supply low impedance and as short as possible for noise-free operation. A 500pF C0G (or NPO) ceramic chip capacitor should be placed between AIN+ and the ground plane as close as possible to the MAX11166/MAX11167. This capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. For best performance, connect the REF output to the ground plane with a 16V, 10FF ceramic chip capacitor with a X5R or X7R dielectric in a 1210 or smaller case size. Ensure that all bypass capacitors are connected directly into the ground plane with an independent via. Bypass VDD and OVDD to the ground plane with 0.1FF ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. Add at least one bulk 10FF decoupling capacitor to VDD and OVDD per PCB. For best performance, bring a VDD power plane in on the analog interface side of the MAX11166/MAX11167 and a OVDD power plane from the digital interface side of the device. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. www.maximintegrated.com 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of less than Q1 LSB guarantees no missing codes and a monotonic transfer function. Offset Error For the MAX11166/MAX11167, the offset error is defined at code transition 0x8000 to 0x8001. The offset code transitions should occur with an analog input voltage of exactly 0.5 x (5.0V/4.096V) x VREF /65536 above GND. The offset error is defined as the deviation between the actual analog input voltage required to produce the offset code transition and the ideal analog input of 0.5 x (5.0V/4.096V) x VREF /65536 above GND, expressed in LSBs. Gain Error Gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, subtracted from the ideal change in analog input voltage on (5.0V/4.096V) x VREF x (65534/65536). For the MAX11166/MAX11167, top code transition is 0xFFFE to 0xFFFF. The bottom code transition is 0x0000 and 0x0001. For the MAX11166/ MAX11167, the analog input voltage to produce these code transitions is measured and then the gain error is computed by subtracting 2.0 x (5.0V/4.096V) x VREF x (65534/65536) from this measurement. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB where N = 16 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components not including the fundamental, the first five harmonics, and the DC offset. Maxim Integrated │ 24 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Signal-to-Noise Plus Distortion Spurious-Free Dynamic Range Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all the other ADC output signals: Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component. Signal RMS = 20 × log SINAD(dB) (Noise + Distortion) RMS Effective Number of Bits The effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows: SINAD − 1.76 ENOB = 6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: 2 2 2 2 V2 + V3 + V4 + V5 = 20 × log THD V 1 Aperture Delay Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in aperture delay. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in a manner that ensures that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3dB. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as full-power input bandwidth frequency. where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics. www.maximintegrated.com Maxim Integrated │ 25 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Selector Guide PART BITS INPUT RANGE (V) REFERENCE PACKAGE SPEED (ksps) MAX11160 16 0 to 5 Internal µMAX-10, 3mm x 3mm TDFN-10 500 MAX11161 16 0 to 5 Internal µMAX-10, 3mm x 3mm TDFN-10 250 MAX11162 16 0 to 5 External µMAX-10, 3mm x 3mm TDFN-10 500 MAX11163 16 0 to 5 External µMAX-10, 3mm x 3mm TDFN-10 250 MAX11164 16 0 to 5 Internal/External 3mm x 3mm TDFN-12 500 MAX11165 16 0 to 5 Internal/External 3mm x 3mm TDFN-12 250 MAX11166 16 ±5 Internal/External 3mm x 3mm TDFN-12 500 MAX11167 16 ±5 Internal/External 3mm x 3mm TDFN-12 250 MAX11168 16 ±5 Internal µMAX-10, 3mm x 3mm TDFN-10 500 MAX11169 16 ±5 Internal µMAX-10, 3mm x 3mm TDFN-10 250 Package Information Ordering Information PART TEMP RANGE PIN-PACKAGE MAX11166ETC+* -40°C to +85°C 12 TDFN-EP** MAX11167ETC+ -40°C to +85°C 12 TDFN-EP** +Denotes a lead(Pb)-free/RoHS-compliant package. *Future Product—Contact factory for availability. **EP = Exposed Pad. For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE PACKAGE OUTLINE LAND TYPE CODE NO. PATTERN NO. 12 TDFN-EP www.maximintegrated.com TD1233+1 21-0664 90-0397 Maxim Integrated │ 26 MAX11166/MAX11167 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 8/12 Initial release — For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc. © 2012 Maxim Integrated │ 27