ONSEMI MC74VHC1G66_11

MC74VHC1G66
SPST (NO) Normally Open
Analog Switch
MARKING DIAGRAMS
5
SC−88A
DF SUFFIX
CASE 419A
High Speed: tPD = 20 ns (Typ) at VCC = 5.0 V
5
5
1
Low Power Dissipation: ICC = 1.0 mA (Max) at TA = 25°C
V9
M
G
Diode Protection Provided on Inputs and Outputs
Improved Linearity and Lower ON Resistance over Input Voltage
V9 MG
G
1
V9 MG
G
TSOP−5
DT SUFFIX
CASE 483
Features
•
•
•
•
•
•
•
•
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M
The MC74VHC1G66 is a single pole single throw (SPST) analog
switch. It achieves high speed propagation delays and low ON
resistances while maintaining low power dissipation. This bilateral
switch controls analog and digital voltages that may vary across the
full power−supply range (from VCC to GND).
The MC74VHC1G66 is compatible in function to a single gate of
the High Speed CMOS MC74VHC4066 and the metal−gate CMOS
MC14066. The device has been designed so that the ON resistances
(RON) are much lower and more linear over input voltage than RON of
the metal−gate CMOS or High Speed CMOS analog switches.
The ON/OFF control inputs are compatible with standard CMOS
outputs. The ON/OFF control input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup,
hot insertion, etc.
1
= Device Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
Chip Complexity: 11 FETs or 3 Equivalent Gates
ON/OFF Control Input has OVT
Chip Complexity: FETs = 11
These Devices are Pb−Free and are RoHS Compliant
PIN ASSIGNMENT
1
IN/OUT XA
2
OUT/IN YA
3
GND
4
ON/OFF CONTROL
5
VCC
FUNCTION TABLE
On/Off Control Input
State of Analog Switch
L
H
Off
On
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 15
1
Publication Order Number:
MC74VHC1G66/D
MC74VHC1G66
IN/OUT XA
1
OUT/IN YA
2
GND
3
5
4
VCC
IN/OUT XA
1
6
VCC
OUT/IN YA
2
5
NC
GND
3
4
ON/OFF
CONTROL
ON/OFF
CONTROL
(SC−88A, TSOP−5)
(UDFN6)
Figure 1. Pinout Diagrams
X1
U
IN/OUT XA
1
1
U
ON/OFF CONTROL
Figure 2. Logic Symbol
OUT/IN
YA
MAXIMUM RATINGS
Symbol
Characteristics
VCC
DC Supply Voltage
VIN
Digital Input Voltage
VIS
Analog Output Voltage
IIK
ICC
TSTG
V
−0.5 to +7.0
V
V
Digital Input Diode Current
−20
mA
DC Supply Current, VCC and GND
+25
mA
*65 to )150
°C
260
°C
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85°C
MSL
Moisture Sensitivity
FR
Flammability Rating
ILATCHUP
Unit
−0.5 to VCC +0.5
TL
VESD
Value
−0.5 to +7.0
ESD Withstand Voltage
Latchup Performance
)150
°C
SC70−5 (Note 1)
SOT23−5
350
230
°C/W
SC70−5
SOT23−5
150
200
mW
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
N/A
V
Above VCC and Below GND at 125°C (Note 5)
$500
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
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2
MC74VHC1G66
RECOMMENDED OPERATING CONDITIONS
Characteristics
Min
Max
Unit
2.0
5.5
V
DC Input Voltage
GND
5.5
V
VIS
DC Output Voltage
GND
VCC
V
TA
Operating Temperature Range
−55
+125
°C
tr, tf
Input Rise and Fall Time
ON/OFF Control Input
0
0
100
20
ns/V
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
Time, Years
80
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
Time, Hours
TJ = 90 ° C
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ =100° C
Device Junction Temperature versus
Time to 0.1% Bond Failures
TJ =110 ° C
VIN
TJ =120° C
DC Supply Voltage
TJ = 130 ° C
VCC
NORMALIZED FAILURE RATE
Symbol
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
TA = 25°C
VCC
(V)
Min
1.5
2.1
3.15
3.85
Max
TA ≤ 85°C
Min
Max
Min
Max
Minimum High−Level
Input Voltage
ON/OFF Control Input
RON = Per Spec
2.0
3.0
4.5
5.5
VIL
Maximum Low−Level
Input Voltage
ON/OFF Control Input
RON = Per Spec
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
IIN
Maximum Input
Leakage Current
ON/OFF Control Input
VIN = VCC or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
VIO = 0 V
5.5
1.0
20
40
mA
RON
Maximum ”ON”
Resistance
VIN = VIH
VIS = VCC or GND
|IIS| ≤ 5 mA (Figure 4)
3.0
4.5
5.5
60
45
40
70
50
45
100
60
55
W
IOFF
Maximum Off−Channel
Leakage Current
VIN = VIL
VIS = VCC or GND
Switch Off (Figure 5)
5.5
0.1
0.5
1.0
mA
3
1.5
2.1
3.15
3.85
Unit
VIH
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1.5
2.1
3.15
3.85
−55 ≤ TA ≤ 125°C
V
MC74VHC1G66
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr/tf = 3.0 ns
Symbol
Parameter
TA = 25°C
Max
Max
Unit
1
0.6
0.6
0.6
5
2
1
1
6
3
1
1
7
4
2
1
ns
2.0
3.0
4.5
5.5
32
28
24
20
40
35
30
25
45
40
35
30
50
45
40
35
ns
2.0
3.0
4.5
5.5
32
28
24
20
40
35
30
25
45
40
35
30
50
45
40
35
ns
ON/OFF Control Input
0.0
3
10
10
10
pF
Control Input = GND
Analog I/O
Feedthrough
5.0
4
4
10
10
10
10
10
10
YA = Open
tPLZ,
tPHZ
Maximum
Propagation Delay,
ON/OFF Control to Analog
Output
RL = 1000 W
tPZL,
tPZH
Maximum
Propagation Delay,
ON/OFF Control to
Analog Output
RL = 1000 W
Maximum Input
Capacitance
(Figure 14)
(Figure 15)
(Figure 15)
Min
−55 ≤ TA ≤ 125°C
Typ
Maximum
Propagation Delay,
Input X to Y
Min
TA ≤ 85°C
2.0
3.0
4.5
5.5
Test Conditions
tPLH,
tPHL
CIN
VCC
(V)
Max
Min
Typical @ 25°C, VCC = 5.0 V
CPD
18
Power Dissipation Capacitance (Note 6)
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol
BW
ISOoff
NOISEfeed
THD
Test Conditions
VCC
Limit
25°C
Maximum On−Channel Bandwidth or
Minimum Frequency Response
(Figure 10)
fin = 1 MHz Sine Wave
Adjust fin voltage to obtain 0 dBm at VOS
Increase fin = frequency until dB meter reads −3 dB
RL = 50 W
3.0
4.5
5.5
150
175
180
MHz
Off−Channel Feedthrough Isolation
(Figure 11)
fin = Sine Wave
Adjust fin voltage to obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 W
3.0
4.5
5.5
−80
−80
−80
dB
Feedthrough Noise Control to Switch
(Figure 12)
Vin ≤ 1 MHz Square Wave (tr = tf = 2 ns)
3.0
4.5
5.5
45
60
130
mVPP
Total Harmonic Distortion
(Figure 13)
fin = 1 kHz, RL = 10 kW
THD = THDMeasured − THDSource
VIS = 3.0 VPP sine wave
VIS = 5.0 VPP sine wave
Parameter
RL = 600 W
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4
Unit
%
3.3
5.5
0.30
0.15
MC74VHC1G66
PLOTTER
POWER
SUPPLY
-
DC PARAMETER
ANALYZER
COMPUTER
+
VCC
VCC
1
VCC
5
1
2
5
2
VCC
3
VIL
A
4
3
Figure 4. On Resistance Test Set−Up
VCC
4
Figure 5. Maximum Off−Channel Leakage Current
Test Set−Up
VCC
1
A
5
1
2
N/C
VCC
3
2
TEST
POINT
VIH
5
4
VCC
3
Figure 6. Maximum On−Channel Leakage Current
Test Set−Up
4
Figure 7. Propagation Delay Test Set−Up
Switch to Position 2 when testing tPLZ and tPZL
Switch to Position 1 when testing tPHZ and tPZH
VCC
TEST POINT
VCC
VCC
1
1
2
A
5
2
VCC
1
N/C
1
N/C
2
5
RL
CL*
3
3
4
4
2
*Includes all probe and jig capacitance.
Figure 8. Propagation Delay Output Enable/Disable
Test Set−Up
Figure 9. Power Dissipation Capacitance
Test Set−Up
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5
MC74VHC1G66
VOS
VIS
VCC
0.1 mF
fin
1
VOS
VCC
0.1 mF
fin
5
1
2
dB
Meter
5
2
3
dB
Meter
4
RL
3
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 10. Maximum On−Channel Bandwidth
Test Set−Up
Figure 11. Off−Channel Feedthrough Isolation
Test Set−Up
(VCC)/2
VCC
RL
RL
1
5
V
VOS
2
IS
IN
v 1 MHz
t r + t + 2 ns
f
3
VCC
4
GND
*Includes all probe and jig capacitance.
Figure 12. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set−Up
To Distortion
Meter
(VCC)/2
VIS
VCC
0.1 mF
RL
4
fin
1
5
VOS
2
3
4
*Includes all probe and jig capacitance.
Figure 13. Total Harmonic Distortion Test Set−Up
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6
MC74VHC1G66
VCC
XA
50% VCC
50%
tPLH
tPHL
VOH
YA
50% VCC
VOL
Figure 14. Propagation Delay, Analog In to Analog Out Waveforms
tr
Control
tf
90%
50% VCC
10%
tPZL
VCC
tPLZ
High
Impedance
50% VCC
10%
Analog Out
90%
50% VCC
tPHZ
tPZH
VOL
VOH
High
Impedance
Figure 15. Propagation Delay, ON/OFF Control
ORDERING INFORMATION
Device
Package
MC74VHC1G66DFT1G
SC−88A
(Pb−Free)
MC74VHC1G66DFT2G
SC−88A
(Pb−Free)
MC74VHC1G66DTT1G
TSOP−5
(Pb−Free)
Shipping†
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MC74VHC1G66
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE K
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
M
B
M
N
J
C
H
K
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8
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74VHC1G66
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
D 5X
NOTE 5
2X
0.10 T
2X
0.20 T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
0.20 C A B
M
5
1
4
2
L
3
B
S
K
DETAIL Z
G
A
DIM
A
B
C
D
G
H
J
K
L
M
S
DETAIL Z
J
C
0.05
SEATING
PLANE
H
T
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
1.25
1.55
0_
10 _
2.50
3.00
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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MC74VHC1G66/D