INFINEON ICE2QR4765G

Datasheet,Version 2.0, July 26, 2011
®
CoolSET - Q1
ICE2QR4765G
Off-Line SMPS Quasi-Resonant
PWM Controller with integrated
650V CoolMOS ® a n d s t a r t u p c e l l i n
DSO-16/12
Power Management & Supply
N e v e r
s t o p
t h i n k i n g .
CoolSET® - Q1
ICE2QR4765G
Revision History:
July 26, 2011
Previous Version:
1.0
Page
Datasheet
Subjects (major changes since last revision)
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon
Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com
CoolMOS®, CoolSET® are trademarks of Infineon Technologies AG.
Edition 2011-07-26
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 7/26/11.
All Rights Reserved.
Attention please!
The information given in this data sheet shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
CoolSET® - Q1
ICE2QR4765G
Off-Line SMPS Quasi-Resonant PWM
Controller with integrated 650V CoolMOS® and
startup cell in DSO-16/12
Product Highlights
•
•
•
•
•
Quasi resonant operation
Active Burst Mode to reach the lowest standby power requirement
<100mW@no load
Digital frequency reduction for better overall system efficiency
Integrated 650V avalanche rugged CoolMOS® with startup cell
PB-free lead plating; RoHS compliant
Features
•
•
•
•
•
•
•
•
•
•
•
Description
650V avalanche rugged CoolMOS® with built-in startup
cell
Quasiresonant operation till very low load
Active burst mode operation for low standby input power
(< 0.1W)
Digital frequency reduction with decreasing load for
reduced switching loss
Built-in digital soft-start
Foldback point correction and cycle-by-cycle peak
current limitation
Maximum on/off time limitation
Auto restart mode for VCC Overvoltage and
Undervoltage protections
Auto restart mode for overload protection
Auto restart mode for overtemperature protection
Latch-off mode for adjustable output overvoltage
protection and transformer short-winding protection
The CoolSET®-Q1 series (ICE2QRxx65) is the first
generation of quasi-resonant integrated power ICs. It is
optimized for off-line switch mode power supply applications
such as LCD monitor, DVD R/W, DVD Combo, Blue-ray
DVD, set top box, etc. Operating the MOSFET switch in
quasi-resonant mode, lower EMI, higher efficiency and lower
voltage stress on secondary diodes are expected for the
SMPS. Based on the BiCMOS technology, the CoolSET®-Q1
series has a wide operation range (up to 25V) of IC power
supply and lower power consumption. It also offers many
advantages such as quasi-resonant operation till very low load
which increases the average system efficiency, Active Burst
Mode operation which enables an ultra-low power
consumption at standby mode with small and controllable
output voltage ripple, etc.
Wp
Snubber
Cbus
CZC RZC2
85 ~ 265 VAC
PG-DSO-16/12
Lf
DO
Ws
RZC1
Cf VO
CO
Wa
RVCC DVCC
CVCC
Dr1~Dr4
ZC
Drain
VCC
Power Management
CPS
Startup Cell
Rb1
PWM controller
Current Mode Control
Cycle-by-Cycle
current limitation
Zero Crossing Block
GND
CS
CoolMOS
Rb2
Optocoupler
Rc1
FB
Active Burst Mode
Protections
Control Unit
Rovs1
RCS
®
TL431
®
Cc1
CoolSET -Q1
Cc2
Rovs2
Type
Package
Marking
VDS
RDSon1)
230VAC ±15%2)
85-265 VAC2)
ICE2QR4765G
PG-DSO-16/12
2QR4765G
650V
4.70
29W
17W
1)
typ @ T=25°C
2)
Calculated maximum input power rating at Ta=50°C, Ti=125°C and without copper area as heat sink.
Version 2.0
3
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Table of Contents
Page
1
1.1
1.2
1.3
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration with PG-DSO-16/12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package PG-DSO-16/12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.1.3
3.3.2
3.4
3.4.1
3.5
3.5.1
3.5.2
3.5.3
3.6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VCC Pre-Charging and Typical VCC Voltage During Start-up . . . . . . . . . . . . . . . . 7
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Digital Frequency Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Up/down counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Zero crossing (ZC counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ringing suppression time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switch Off Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Foldback Point Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Entering Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
During Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Leaving Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Foldback Point Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Zero Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoolMOS® Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Typical CoolMOS® Performance Characteristic . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Input power curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Version 2.0
4
5
5
5
5
12
12
12
13
13
13
14
14
14
14
15
15
16
16
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Pin Configuration and Functionality
1
Pin Configuration and Functionality
1.1
Pin Configuration with PG-DSO-16/
12
Pin
Symbol
ZC
Zero crossing
2
FB
Feedback
3
N.C.
Not Connected
4
CS
Current Sense
5
Drain
650V1) CoolMOS™ Drain
6
Drain
650V1) CoolMOS™ Drain
7
Drain
650V1) CoolMOS™ Drain
8
Drain
650V1) CoolMOS™ Drain
9
N.C.
Not Connected
10
N.C.
Not Connected
11
VCC
Controller Supply Voltage
12
GND
Controller Ground
FB (Feedback)
Normally, an external capacitor is connected to this pin for a
smooth voltage VFB. Internally, this pin is connected to the
PWM signal generator for switch-off determination
(together with the current sensing signal), the digital signal
processing for the frequency reduction with decreasing load
during normal operation, and the Active Burst Mode
controller for entering Active Burst Mode operation
determination and burst ratio control during Active Burst
Mode operation. Additionally, the open-loop / over-load
protection is implemented by monitoring the voltage at this
pin.
CS (Current Sense)
This pin is connected to the external shunt resistor for the
primary current sensing and the internal PWM signal
generator for switch-off determination (together with the
feedback voltage). Moreover, short-winding protection is
realised by monitoring the voltage Vcs during on-time of the
main power switch.
at Tj = 110°C
1.2
Package PG-DSO-16/12
ZC
1
12
GND
FB
2
11
VCC
N.C.
3
10
N.C.
CS
4
9
N.C.
Pin Functionality
ZC (Zero Crossing)
At this pin, the voltage from the auxiliary winding after a
time delay circuit is applied. Internally, this pin is connected
to the zero-crossing detector for switch-on determination.
Additionally, the output overvoltage detection is realized by
comparing the voltage Vzc with an internal preset threshold.
Function
1
1)
1.3
Drain (Drain of integrated CoolMOS®)
Drain pin is the connection to the drain of the internal
CoolMOS®.
VCC (Power supply)
VCC pin is the positive supply of the IC. The operating range
is between VVCCoff and VVCCOVP.
GND (Ground)
This is the common ground of the controller.
Figure 1
Version 2.0
Drain
5
8
Drain
Drain
6
7
Drain
Pin Configuration PG-DSO-16/12 (top view)
5
July 26, 2011
Figure 2
Version 2.0
6
2pF
25kO
RFB
VREF
D1
C3
C2
VFBBOff
VFBBOn
VFBEB
VFBZL
VFBZH
VFBR1
VFBOLP
VZCRS
VZCOVP
C10
C9
C8
C7
C6
C5
C4
Count=7
C1
Comparator
ZC counter
tBEB
&
Active
Burst Mode
Ringing
Suppression
G1
Active Burst Block
Regulation
tOLP_B
Delay
tZCOVP
tCOUNT
Up/down counter
clk
Zero Crossing
VPWM
q
OSC
f
en sB
PWM
Comparator
Soft-start
VVCCOVP
Current Mode
10.5
18V
Undervoltage Lockout
Power Management
GPWM
1
G3
1
G4
R
S
G8
Q
C15
G2
1
G7
1
Foldback
Correction
C13 VCSB
10us
Internal
Bias
PWM Control
PWM OP
&
G6
&
G5
C12
Voltage
Reference
C14
Leading
Edge
Blanking
tLEB
TOnMax
&
G9
1pF
Current Limiting
D1
10kO
CoolMOS®
Gate
Drive
VCSSW
Gate Driver
R
latched
Protect
TOffMax
Delay
tCSSW
Q
R
Autorestart
Protect
S Q
S
Protection
OTP
Startup Cell
Drain
CS
GND
2
FB
ZC
VZCC
VCC
CoolSET® - Q1
ICE2QR4765G
Representative Blockdiagram
Representative Blockdiagram
Representative Block diagram
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Functional Description
3
Functional Description
3.1
VCC Pre-Charging and Typical
VCC Voltage During Start-up
3.2
As shown in Figure 4, at the time ton, the IC begins to
operate with a soft-start. By this soft-start the switching
stresses for the switch, diode and transformer are minimised.
The soft-start implemented in ICE2QR4765G is a digital
time-based function. The preset soft-start time is 12ms with
4 steps. If not limited by other functions, the peak voltage on
CS pin will increase step by step from 0.32V to 1V finally.
In ICE2QR4765G, a startup cell is integrated into the
CoolMOS®. As shown in Figure 2, the start cell consists of a
high voltage device and a controller, whereby the high
voltage device is controlled by the controller. The startup
cell provides a pre-charging of the VCC capacitor till VCC
voltage reaches the VCC turned-on threshold VVCCon and the
IC begins to operate.
Once the mains input voltage is applied, a rectified voltage
shows across the capacitor Cbus. The high voltage device
provides a current to charge the VCC capacitor Cvcc. Before
the VCC voltage reaches a certain value, the amplitude of the
current through the high voltage device is only determined
by its channel resistance and can be as high as several mA.
After the VCC voltage is high enough, the controller controls
the high voltage device so that a constant current around
1mA is provided to charge the VCC capacitor further, until
the VCC voltage exceeds the turned-on threshold VVCCon. As
shown in the time phase I in Figure 3, the VCC voltage
increase near linearly and the charging speed is independent
of the mains voltage level.
Vcs_sst
(V)
1.00
0.83
0.66
0.49
0.32
ton
Figure 4
VVCC
VVCCon
I
II
3.3
III
Figure 3
t2
t
VCC voltage at start up
The time taking for the VCC pre-charging can then be
approximately calculated as:
t
V VCCon ⋅ C vcc
= -----------------------------------------1
I
VCCch arg e2
[1]
6
9
12
Time(ms)
Maximum current sense voltage during
softstart
Normal Operation
3.3.1
Digital Frequency Reduction
As mentioned above, the digital signal processing circuit
consists of an up/down counter, a ZC counter and a
comparator. These three parts are key to implement digital
frequency reduction with decreasing load. In addition, a
ringing suppression time controller is implemented to avoid
mistriggering by the high frequency oscillation when the
output voltage is very low under conditions such as soft start
period or output short circuit. Functionality of these parts is
described in the following.
where IVCCcharge2 is the charging current from the startup cell
which is 1.05mA, typically.
When the VCC voltage exceeds the VCC turned-on
threshold VVCCon at time t1, the startup cell is switched off and
the IC begins to operate with soft-start. Due to power
consumption of the IC and the fact that there is still no energy
from the auxiliary winding to charge the VCC capacitor
before the output voltage is built up, the VCC voltage drops
(Phase II). Once the output voltage is high enough, the VCC
capacitor receives the energy from the auxiliary winding
from the time point t2 onward. The VCC will then reach a
constant value depending on output load.
Version 2.0
3
The PWM controller during normal operation consists of a
digital signal processing circuit including an up/down
counter, a zero-crossing counter (ZC counter) and a
comparator, and an analog circuit including a current
measurement unit and a comparator. The switch-on and -off
time points are determined by the digital circuit and the
analog circuit respectively. The zero-crossing input signal
and the value of the up/down counter are needed for the
switch-on determination while the feedback signal VFB and
the current sensing signal VCS are necessary for the switchoff determination. Details about the full operation of the
PWM controller in normal operation are illustrated in the
following paragraphs.
VVCCoff
t1
Soft-start
3.3.1.1
Up/down counter
The up/down counter stores the number of the zero crossing
where the main power switch is switched on after
demagnetisation of the transformer. This value is fixed
7
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Functional Description
according to the feedback voltage, VFB, which contains
information about the output power. Indeed, in a typical peak
current mode control, a high output power results in a high
feedback voltage, and a low output power leads to a low
regulation voltage. Hence, according to VFB, the value in the
up/down counter is changed to vary the power MOSFET offtime according to the output power. In the following, the
variation of the up/down counter value according to the
feedback voltage is explained.
The feedback voltage VFB is internally compared with three
threshold voltages VFBZL, VFBZH and VFBR1, at each clock
period of 48ms. The up/down counter counts then upward,
keep unchanged or count downward, as shown in Table 1.
clock
T=48ms
t
VFB
VFBR1
VFBZH
VFBZL
Operation of the up/down counter
n+2
n+2
n+2
n+1
n
n-1
vFB
up/down counter
action
n+2
t
n+1
Up/down
counter
n
Table 1
VFBZH, are changed internally depending on the line voltage
levels.
Case 1
4
5
6
6
6
6
5
4
3 1
Always lower than VFBZL
Count upwards till 7
Case 2
2
3
4
4
4
4
3
2
1 1
Case 3
7
7
7
7
7
7
6
5
4 1
Once higher than VFBZL, but
always lower than VFBZH
Stop counting, no
value changing
Once higher than VFBZH, but
always lower than VFBR1
Count downwards
till 1
Once higher than VFBR1
Figure 5
Up/down counter operation
3.3.1.2
Zero crossing (ZC counter)
In the system, the voltage from the auxiliary winding is
applied to the zero-crossing pin through a RC network,
which provides a time delay to the voltage from the auxiliary
winding. Internally, this pin is connected to a clamping
network, a zero-crossing detector, an output overvoltage
detector and a ringing suppression time controller.
During on-state of the power switch a negative voltage
applies to the ZC pin. Through the internal clamping
network, the voltage at the pin is clamped to certain level.
The ZC counter has a minimum value of 0 and maximum
value of 7. After the internal MOSFET is turned off, every
time when the falling voltage ramp of on ZC pin crosses the
100mV threshold, a zero crossing is detected and ZC counter
will increase by 1. It is reset every time after the DRIVER
output is changed to high.
The voltage vZC is also used for the output overvoltage
detection. Once the voltage at this pin is higher than the
threshold VZCOVP during off-time of the main switch, the IC
is latched off after a fixed blanking time.
To achieve the switch-on at voltage valley, the voltage from
the auxiliary winding is fed to a time delay network (the RC
network consists of Dzc, Rzc1, Rzc2 and Czc as shown in typical
application circuit) before it is applied to the zero-crossing
detector through the ZC pin. The needed time delay to the
main oscillation signal Dt should be approximately one
fourth of the oscillation period (by transformer primary
inductance and drain-source capacitance) minus the
propagation delay from the detected zero-crossing to the
switch-on of the main switch tdelay, theoretically:
Set up/down counter
to 1
In the ICE2QR4765G, the number of zero crossing is limited
to 7. Therefore, the counter varies between 1 and 7, and any
attempt beyond this range is ignored. When VFB exceeds
VFBR1 voltage, the up/down counter is reset to 1, in order to
allow the system to react rapidly to a sudden load increase.
The up/down counter value is also reset to 1 at the start-up
time, to ensure an efficient maximum load start up. Figure 5
shows some examples on how up/down counter is changed
according to the feedback voltage over time.
The use of two different thresholds VFBZL and VFBZH to count
upward or downward is to prevent frequency jittering when
the feedback voltage is close to the threshold point.
However, for a stable operation, these two thresholds must
not be affected by the foldback current limitation (see
Section 3.4.1), which limits the VCS voltage. Hence, to
prevent such situation, the threshold voltages, VFBZL and
T
osc
Δt = ------------ – t delay
4
Version 2.0
1
8
[2]
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Functional Description
This time delay should be matched by adjusting the time
constant of the RC network which is calculated as:
to prevent the switching frequency from going too low
because of long on time.
R zc1 ⋅ R zc2
τ td = C zc ⋅ --------------------------------R zc1 + R zc2
3.4
[3]
There is a cycle by cycle current limitation realized by the
current limit comparator to provide an overcurrent detection.
The source current of the MOSFET is sensed via a sense
resistor RCS. By means of RCS the source current is
transformed to a sense voltage VCS which is fed into the pin
CS. If the voltage VCS exceeds an internal voltage limit,
adjusted according to the Mains voltage, the comparator
immediately turns off the gate drive.
To prevent the Current Limitation process from distortions
caused by leading edge spikes, a Leading Edge Blanking
time (tLEB) is integrated in the current sensing path.
A further comparator is implemented to detect dangerous
current levels (VCSSW) which could occur if one or more
transformer windings are shorted or if the secondary diode is
shorted. To avoid an accidental latch off, a spike blanking
time of tCSSW is integrated in the output path of the
comparator.
3.3.1.3
Ringing suppression time
After MOSFET is turned off, there will be some oscillation
on VDS, which will also appear on the voltage on ZC pin. To
avoid mistriggering by such oscillations to turn on the
MOSFET, a ringing suppression timer is implemented. This
suppresion time is depended on the voltage vZC. If the
voltage vZC is lower than the threshold VZCRS, a longer preset
time is applied. However, if the voltage vZC is higher than the
threshold, a shorter time is set.
3.3.1.4
Switch on determination
After the gate drive goes to low, it can not be changed to high
during ring suppression time.
After ring suppression time, the gate drive can be turned on
when the ZC counter value is higher or equal to up/down
counter value.
However, it is also possible that the oscillation between
primary inductor and drain-source capacitor damps very fast
and IC can not detect enough zero crossings and ZC counter
value will not be high enough to turn on the gate drive. In this
case, a maximum off time is implemented. After gate drive
has been remained off for the period of TOffMax, the gate drive
will be turned on again regardless of the counter values and
VZC. This function can effectively prevent the switching
frequency from going lower than 20kHz. Otherwise it will
cause audible noise, during start up.
3.4.1
Foldback Point Correction
When the main bus voltage increases, the switch on time
becomes shorter and therefore the operating frequency is
also increased. As a result, for a constant primary current
limit, the maximum possible output power is increased
which is beyond the converter design limit.
To avoid such a situation, the internal foldback point
correction circuit varies the VCS voltage limit according to
the bus voltage. This means the VCS will be decreased when
the bus voltage increases. To keep a constant maximum
input power of the converter, the required maximum VCS
versus various input bus voltage can be calculated, which is
shown in Figure 6.
3.3.2
Switch Off Determination
In the converter system, the primary current is sensed by an
external shunt resistor, which is connected between low-side
terminal of the main power switch and the common ground.
The sensed voltage across the shunt resistor vCS is applied to
an internal current measurement unit, and its output voltage
V1 is compared with the regulation voltage VFB. Once the
voltage V1 exceeds the voltage VFB, the output flip-flop is
reset. As a result, the main power switch is switched off. The
relationship between the V1 and the VCS is described by:
V 1 = 3.3 ⋅ V cs + 0.7
1
Vcs-max(V)
0.9
0.8
0.7
[4]
0.6
To avoid mistriggering caused by the voltage spike across
the shunt resistor at the turn on of the main power switch, a
leading edge blanking time, tLEB, is applied to the output of
the comparator. In other words, once the gate drive is turned
on, the minimum on time of the gate drive is the leading edge
blanking time.
In addition, there is a maximum on time, tOnMax, limitation
implemented in the IC. Once the gate drive has been in high
state longer than the maximum on time, it will be turned off
Version 2.0
Current Limitation
80
100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400
Vin(V)
Figure 6
Variation of the VCS limit voltage according to
the IZC current
According to the typical application circuit, when MOSFET
is turned on, a negative voltage proportional to bus voltage
will be coupled to auxiliary winding. Inside CoolSET® - Q1,
an internal circuit will clamp the voltage on ZC pin to nearly
9
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Functional Description
section. One comparator observes the feedback signal if the
voltage level VBH (3.6V) is exceeded. In that case the
internal circuit is again activated by the internal bias to start
with switching.
Turn-on of the power MOSFET is triggered by the timer.
The PWM generator for Active Burst Mode operation
composes of a timer with a fixed frequency of 52kHz,
typically, and an analog comparator. Turn-off is resulted by
comparison of the voltage signal v1 with an internal
threshold, by which the voltage across the shunt resistor VcsB
is 0.34V, accordingly. A turn-off can also be triggered by the
maximal duty ratio controller which sets the maximal duty
ratio to 50%. In operation, the output flip-flop will be reset
by one of these signals which comes first.
If the output load is still low, the feedback signal decreases
as the PWM section is operating. When feedback signal
reaches the low threshold VBL(3.0V), the internal bias is
reset again and the PWM section is disabled until the next
regulation signal increases beyond the VBH threshold. In
Active Burst Mode, the feedback signal is changing like a
saw tooth between 3.0V and 3.6V shown in Figure 8.
0V. As a result, the current flowing out from ZC pin can be
calculated as
V BUS N a
I ZC = -----------------------R ZC1 N P
[5]
When this current is higher than IZC_1, the amount of current
exceeding this threshold is used to generate an offset to
decrease the maximum limit on VCS. Since the ideal curve
shown in Figure 6 is a nonlinear one, a digital block in
CoolSET® - Q1 is implemented to get a better control of
maximum output power. Additional advantage to use digital
circuit is the production tolerance is smaller compared to
analog solutions. The typical maximum limit on VCS versus
the ZC current is shown in Figure 7.
1
Vcs-max(V)
0.9
0.8
3.5.3
Leaving Active Burst Mode Operation
The feedback voltage immediately increases if there is a high
load jump. This is observed by one comparator. As the
current limit is 34% during Active Burst Mode a certain load
is needed so that feedback voltage can exceed VLB (4.5V).
After leaving active burst mode, maximum current can now
be provided to stabilize VO. In addition, the up/down counter
will be set to 1 iimmediately after leaving Active Burst
0.7
0.6
300
500
700
900
1100
1300
1500
1700
1900
2100
Iz c(uA)
VCS-max versus IZC
Figure 7
3.5
Active Burst Mode Operation
At light load condition, the IC enters Active Burst Mode
operation to minimize the power consumption. Details about
Active Burst Mode operation are explained in the following
paragraphs.
3.5.1
Entering Active Burst Mode Operation
For determination of entering Active Burst Mode operation,
three conditions apply:
• the feedback voltage is lower than the threshold of
VFBEB(1.25V). Accordingly, the peak current sense
voltage across the shunt resistor is 0.17V;
• the up/down counter is 7; and
• a certain blanking time (tBEB).
Once all of these conditions are fulfilled, the Active Burst
Mode flip-flop is set and the controller enters Active Burst
Mode operation. This multi-condition determination for
entering Active Burst Mode operation prevents
mistriggering of entering Active Burst Mode operation, so
that the controller enters Active Burst Mode operation only
when the output power is really low during the preset
blanking time.
3.5.2
During Active Burst Mode Operation
After entering the Active Burst Mode the feedback voltage
rises as VOUT starts to decrease due to the inactive PWM
Version 2.0
10
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Functional Description
reset and the main power switch is then kept off. After the
VCC voltage falls below the threshold VVCCoff, the startup
cell is activated. The VCC capacitor is then charged up.
Once the voltage exceeds the threshold VVCCon, the IC begins
to operate with a new soft-start.
In case of open control loop or output over load, the feedback
voltage will be pulled up. After a blanking time of 24ms, the
IC enters auto-restart mode. The blanking time here enables
the converter to provide a max. power in case the increase in
VFB is due to a sudden load increase. During off-time of the
power switch, the voltage at the zero-crossing pin is
monitored for output over-voltage detection. If the voltage is
higher than the preset threshold vZCOVP, the IC is latched off
after the preset blanking time. This latch off mode can only
be reset if the Vcc <6.23V.
If the junction temperature of IC exceeds 140 °C, the IC
enters into autorestart mode (OTP).
If the voltage at the current sensing pin is higher than the
preset threshold vCSSW during on-time of the power switch,
the IC is latched off. This is short-winding protection.
During latch-off protection mode, the VCC voltage drops to
10.5V and then the startup cell is activated. The VCC voltage
is then charged to 18V. The startup cell is shut down again.
This action repeats again and again.
There is also a maximum on time limitation implemented
inside the ICE2QR4765G. Once the gate voltage is high and
longer than tOnMAx, the switch is turned off immediately.
Mode. This is helpful to decrease the output voltage
undershoot.
VFB
Entering
Active Burst
Mode
VFBLB
VFBBOn
VFBBOff
Leaving
Active Burst
Mode
VFBEB
time to 7th zero and
blanking Window (tBEB)
VCS
1.0V
t
Current limit level
during Active Burst
Mode
VCSB
VVCC
t
VVCCoff
VO
t
Max. Ripple < 1%
t
Figure 8
3.6
Signals in Active Burst Mode
Protection Functions
The IC provides full protection functions. The following
table summarizes these protection functions.
Table 2
Protection features
VCC Overvoltage
Auto Restart Mode
VCC Undervoltage
Auto Restart Mode
Overload/Open Loop
Auto Restart Mode
Over temperature
Auto Restart Mode
Output Overvoltage
Latched Off Mode
Short Winding
Latched Off Mode
During operation, the VCC voltage is continuously
monitored. In case of an under- or an over-voltage, the IC is
Version 2.0
11
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Electrical Characteristics
4
Electrical Characteristics
Note:
All voltages are measured with respect to ground (Pin 12). The voltage levels are valid if other ratings are not
violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the
integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 11 (VCC) is
discharged before assembling the application circuit.Ta=25°C unless otherwise specified.
Parameter
Symbol
Limit Values
Unit
Remarks
Tj=110°C
min.
max.
-
650
V
Switching drain current, pulse width tp limited Is
by Tjmax
-
1.67
A
Pulse drain current, pulse width tp limited by
Tjmax
ID_Puls
-
2.32
A
Avalanche energy, repetitive tAR limited by
max. Tj=150°C1)
EAR
-
0.01
mJ
Avalanche current, repetitive tAR limited by
max. Tj=150°C
IAR
-
0.5
A
VCC Supply Voltage
VVCC
-0.3
27
V
FB Voltage
VFB
-0.3
5.5
V
ZC Voltage
VZC
-0.3
5.5
V
CS Voltage
VCS
-0.3
5.5
V
Maximum current out from ZC pin
IZCMAX
3
-
mA
Junction Temperature
Tj
-40
150
°C
Storage Temperature
TS
-55
150
°C
Thermal Resistance
Junction -Ambient
RthJA
-
110
K/W
ESD Capability (incl. Drain Pin)
VESD
-
2
kV
Drain Source Voltage
VDS
Controller & CoolMOS®
Human body model2)
1)
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f
2)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description.
Parameter
VCC Supply Voltage
Version 2.0
Symbol
VVCC
Limit Values
Unit
min.
max.
VVCCoff
VVCCOVP V
12
Remarks
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Electrical Characteristics
Junction Temperature of Controller TjCon
-25
130
°C
Junction Temperature of
CoolMOS®
-25
150
°C
4.3
4.3.1
Note:
TjCoolMOS
Max. value is limited by over
temperature protection of the
controller
Characteristics
Supply Section
The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range TJ from – 25 °C to 125 °C. Typical values represent the median values, which are related to
25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Start Up Current
IVCCstart
-
300
550
mA
VVCC =VVCCon -0.2V
VCC Charge Current
IVCCcharge1
-
5.0
-
mA
VVCC = 0V
IVCCcharge2
0.8
-
-
mA
VVCC = 1V
IVCCcharge3
-
1
-
mA
VVCC =VVCCon -0.2V
Maximum Input Current of
Startup Cell and CoolMOS®
IDrainIn
-
-
2
mA
VVCC =VVCCon -0.2V
Leakage Current of
Startup Cell and CoolMOS®
IDrainLeak
-
0.2
50
mA
VDrain = 610V
at Tj=100°C
Supply Current in normal operation
IVCCNM
-
1.5
2.3
mA
output low
Supply Current in
IVCCAR
Auto Restart Mode with Inactive Gate
-
300
-
mA
IFB = 0A
Supply Current in Latch-off Mode
IVCClatch
-
300
-
mA
Supply Current in Burst Mode with
inactive Gate
IVCCburst
-
500
950
mA
VCC Turn-On Threshold
VVCCon
17.0
18.0
19.0
V
VCC Turn-Off Threshold
VVCCoff
9.8
10.5
11.2
V
VCC Turn-On/Off Hysteresis
VVCChys
-
7.5
-
V
4.3.2
VFB = 2.5V, exclude the
current flowing out from
FB pin
Internal Voltage Reference
Parameter
Internal Reference Voltage
Version 2.0
Symbol
VREF
Limit Values
min.
typ.
max.
4.80
5.00
5.20
13
Unit
Test Condition
V
Measured at pin FB IFB=0
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Electrical Characteristics
4.3.3
PWM Section
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Feedback Pull-Up Resistor
RFB
14
23
33
kΩ
PWM-OP Gain
GPWM
3.18
3.3
-
-
Offset for Voltage Ramp
VPWM
0.6
0.7
-
V
Maximum on time in normal
operation
tOnMax
22
30
41
ms
4.3.4
Current Sense
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Peak current limitation in normal
operation
VCSth
0.97
1.03
1.09
V
Leading Edge Blanking time
tLEB
200
330
460
ns
Peak Current Limitation in Active
Burst Mode
VCSB
0.29
0.34
0.39
V
4.3.5
Test Condition
Soft Start
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Soft-Start time
tSS
8.5
12
-
ms
soft-start time step
tSS_S1)
-
3
-
ms
Internal regulation voltage at first
step
VSS11)
-
1.76
-
V
Internal regulation voltage step at
soft start
VSS_S1)
-
0.56
-
V
1)
Test Condition
Test Condition
The parameter is not subjected to production test - verified by design/characterization
4.3.6
Foldback Point Correction
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
ZC current first step threshold
IZC_FS
0.350
0.5
0.621
mA
ZC current last step threshold
IZC_LS
1.3
1.7
2.2
mA
CS threshold minimum
VCSMF
-
0.66
-
V
Version 2.0
14
Test Condition
Izc=2.2mA, VFB=3.8V
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Electrical Characteristics
4.3.7
Digital Zero Crossing
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Zero crossing threshold voltage
VZCCT
50
100
170
mV
Ringing suppression threshold
VZCRS
-
0.7
-
V
Minimum ringing suppression time tZCRS1
1.62
2.5
4.5
μs
VZC > VZCRS
Maximum ringing suppression
time
tZCRS2
-
25
-
μs
VZC < VZCRS
Threshold to set Up/Down Counter
to one
VFBR1
-
3.9
-
V
Threshold for downward counting
at low line
VFBZHL
-
3.2
-
V
Threshold for upward counting at
low line
VFBZLL
-
2.5
-
V
Threshold for downward counting
at hig line
VFBZHH
-
2.9
-
V
Threshold for upward counting at
highline
VFBZLH
-
2.3
-
V
ZC current for IC switch threshold
to high line
IZCSH
-
1.3
-
mA
ZC current for IC switch threshold
to low line
IZCSL
-
0.8
-
mA
Counter time1)
tCOUNT
-
48
-
ms
Maximum restart time in normal
operation
tOffMax
30
42
57.5
μs
1)
The parameter is not subjected to production test - verified by design/characterization
4.3.8
Active Burst Mode
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Feedback voltage for entering
Active Burst Mode
VFBEB
-
1.25
-
Minimum Up/down value for
entering Active Burst Mode
NZC_ABM
-
7
-
Blanking time for entering Active
Burst Mode
tBEB
-
24
-
ms
Feedback voltage for leaving
Active Burst Mode
VFBLB
-
4.5
-
V
Feedback voltage for burst-on
VFBBOn
-
3.6
-
V
Feedback voltage for burst-off
VFBBOff
-
3.0
-
V
Version 2.0
15
Test Condition
V
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Electrical Characteristics
Fixed Switching Frequency in
Active Burst Mode
fsB
39
52
65
Max. Duty Cycle in Active Burst
Mode
DmaxB
-
0.5
-
4.3.9
kHz
Protection
Parameter
Symbol
Limit Values
Unit
min.
typ.
max.
VCC overvoltage threshold
VVCCOVP
24.0
25.0
26.0
V
Over Load or Open Loop Detection
threshold for OLP protection at FB
pin
VFBOLP
-
4.5
-
V
Over Load or Open Loop
Protection Blanking Time
tOLP_B
20
30
44
ms
Output Overvoltage detection
threshold at the ZC pin
VZCOVP
3.55
3.7
3.84
V
Blanking time for Output
Overvoltage protection
tZCOVP
-
100
-
μs
Threshold for short winding
protection
VCSSW
1.63
1.68
1.78
V
Blanking time for short-windding
protection
tCSSW
-
190
-
ns
Over temperature protection1)
TjCon
130
140
150
°C
Note:
Test Condition
The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP
4.3.10
CoolMOS® Section
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Drain Source Breakdown Voltage
V(BR)DSS
650
-
-
V
Tj = 110°C
Drain Source On-Resistance
RDSon
-
4.70
10.0
5.44
12.5
Ω
Ω
Tj = 25°C
Tj=125°C1)
at ID = 0.5A
Effective output capacitance, energy
related
Co(er)
-
4.751)
-
pF
VDS = 0V to 480V
Rise Time
trise
-
302)
-
ns
Fall Time
tfall
-
302)
-
ns
1)
The parameter is not subjected to production test - verified by design/characterization
2)
Measured in a Typical Flyback Converter Application
Version 2.0
16
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Typical CoolMOS® Performance Characteristic
5
Typical CoolMOS® Performance Characteristic
Safe Operating Area for ICE2QR4765G
ID = f ( V DS )
parameter : D = 0, TC = 25deg.C
10
ID [A]
1
0.1
tp =
tp =
tp =
tp =
DC
0.01
0.1ms
1ms
10ms
100ms
0.001
1
10
100
1000
V DS [V]
Figure 9
Safe Operating Area(SOA) curve for ICE2QR4765G
Allowable Power Dissipation for Quasi CoolSET in DSO-16/12 package
1.2
Allowable Power Dissipation, Ptot [W]
1.0
0.8
0.6
0.4
0.2
0.0
0
20
40
60
80
100
120
140
Ambient temperature, T A [deg.C]
Figure 10
Version 2.0
Power dissipation; Ptot=f(Ta)
17
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Typical CoolMOS® Performance Characteristic
700
V BR(DSS) [V]
660
620
580
540
-60
Figure 11
Version 2.0
-20
20
60
T j [°C]
100
140
180
Drain-source breakdown voltage; VBR(DSS)=f(Tj)
18
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Input power curve
6
Input power curve
Two input power curves gives typical input power versus ambient temperature are showed below;
Vin=85~265Vac(Figure 12) and Vin=230Vac(Figure 13). The curves are derived based on a typical discontinuous mode
flyback model which considers 115V maximum secondary to primary reflected voltage(high priority). The calculation is
based on no copper area as heatsink for the device. The input power already includes power loss at input comman mode choke
and bridge rectifier and the CoolMOS®. The device saturation current(ID_plus@Tj=125 °C) is also considered.
To estimate the out power of the device, it is simply multiplying the input power at a particulary ambient temperature with
the estimated efficiency for the application. For example, a wide range input voltage(Figure 12), operating temperature is 50
°C, estimated efficiency is 85%,the output power is 14.45W(17W*0.85).
Input Power curve of ICE2QR4765
Input Power(85Vac~265Vac)[W]
25
20
15
10
5
0
0
25
35
45
55
65
75
85
95
105
115
125
95
105
115
125
Ambient Temperature[0C]
Figure 12
Input Power curve Vin=85~265Vac;Pin=f(Ta)
Input Power curve of ICE2QR4765
40
Input Power(230Vac)[W]
35
30
25
20
15
10
5
0
0
25
35
45
55
65
75
85
Ambient Temperature[0C]
Figure 13
Version 2.0
Input Power curve Vin=230Vac;Pin=f(Ta)
19
July 26, 2011
CoolSET® - Q1
ICE2QR4765G
Outline Dimension
7
Outline Dimension
PG-DSO-16/12
(Plastic Dual Small Outline)
Figure 14
PG-DSO-16/12 (Pb-free lead plating Plastic Dual Small Outline Package)
Dimensions in mm
Version 2.0
20
July 26, 2011
Total Quality Management
Qualität hat für uns eine umfassende
Bedeutung. Wir wollen allen Ihren
Ansprüchen in der bestmöglichen Weise
gerecht werden. Es geht uns also nicht nur
um die Produktqualität – unsere
Anstrengungen gelten gleichermaßen der
Lieferqualität und Logistik, dem Service
und Support sowie allen sonstigen
Beratungs- und Betreuungsleistungen.
Dazu gehört eine bestimmte Geisteshaltung
unserer Mitarbeiter. Total Quality im
Denken und Handeln gegenüber Kollegen,
Lieferanten und Ihnen, unserem Kunden.
Unsere Leitlinie ist jede Aufgabe mit „Null
Fehlern“ zu lösen – in offener Sichtweise
auch über den eigenen Arbeitsplatz hinaus –
und uns ständig zu verbessern.
Unternehmensweit orientieren wir uns
dabei auch an „top“ (Time Optimized
Processes), um Ihnen durch größere
Schnelligkeit den entscheidenden
Wettbewerbsvorsprung zu verschaffen.
Geben Sie uns die Chance, hohe Leistung
durch umfassende Qualität zu beweisen.
Wir werden Sie überzeugen.
Quality takes on an allencompassing
significance at Semiconductor Group. For
us it means living up to each and every one
of your demands in the best possible way.
So we are not only concerned with product
http://www.infineon.com
Published by Infineon Technologies AG
quality. We direct our efforts equally at
quality of supply and logistics, service and
support, as well as all the other ways in
which we advise and attend to you.
Part of this is the very special attitude of our
staff. Total Quality in thought and deed,
towards co-workers, suppliers and you, our
customer. Our guideline is “do everything
with zero defects”, in an open manner that is
demonstrated beyond your immediate
workplace, and to constantly improve.
Throughout the corporation we also think in
terms of Time Optimized Processes (top),
greater speed on our part to give you that
decisive competitive edge.
Give us the chance to prove the best of
performance through the best of quality –
you will be convinced.