CY7C1041CV33 4-Mbit (256 K × 16) Static RAM 4-Mbit (256 K × 16) Static RAM Features Functional Description ■ Temperature ranges ❐ Commercial: 0 °C to 70°C The CY7C1041CV33 is a high performance CMOS static RAM organized as 262,144 words by 16 bits. ■ Pin and function compatible with CY7C1041BV33 ■ High speed ❐ tAA = 8 ns ■ Low active power ❐ 360 mW (max) To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (/IO0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). ■ 2.0 V data retention ■ Automatic power down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 44-pin TSOP II package To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. For more information, see the Truth Table on page 10 for a complete description of Read and Write modes. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER 256K x 16 RAM Array I/O0–I/O7 I/O8–I/O15 • BHE WE CE OE BLE A16 A17 A14 A15 A13 A12 A9 Cypress Semiconductor Corporation Document Number: 38-05134 Rev. *L A10 A11 COLUMN DECODER 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 4, 2011 [+] Feedback CY7C1041CV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 10 Document Number: 38-05134 Rev. *L Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagram ............................................................ 12 Acronyms ....................................................................... 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15 Page 2 of 15 [+] Feedback CY7C1041CV33 Selection Guide Description -8 Maximum Access Time Unit 8 ns Maximum Operating Current 100 mA Maximum CMOS Standby Current 10 mA Pin Configuration Figure 1. 44-pin TSOP II (Top View) [1] A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 IO5 IO6 IO7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 IO10 IO9 IO8 NC A14 A13 A12 A11 A10 Note 1. NC pins are not connected on the die. Document Number: 38-05134 Rev. *L Page 3 of 15 [+] Feedback CY7C1041CV33 Pin Definitions Pin Name TSOP Pin Number I/O Type A0–A17 1–5, 18–27, 42–44 Input Description Address Inputs. Used to select one of the address locations. I/O0–I/O15 7–10,13–16, Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation. 29–32, 35–38 NC 28 No Connect No Connects. Not connected to the die. WE 17 Input or Control Write Enable Input, Active LOW. When selected LOW, a write is conducted. When deselected HIGH, a read is conducted. CE 6 Input or Control Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. BHE, BLE 40, 39 Input or Control Byte Write Select Inputs, Active LOW. BHE controls I/O15 – I/O8, BLE controls I/O7 – I/O0. OE 41 Input or Control Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, the I/O pins are tri-stated and act as input data pins. VSS 12, 34 Ground Ground for the Device. Connected to ground of the system. VCC 11, 33 Power Supply Power Supply Inputs to the Device. Document Number: 38-05134 Rev. *L Page 4 of 15 [+] Feedback CY7C1041CV33 DC Input Voltage[2] ............................... –0.5 V to VCC + 0.5V Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied .......................................... –55 C to +125 C Static Discharge Voltage.......................................... > 2001 V (MIL-STD-883, Method 3015) Latch Up Current .................................................... > 200 mA Operating Range Supply Voltage on VCC Relative to GND[2] ...–0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State[2] .................................. –0.5 V to VCC + 0.5 V Range Commercial Ambient Temperature (TA) VCC 0 C to +70 C 3.3 V 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions -8 Min Max Unit VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH VIL [2] IIX Input Leakage Current GND < VI < VCC –1 +1 A IOZ Output Leakage Current GND < VOUT < VCC, Output disabled –1 +1 A ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC – 100 mA ISB1 Automatic CE Power Down Current —TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 40 mA ISB2 Automatic CE Power Down Current — CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 10 mA 2.4 – V – 0.4 V Input HIGH Voltage 2.0 VCC + 0.3 V Input LOW Voltage –0.3 0.8 V Note 2. VIL (min) = –2.0 V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns. Document Number: 38-05134 Rev. *L Page 5 of 15 [+] Feedback CY7C1041CV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max Unit 8 pF 8 pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Test Conditions TSOP II Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 42.96 C/W 10.75 C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [3] 10-ns devices: 12-, 15-, 20-ns devices: Z = 50 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R 317 3.3V OUTPUT 30 pF* OUTPUT R2 351 30 pF* 1.5 V (b) (a) High Z characteristics: 3.0 V GND ALL INPUT PULSES 90% 90% 10% 10% Rise Time: 1 V/ns (c) R 317 3.3 V Fall Time: 1 V/ns OUTPUT R2 351 5 pF (d) Note 3. AC characteristics (except High Z) for 10-ns parts are tested using the load conditions shown in Figure 2 (a). All other speeds are tested using the Thevenin load shown in Figure 2 (b). High Z characteristics are tested for all speeds using the test load shown in Figure 2 (d). Document Number: 38-05134 Rev. *L Page 6 of 15 [+] Feedback CY7C1041CV33 Switching Characteristics Over the Operating Range [4] Parameter Description -8 Unit Min Max 100 – s Read Cycle tpower[5] VCC(Typical) to the First Access tRC Read Cycle Time 8 – ns tAA Address to Data Valid – 8 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 8 ns tDOE OE LOW to Data Valid – 5 ns 0 – ns – 4 ns 3 – ns – 4 ns Z[6] tLZOE OE LOW to Low tHZOE OE HIGH to High Z[6, 7] tLZCE CE LOW to Low Z[6] tHZCE CE HIGH to High Z[6, 7] tPU CE LOW to Power Up 0 – ns tPD CE HIGH to Power Down – 8 ns tDBE Byte Enable to Data Valid – 5 ns tLZBE Byte Enable to Low Z 0 – ns tHZBE Byte Disable to High Z – 5 ns tWC Write Cycle Time 8 – ns tSCE CE LOW to Write End 6 – ns tAW Address Setup to Write End 6 – ns tHA Address Hold from Write End 0 – ns tSA Address Setup to Write Start 0 – ns tPWE WE Pulse Width 6 – ns tSD Data Setup to Write End 4 – ns tHD Data Hold from Write End 0 – ns tLZWE WE HIGH to Low Z[6] 3 – ns – 4 ns 6 – ns Write Cycle[8, 9] Z[6, 7] tHZWE WE LOW to High tBW Byte Enable to End of Write Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 7. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 2 on page 6. Transition is measured 500 mV from steady state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05134 Rev. *L Page 7 of 15 [+] Feedback CY7C1041CV33 Switching Waveforms Figure 3. Read Cycle No. 1 (Address Transition Controlled)[10, 11] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE BHE, BLE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Notes 10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05134 Rev. *L Page 8 of 15 [+] Feedback CY7C1041CV33 Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (CE Controlled)[13, 14] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE t BW BHE, BLE tSD tHD DATA IO Figure 6. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA IO Notes 13. Data IO is high impedance if OE, BHE, and/or BLE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05134 Rev. *L Page 9 of 15 [+] Feedback CY7C1041CV33 Switching Waveforms (continued) Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA IO tLZWE Truth Table CE OE WE BLE BHE H X X X X High Z High Z Power Down Standby (ISB) L L H L L Data Out Data Out Read – All Bits Active (ICC) L X L I/O0 – I/O7 I/O8 – I/O15 Mode Power L H Data Out High Z Read – Lower Bits Only Active (ICC) H L High Z Data Out Read – Upper Bits Only Active (ICC) L L Data In Data In Write – All Bits Active (ICC) L H Data In High Z Write – Lower Bits Only Active (ICC) H L High Z Data In Write – Upper Bits Only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document Number: 38-05134 Rev. *L Page 10 of 15 [+] Feedback CY7C1041CV33 Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 8 Ordering Code CY7C1041CV33-8ZSXC Package Diagram Package Type 51-85087 44-pin Thin Small Outline Package Type II (Pb-free) Operating Range Commercial Please contact your local Cypress sales representative for availability of these parts Ordering Code Definitions CY 7C 1 04 1 C V33 - 8 ZS X C Temperature Range: C= Commercial X = Pb-free; X Absent = Leaded Package Type: ZS = 44-pin TSOP II Speed Grade: 8 ns V33 = 3.0 V to 3.6 V Process Technology:C 150 nm Data width: × 16-bits 4-Mbit density Fast Asynchronous SRAM Marketing Code: 7C = SRAMs Company ID: CY = Cypress Document Number: 38-05134 Rev. *L Page 11 of 15 [+] Feedback CY7C1041CV33 Package Diagram Figure 8. 44-pin Thin Small Outline Package Type II, 51-85087 51-85087 *C Document Number: 38-05134 Rev. *L Page 12 of 15 [+] Feedback CY7C1041CV33 Acronyms Document Conventions Acronym Description Units of Measure CE Chip Enable CMOS complementary metal oxide semiconductor ohms FBGA fine-pitch ball grid array ns nano seconds I/O input/output V Volts OE Output Enable µs micro seconds SOJ Small Outline J-lead µA micro Amperes SRAM static random access memory mA milli Amperes TSOP thin small outline package mm milli meter TTL transistor-transistor logic ms milli seconds WE Write Enable MHz Mega Hertz pF pico Farad % percent mW milli Watts W Watts °C degree Celcius Document Number: 38-05134 Rev. *L Symbol Unit of Measure Page 13 of 15 [+] Feedback CY7C1041CV33 Document History Page Document Title: CY7C1041CV33, 4-Mbit (256 K × 16) Static RAM Document Number: 38-05134 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109513 12/13/01 HGK New Data Sheet *A 112440 12/20/01 BSS Updated 51-85106 from revision *A to *C *B 112859 03/25/02 DFP Added CY7C1042CV33 in BGA package Removed 1042 BGA option pin ACC Final Data Sheet *C 116477 09/16/02 CEA Add applications foot note to data sheet *D 119797 10/21/02 DFP Added 20-ns speed bin *E 262949 See ECN RKF 1) Added Lead (Pb)-Free parts in the Ordering info (Page #9) 2) Added Automotive Specs to Datasheet *F 361795 See ECN SYT Added Pb-Free offerings in the Ordering Information *G 435387 See ECN NXR Removed -8 Speed bin from Product offering. Corrected typo in description for BHE/BLE in pin definitions table on Page# 3 corrected their Pin name from OE2 to OE. Included the Maximum Ratings for Static Discharge Voltage and Latch up Current. Changed the description of IIX current from Input Load Current to Input Leakage Current Added note# 4 on page# 4 Updated the Ordering Information table *H 499153 See ECN NXR Added Automotive-A Operating Range Changed tpower value from 1 s to 100 s Updated Ordering Information table *I 2104110 See ECN VKN/AESA Added Automotive-E specs for 12 ns speed Updated Ordering Information table AJU/VIVG Removed inactive parts. Updated package diagrams. *J 2897141 03/22/10 *K 3072834 11/12/2010 PRAS Removed inactive parts. Added Ordering Code Definitions on page 11. *L 3186840 03/03/2011 PRAS Updated Features. Updated Selection Guide (Added -8 ns speed grade devices and removed -10 ns, -12 ns, -15 ns and -20 ns speed grade devices). Removed Figure “48-Ball FBGA Pinout (Top View)” and renamed Figure “44-Pin SOJ/TSOP II (Top View)” as “44-pin TSOP II (Top View)” in Pin Configuration. Updated Pin Definitions (Deleted the column “BGA Pin Number” and renamed the column “SOJ, TSOP Pin Number” as “TSOP Pin Number”. Updated Operating Range Updated Electrical Characteristics (Added -8 ns speed grade devices and removed -10 ns, -12 ns, -15 ns and -20 ns speed grade devices). Updated Thermal Resistance (Deleted the columns SOJ and FBGA). Updated Switching Characteristics (Added -8 ns speed grade devices and removed -10 ns, -12 ns, -15 ns and -20 ns speed grade devices). Updated Ordering Information (Added new speed bin (-8 ns speed grade devices) and removed -10 ns, -12 ns, -15 ns and -20 ns speed grade devices). Added Acronyms and Units of Measure. Dislodged Automotive information to new datasheet (001-67307) Removed SOJ and FBGA package related information in all instances in the document. Updated in new template. Document Number: 38-05134 Rev. *L Page 14 of 15 [+] Feedback CY7C1041CV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. 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Document Number: 38-05134 Rev. *L Revised March 4, 2011 Page 15 of 15 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback