CY2314ANZ 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Features Functional Description ■ One input to 14 output buffer or driver ■ Supports up to three SDRAM DIMMs ■ Two additional outputs for feedback ■ Serial interface for output control The CY2314ANZ is a 3.3V buffer designed to distribute high speed clocks in desktop PC applications. The part has 14 outputs, 12 of which can be used to drive up to three SDRAM DIMMs. The remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz. ■ Low skew outputs ■ Up to 100 MHz operation ■ Multiple VDD and VSS pins for noise reduction ■ Dedicated OE pin for testing ■ Low EMI outputs ■ 28-pin SOIC (300-mil) package ■ 3.3V operation The CY2314ANZ also includes a serial interface which can enable or disable each output clock. On power up, all output clocks are enabled. A separate Output Enable pin facilitates testing on ATE. Logic Block Diagram BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDATA SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 Serial Interface Decoding SCLOCK OE Cypress Semiconductor Corporation Document #: 38-07143 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 10, 2008 [+] Feedback CY2314ANZ Pin Configuration Figure 1. 28-Pin SOIC Top View VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN SDRAM4 SDRAM5 SDRAM12 VDDIIC SDATA 1 2 V DD SDRAM11 SDRAM10 V SS V DD SDRAM9 SDRAM8 V SS OE SDRAM7 SDRAM6 SDRAM13 V SSIIC SCLK 28 27 3 4 26 5 6 24 7 22 8 21 9 10 20 19 11 18 12 17 13 16 14 15 25 23 Device Functionality OE SDRAM [0-13] 0 High-Z 1 1 x BUF_IN Serial Configuration Map ■ The serial bits are read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Table 2. Byte 1: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Bit Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Bit 7 27 SDRAM11 (Active/Inactive) Pin # Description ■ Reserved and unused bits should be programmed to “0” Bit 6 26 SDRAM10 (Active/Inactive) ■ Serial interface address for the CY2314ANZ is: Bit 5 23 SDRAM9 (Active/Inactive) Bit 4 22 SDRAM8 (Active/Inactive) Bit 3 -- Reserved, Drive to 0 Bit 2 -- Reserved, Drive to 0 Bit 1 19 SDRAM7 (Active/Inactive) Bit 0 18 SDRAM6 (Active/Inactive) A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 ---- Table 1. Byte 0: SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enabled Bit Pin # Description Bit 7 11 SDRAM5 (Active/Inactive) Bit 6 10 SDRAM4 (Active/Inactive) Bit 5 -- Reserved, Drive to 0 Bit 4 -- Reserved, Drive to 0 Bit 3 7 SDRAM3 (Active/Inactive) Bit 2 6 SDRAM2 (Active/Inactive) Bit 1 3 SDRAM1 (Active/Inactive) Bit 0 2 SDRAM0 (Active/Inactive) Document #: 38-07143 Rev. *B Table 3. Byte 2: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Description Bit 7 17 SDRAM13 (Active/Inactive) Bit 6 12 SDRAM12 (Active/Inactive) Bit 5 -- Reserved, Drive to 0 Bit 4 -- Reserved, Drive to 0 Bit 3 -- Reserved, Drive to 0 Bit 2 -- Reserved, Drive to 0 Bit 1 -- Reserved, Drive to 0 Bit 0 -- Reserved, Drive to 0 Page 2 of 8 [+] Feedback CY2314ANZ Maximum Ratings Supply Voltage to Ground Potential................–0.5V to +7.0V Storage Temperature ................................. –65°C to +150°C DC Input Voltage (Except BUF_IN) ....... –0.5V to VDD + 0.5V Junction Temperature................................................. 150°C DC Input Voltage (BUF_IN) ............................–0.5V to +7.0V Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions [1] Parameter Description VDD Supply Voltage Min Max Unit 3.135 3.465 V 0 TA Operating Temperature (Ambient Temperature) 70 °C CL Load Capacitance 30 pF CIN Input Capacitance 7 pF tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms Min Max Unit 0.8 V 0.7 V Electrical Characteristics Over the Operating Range Parameter Description Voltage[2] Test Conditions VIL Input LOW VILiic Input LOW Voltage VIH Input HIGH Voltage[2] IIL Input LOW Current (BUF_IN input) VIN = 0V IIL Input LOW Current (Except BUF_IN Pin) VIN = 0V IIH Input HIGH Current VIN = VDD VOL VOH Except serial interface pins For serial interface pins only 2.0 Output LOW Voltage[3] IOL = 25 mA Output HIGH Voltage[3] IOH = –36 mA Current[3] IDD Supply IDD Supply Current[3] IDD –10 –10 V 10 μA 100 μA 10 μA 0.4 V 2.4 V Unloaded outputs, 100 MHz 200 mA Loaded outputs, 100 MHz 290 mA Supply Current[3] Unloaded outputs, 66.67 MHz 150 mA IDD Supply Current[3] Loaded outputs, 66.67 MHz 185 mA IDDS Supply Current BUF_IN=VDD or VSS All other inputs at VDD 500 μA Notes 1. Electrical parameters are guaranteed under the operating conditions specified. 2. BUF_IN input has a threshold voltage of VDD/2. 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07143 Rev. *B Page 3 of 8 [+] Feedback CY2314ANZ Switching Characteristics[4] Over the Operating Range Parameter Name Test Conditions Min Typ Maximum Operating Frequency [3, 5] Duty Cycle = t2 ÷ t1 Max Unit 100 MHz Measured at 1.5V 45.0 50.0 55.0 % t3 Rising Edge Rate [3] Measured between 0.4V and 2.4V 0.9 1.5 4.0 V/ns t4 Falling Edge Rate[3] Measured between 2.4V and 0.4V 0.9 1.5 4.0 V/ns +250 ps [3] t5 Output to Output Skew t6 SDRAM Buffer LH Propogation Delay[3] Input edge greater than 1 V/ns 1.0 3.5 5.0 ns t7 SDRAM Buffer HL Propogation Delay[3] Input edge greater than 1 V/ns 1.0 3.5 5.0 ns t8 SDRAM Buffer Enable Delay[3] Input edge greater than 1 V/ns 1.0 5 12 ns t9 Delay[3] Input edge greater than 1 V/ns 1.0 20 30 ns SDRAM Buffer Disable All outputs equally loaded –250 Switching Waveforms Figure 2. Duty Cycle Timing t1 t2 1.5V 1.5V 1.5V Figure 3. All Outputs Rise/Fall Time OUTPUT 2.4V 0.4V 2.4V 0.4V t3 3.3V 0V t4 Figure 4. Output-Output Skew OUTPUT 1.5V 1.5V OUTPUT t5 Notes 4. All parameters specified with loaded outputs. 5. Duty cycle of input clock is 50%. Rising and falling edge rate of the input clock is greater than 1 V/ns. Document #: 38-07143 Rev. *B Page 4 of 8 [+] Feedback CY2314ANZ Switching Waveforms (continued) Figure 5. SDRAM Buffer LH and HL Propagataion Delay INPUT OUTPUT t6 t7 Figure 6. SDRAM Buffer Enable and Disable Times OE Three-State OUTPUTS t8 Active t9 Test Circuit VDD 0.1 μF OUTPUTS CLK out CLOAD GND Document #: 38-07143 Rev. *B Page 5 of 8 [+] Feedback CY2314ANZ Application Information Clock traces must be terminated with either series or parallel termination, as is normally done. Figure 7. Application Circuit Rs CPUCLK BUF_IN PCICLK USBCLK REF Rs SDATA SDATA SCLK SDRAM(0-13) SDRAM(0-13) SCLK V DD 3.3V APIC Ct V DD * CY2280 48 Pin SSOP (or CY2281 or CY2282) Cd 0.1uF VSS CY 2314 28 Pin SOIC * This Frequency Synthesizer is used to generate CPU, PCI, USB, REF, and APIC Clocks Cd = DECOUPLING CAPACITORS Ct = OPTIONAL EMI- REDUCING CAPACITORS Rs = SERIES TERMINATING RESISTORS Recommendation ■ Surface mount, low ESR,and ceramic capacitors must be used for filtering. Typically, these capacitors have a value of 0.1 μF. In some cases, smaller value capacitors may be required. ■ The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout ■ Footprints must be laid out for optional EMI reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. ■ A ferrite bead may be used to isolate the board VDD from the clock generator VDD island. Ensure that the ferrite bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Refer to the application note Layout and Termination Techniques for Cypress Clock Generators for more details. ■ If a ferrite bead is used, a 10 μF to 22 μF tantalum bypass capacitor should be placed close to the ferrite bead. This capacitor prevents power supply droop during current surges. Ordering Information Ordering Code Package Name Package Type Operating Range Pb-Free CY2314ANZSXC-1 SZ283 28-Pin SOIC Commercial CY2314ANZSXC-1T SZ283 28-Pin SOIC - Tape and Reel Commercial Document #: 38-07143 Rev. *B Page 6 of 8 [+] Feedback CY2314ANZ Package Diagram Figure 8. 28-Pin (300-Mil) Molded SOIC SZ283 51-85026-A Document #: 38-07143 Rev. *B Page 7 of 8 [+] Feedback CY2314ANZ Document History Page Document Title: CY2314ANZ 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Document Number: 38-07143 Rev. ECN No. Orig. of Change Submission Description of Change Date ** 110252 DSG 11/18/01 Change from Spec number: 38-00687 to 38-07143 *A 121830 RBI 12/14/02 Power up requirements added to Operating Conditions Information *B 2606695 KVM/PYRS 11/13/08 Update Ordering Information Table: Remove CY2314ANZSC-1 Add Pb-free devices CY2314ANZSXC-1 and CY2314ANZSXC-1T Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. 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Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07143 Rev. *B Revised November 10, 2008 Page 8 of 8 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback