CY24293 Two Outputs PCI-Express Clock Generator Features Functional Description ■ 25 MHz Crystal or Clock Input CY24293 is a two output PCI-Express clock generator device intended for networking applications. The device takes 25 MHz crystal or clock input and provides two pairs of differential outputs at 25 MHz, 100 MHz, 125 MHz, or 200 MHz for HCSL, and 25 MHz or 100 MHz for the LVDS signaling standard. ■ Two sets of Differential PCI-Express Clocks ■ Pin Selectable Output Frequencies ■ Supports HCSL or LVDS Compatible Output Levels ■ Spread Spectrum Capability on all Output Clocks with Pin Selectable Spread Range ■ 16-pin TSSOP Package ■ Operating Voltage 3.3V ■ Commercial and Industrial Operating Temperature Range The device incorporates Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction. The spread type and amount can be selected using select pins. Logic Block Diagram VDDX XIN/EXCLKIN Clock Buffer/ Crystal Oscillator (25 MHz) XOUT VDDO PCIE0P PCIE0N PLL Clock Synthesizer SS0 PCIE1P SS1 PCIE1N Control Logic S0 S1 I REF OE GNDX Cypress Semiconductor Corporation Document Number: 001-46117 Rev. *C • 198 Champion Court GNDO • R REF= 475 Ohms 1% San Jose, CA 95134-1709 • 408-943-2600 Revised April 02, 2009 [+] Feedback CY24293 Pinouts Figure 1. Pin Diagram - CY24293 16-Pin TSSOP S0 S1 1 16 2 15 PCIE0P SS0 XIN/EXCLKIN 3 4 14 PCIE0N GNDO XOUT 5 OE 6 GNDX SS1 TSSOP 13 VDDX 12 11 VDDO 7 10 PCIE1N 8 9 PCIE1P IREF Table 1. Pin Definitions - CY24293 16-Pin TSSOP Pin Number Pin Name Pin Type Description 1 S0 Input Frequency select pin. Has internal weak pull up. Refer to Table 2. 2 S1 Input Frequency select pin. Has internal weak pull up. Refer to Table 2. 3 SS0 Input 4 XIN/EXCLKIN Input Crystal or clock input. 25 MHz fundamental mode crystal or clock input. 5 XOUT Output Crystal output. 25 MHz fundamental mode crystal input. Float for clock input. OE Input High true output enable pin. When set low, PCI-E outputs are tri-stated. Has internal weak pull up. Ground 6 Spread Spectrum Select pin 0. Has internal weak pull up. Refer to Table 3. 7 GNDX Power 8 SS1 Input Spread Spectrum Select pin 1. Has internal weak pull up. Refer to Table 3. 9 IREF Output Current set for all differential clock drivers. Connect 475Ω resistor to ground. 10 PCIE1N Output Differential PCI-Express complementary clock output. Tristated when disabled. 11 PCIE1P Output Differential PCI-Express true clock output. Tristated when disabled. 12 VDDO Input 3.3V Power supply for output driver and analog circuits. 13 GNDO Power Ground 14 PCIE0N Output Differential PCI-Express complementary clock output. Tristated when disabled. 15 PCIE0P Output Differential PCI-Express true clock output. Tristated when disabled. 16 VDDX Input 3.3V Power supply for oscillator and digital circuits. Table 2. Output Selection Table S1 S0 PCIE0[N,P], PCIE1[N,P] 0 0 25 MHz 0 1 100 MHz 1 0 125 MHz 1 1 200 MHz Table 3. Spread Selection Table SS1 SS0 Spread% 0 0 No Spread 0 1 -0.5% 1 0 -0.75% 1 1 No Spread Document Number: 001-46117 Rev. *C Page 2 of 10 [+] Feedback CY24293 Application Information Crystal Recommendations CY24293 requires a parallel resonance crystal. Substituting a series resonance crystal causes the CY24293 to operate at the wrong frequency and violate the ppm specification. For most applications, there is a 300 ppm frequency shift between series and parallel crystals due to incorrect loading. Table 4. Crystal Recommendations Frequency Cut Load Cap Eff Series Rest (max) Drive (max) 25.00 MHz Parallel 16 pF 30 Ω 1.0 mW Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, consider the total capacitance the crystal sees to calculate the appropriate capacitive loading (CL). Figure 2 shows a typical crystal configuration using two trim capacitors. It is important to note that the trim capacitors in series with the crystal are not parallel. It is a common misconception that load capacitors are in parallel with the crystal and must be approximately equal to the load capacitance of the crystal. This is not true. Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned in the previous section, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1, Ce2) must be calculated to provide equal capacitive loading on both sides. Figure 2. Crystal Loading Example Clock Chip Ci2 Ci1 Pin 3 to 6p X2 X1 Cs1 30 ppm 10 ppm 5 ppm/yr. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2: Load capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL ................................................... Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance Current Source (Iref) Reference Resistor If the board target trace impedance (Z) is 50Ω, then for RREF = 475Ω (1%), provides IREF of 2.32 mA. The output current (IOH) is equal to 6*IREF. Output Termination The PCI-Express differential clock outputs of the CY24293 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are explained in the section PCI-Express Layout Guidelines on page 4. The CY24293 can also be configured for LVDS compatible voltage levels. Refer to the section LVDS Compatible Layout Guidelines on page 5. Cs2 Trace 2.8 pF XTAL Ce1 Tolerance (max) Stability (max) Aging (max) Ce2 Document Number: 001-46117 Rev. *C Trim 26 pF Page 3 of 10 [+] Feedback CY24293 PCB Layout Recommendations 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces must be routed away from the CY24293. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. For optimum device performance and the lowest phase noise, the following guidelines must be observed: 1. Each 0.01 µF decoupling capacitor must be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias must be used between the decoupling capacitor and the VDD pin. 3. The PCB trace to the VDD pin and the ground via must be kept as short as possible. Distance of the ferrite bead and bulk decoupling from the device is less critical. Decoupling Capacitors The decoupling capacitors of 0.01 µF must be connected between VDD and GND as close to the device as possible. Do not share ground vias between components. Route power from the power source through the capacitor pad and then into the CY24293 pin. PCI-Express Layout Guidelines HCSL Compatible Layout Guidelines Table 5. Common Recommendations for Differential Routing Differential Routing[1] Dimension or Value Unit L1 length, route as non-coupled 50Ω trace 0.5 max inch L2 length, route as non-coupled 50Ω trace 0.2 max inch L3 length, route as non-coupled 50Ω trace 0.2 max inch RS 33 Ω RT 49.9 Ω Dimension or Value Unit Table 6. Differential Routing for PCI-Express Load or Connector Differential Routing[1] L4 length, route as coupled microstrip 100Ω differential trace L4 length, route as coupled stripline 100Ω differential trace 2 to 32 inch 1.8 to 30 inch Figure 3. PCI-Express Device Routing Rs L1 L2 L4 L2 L4 RS L1 RT Output Buffer L3 RT L3 PCI Express Load or Connector Note 1. Refer to Figure 3. Document Number: 001-46117 Rev. *C Page 4 of 10 [+] Feedback CY24293 LVDS Compatible Layout Guidelines Table 7. Common Recommendations for Differential Routing Differential Routing[2] Dimension or Value Unit 0.5 max inch L1 length, route as noncoupled 50Ω trace L2 length, route as noncoupled 50Ω trace 0.2 max inch L3 length, route as noncoupled 50Ω trace 0.2 max inch RP 100 Ω RQ 150 Ω RS 33 Ω RT 49.9 Ω Differential Routing[2] Dimension or Value Unit L4 length, route as coupled microstrip 100Ω differential trace 2 to 32 inch 1.8 to 30 inch Table 8. LVDS Device Differential Routing L4 length, route as coupled stripline 100Ω differential trace Figure 4. LVDS Device Routing Rs L1 Rs L1 L4 L2 RQ RP L4 L2 RT Output Buffer L3 RT L3 LVDS Device Input Note 2. Refer to Figure 4. Document Number: 001-46117 Rev. *C Page 5 of 10 [+] Feedback CY24293 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 9. Absolute Maximum Ratings Parameter Description VDD Supply voltage Condition Min Max Unit –0.5 4.6 V VIN Input voltage Relative to VSS –0.5 VDD+0.5 V TS Temperature, Storage Non Functional –65 +150 °C TJ Temperature, Junction Non Functional –65 +150 °C ESDHBM ESD Protection (Human Body Model) JEDEC EIA/JESD22-A114-E 2000 – V UL-94 Flammability rating MSL Moisture sensitivity level V-0 at 1/8 in. 3 Recommended Operation Conditions Parameter Description VDD Supply voltage TAC Commercial ambient temperature TAI tPU Min Typ Max Unit 3.0 – 3.6 V 0 – +70 °C Industrial ambient temperature –40 – +85 °C Power up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms DC Electrical Characteristics Unless otherwise stated, VDD = 3.3V ±0.3V, ambient temperature = -40°C to +85°C Industrial, 0°C to +70°C Commercial Parameter[3] Description VIL Input low voltage Condition Min Typ Max Unit -0.3 – 0.8 V VIH Input high voltage 2.0 – VDD+0.3 V VOL Output low voltage of PCIE0[P/N], PCIE1[P/N] HCSL termination (RS = 33Ω, RT = 49.9Ω) -0.2 0 0.05 V VOH Output high voltage of PCIE0[P/N], PCIE1[P/N] HCSL termination (RS = 33Ω, RT = 49.9Ω) 0.65 0.71 0.85 V IDD Operating supply current No load, OE = 1 – 45 60 mA IDDOD Output disabled current OE = 0 – – 50 mA CIN Input capacitance All input pins – 5 – pF RPU Pull up resistance S0, S1, SS0, SS1, OE – 70k – Ω Note 3. Parameters are guaranteed by design and characterization. Not 100% tested in production Document Number: 001-46117 Rev. *C Page 6 of 10 [+] Feedback CY24293 , AC Electrical Characteristics Unless otherwise stated: VDD = 3.3V ±0.3V, ambient temperature = -40°C to +85°C Industrial, 0°C to +70°C Commercial, Outputs HCSL terminated. Parameter[3] Description Condition FIN Input clock frequency (crystal or external clock) FOUT Output frequency FERR Frequency synthesis error TCCJ Cycle-to-cycle jitter SPMOD Spread modulation frequency Min Typ Max Unit – 25 – MHz HCSL Termination – – 200 MHz LVDS Termination – – 100 MHz – 0 – ppm – – 75 ps [4] – 32 – kHz 45 50 55 % OE going high to differential outputs becoming valid – – 200 ns Output disable time OE going low to differential outputs becoming invalid – – 200 ns TLOCK Clock stabilization from power up Measured from 90% of the applied power supply level – 1 2 ms TR Output rise time[4,5] Measured from 0.175V to 0.525V 130 – 700 ps TF Output fall time[4,5] Measured from 0.525V to 0.175V 130 – 700 ps DTR Rise time variation[4,5] For a given frequency, Max(TR) - Min (TR) – – 125 ps DTF Fall time variation[4,5] For a given frequency, Max(TF) - Min (TF) – – 125 ps TOSKEW Output skew[6] Measured at VCROSS point – – 50 ps VCROSS Absolute crossing point voltage[6,7] 0.25 0.35 0.55 V VXdelta Variation of VCROSS over all clock edges[6,8] – – 140 mV TDC Output clock duty TOEH Output enable time TOEL cycle[4,6] Test and Measurement Setup Figure 5. Test Load Configuration for Differential Output Signals 33 Ohm PCIEP CLoad 50 Ohm CLoad 50 Ohm 33 Ohm PCIEN 475 Ohm Notes 4. Measured with Cload = 4 pF max. (scope probe + trace load) 5. Measurement taken from a differential waveform. 6. Measured at crossing point where the instantaneous voltage value of the rising edge of PCIEP equals the falling edge of PCIEN. 7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 8. Refers to the difference between the PCIEP rising edge VCROSS average value and the PCIEN rising edge VCROSS average value. Document Number: 001-46117 Rev. *C Page 7 of 10 [+] Feedback CY24293 Ordering Information Part Number Type Production Flow Pb-free CY24293ZXC 16-pin TSSOP Commercial, 0°C to 70°C CY24293ZXCT 16-pin TSSOP tape & reel Commercial, 0°C to 70°C CY24293ZXI 16-pin TSSOP Industrial, -40°C to 85°C CY24293ZXIT 16-pin TSSOP tape & reel Industrial, -40°C to 85°C Package Dimensions Figure 6. 16-Pin TSSOP 4.40 mm Body Package PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.05gms 6.25[0.246] 6.50[0.256] PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091 *A Document Number: 001-46117 Rev. *C Page 8 of 10 [+] Feedback CY24293 Document History Page Document Title: CY24293 Two Outputs PCI-Express Clock Generator Document Number: 001-46117 REV. ECN NO. Orig. of Change Submission Date ** 2490167 PYG/DPF/AESA *A 2507681 DPF/AESA See ECN Description of Change New Data Sheet 05/23/2008 Added Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. Added Note 2 for Duty cycle spec in the AC Elect. Characteristics. Added HCSL termination in Condition for VOL, VOH DC Elect. Char. Added VXdelta value of 140 mV in the Differential 100 MHz HCSL output. Changed Cload from 2 pF to 4 pF in Note 2. Added internal weak Pull ups for S0, S1, SS0, SS1 and OE pins. Updated TOEH and TOEL to 200 ns (max.). Updated data sheet template *B 2621901 CXQ/AESA 12/19/2008 Updated IDD spec in DC Electrical Characteristics. Added max spec for IDDOD DC Electrical Characteristics. Added RPU in DC Electrical Characteristics. Replaced TRFVAR with DTR and DTF in AC Electrical Characteristics. Added definitions for rise and fall time variation, crossing point variation in AC Electrical Characteristics. Reduced cycle-to-cycle jitter spec to 75ps in AC Electrical Characteristics. *C 2683343 CXQ/PYRS 04/03/2009 Removed “Preliminary” from datasheet title and headings Added “max” to crystal ESR spec. Changed “LVDS Down Device” to “LVDS Device” in Table 8 and Figure 4. Document Number: 001-46117 Rev. *C Page 9 of 10 [+] Feedback CY24293 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solutions PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-46117 Rev. *C Revised April 02, 2009 Page 10 of 10 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback