CYPRESS CY62138F_11

CY62138F MoBL®
2-Mbit (256 K × 8) Static RAM
2-Mbit (256 K × 8) Static RAM
Features
Functional Description
■
High speed: 45 ns
The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE1 HIGH or CE2 LOW).
■
Wide voltage range: 4.5 V to 5.5 V
■
Pin compatible with CY62138V
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 5 A
■
Ultra low active power
❐ Typical active current: 1.6 mA @ f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 32-pin SOIC and 32-pin thin small outline
package (TSOP) II packages
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A17).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and output enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
Logic Block Diagram
Cypress Semiconductor Corporation
Document #: 001-13194 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 20, 2011
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CY62138F MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Document #: 001-13194 Rev. *E
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 13
Documents Conventions ............................................... 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
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CY62138F MoBL®
Pin Configuration
Figure 1. 32-pin SOIC/TSOP II Pinout (Top View)
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
32
31
2
3
4
30
29
5
6
28
27
26
25
7
8
9
10
24
23
22
11
12
13
14
15
16
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62138FLL
Speed
(ns)
Min
Typ [1]
Max
4.5 V
5.0 V
5.5 V
45
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2 (A)
Typ [1]
Max
Typ [1]
Max
Typ [1]
Max
1.6
2.5
13
18
1
5
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document #: 001-13194 Rev. *E
Page 3 of 15
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CY62138F MoBL®
DC Input Voltage [2, 3] ......... –0.5 V to 6.0 V (VCCmax + 0.5 V)
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage to ground
potential ............................. –0.5 V to 6.0 V (VCCmax + 0.5 V)
DC voltage applied to outputs
in High Z state [2, 3] ............. –0.5 V to 6.0 V (VCCmax + 0.5 V)
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ........................................ > 2001 V
(MIL–STD–883, Method 3015)
Latch-up Current .................................................... > 200 mA
Operating Range
Device
CY62138FLL
Range
Industrial
Ambient
Temperature
VCC [4]
–40 °C to +85 °C 4.5 V to 5.5 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
IOH = –1.0 mA
45 ns
Min
Typ [5]
Max
2.4
–
–
Unit
VOH
Output HIGH voltage
V
VOL
Output LOW voltage
IOL = 2.1 mA
–
–
0.4
V
VIH
Input HIGH voltage
VCC = 4.5 V to 5.5 V
2.2
–
VCC + 0.5
V
–0.5
–
0.8
V
–1
–
+1
A
VIL
Input LOW voltage
VCC = 4.5 V to 5.5 V
IIX
Input leakage current
GND < VI < VCC
IOZ
Output leakage current
GND < VO < VCC, Output disabled
–1
–
+1
A
ICC
VCC operating supply
Current
f = fmax = 1/tRC
–
13
18
mA
–
1.6
2.5
–
1
5
ISB2 [6]
f = 1 MHz
VCC = VCC(max),
IOUT = 0 mA,
CMOS levels
Automatic CE Power-down CE1 > VCC – 0.2 V or CE2 < 0.2 V,
current CMOS inputs
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
A
Notes
2. VIL(min) = –2.0 V for pulse durations less than 20 ns.
3. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
4. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
6. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 001-13194 Rev. *E
Page 4 of 15
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CY62138F MoBL®
Capacitance
Parameter [7]
CIN
Description
Test Conditions
Input capacitance
COUT
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Output capacitance
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [7]
Description
JA
Thermal resistance
(Junction to Ambient)
JC
Thermal resistance
(Junction to Case)
Test Conditions
32-pin SOIC
Still air, soldered on a 3 × 4.5 inch
two-layer printed circuit board
32-pin TSOP II Unit
44.53
44.16
C/W
24.05
11.97
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
VCC
OUTPUT
ALL INPUT PULSES
3.0 V
30 pF
INCLUDING
JIG AND
SCOPE
90%
10%
R2
GND
Rise Time = 1 V/ns
Equivalent to:
90%
10%
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
OUTPUT
RTH
Parameters
5.0 V
Unit
R1
1800

R2
990

RTH
639

VTH
1.77
V
V
Note
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-13194 Rev. *E
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CY62138F MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
Conditions
VCC for Data retention
[9]
Data retention current
VCC = VDR, CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Min
Typ [8]
Max
Unit
2.0
–
–
V
–
1
5
A
tCDR [8]
Chip deselect to data
retention time
0
–
–
ns
tR [10]
Operation recovery time
45
–
–
ns
Data Retention Waveform
Figure 3. Data Retention Waveform [11]
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 2.0 V
VCC(min)
tR
CE
Notes
8. Tested initially and after any design or process changes that may affect these parameters. Typical values are included for reference only and are not guaranteed or
tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
9. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
10. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
11. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
Document #: 001-13194 Rev. *E
Page 6 of 15
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CY62138F MoBL®
Switching Characteristics
Over the Operating Range
Parameter [12]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
5
–
ns
–
18
ns
10
–
ns
OE LOW to low Z
tLZOE
[13]
OE HIGH to high Z
tHZOE
[13, 14]
[13]
tLZCE
CE1 LOW and CE2 HIGH to low Z
tHZCE
CE1 HIGH or CE2 LOW to high Z [13, 14]
–
18
ns
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
ns
CE1 HIGH or CE2 LOW to power-down
–
45
ns
tWC
Write cycle time
45
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to high Z [13, 14]
–
18
ns
10
–
ns
tPD
Write Cycle
tLZWE
[15]
WE HIGH to low Z
[13]
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE , tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
14. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
15. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-13194 Rev. *E
Page 7 of 15
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CY62138F MoBL®
Switching Waveforms
Figure 4. Read Cycle 1 (Address Transition Controlled) [16, 17]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [17, 18, 19]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
HIGH IMPEDANCE
DATA OUT
DATA VALID
tLZCE
tPD
tPU
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
50%
50%
ICC
ISB
Figure 6. Write Cycle No. 1 (WE Controlled) [19, 20, 21, 22]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
NOTE 23
tHD
DATA VALID
tHZOE
Notes
16. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
17. WE is HIGH for read cycle.
18. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
19. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
20. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
21. Data I/O is high impedance if OE = VIH.
22. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
23. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-13194 Rev. *E
Page 8 of 15
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CY62138F MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (CE1 or CE2 Controlled) [24, 25, 26, 27]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [24, 27]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 28
tHD
DATA VALID
tHZWE
tLZWE
Notes
24. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
25. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
26. Data I/O is high impedance if OE = VIH.
27. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
28. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-13194 Rev. *E
Page 9 of 15
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CY62138F MoBL®
Truth Table
CE1
CE2
WE
OE
Inputs/Outputs
Mode
Power
[29]
X
X
High Z
Deselect/Power-down
Standby (ISB)
X[29]
L
X
X
High Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
Data out
Read
Active (ICC)
L
H
H
H
High Z
Output disabled
Active (ICC)
L
H
L
X
Data in
Write
Active (ICC)
H
X
Note
29. The ‘X’ (Don’t care) state for the Chip enables (CE1 and CE2) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document #: 001-13194 Rev. *E
Page 10 of 15
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CY62138F MoBL®
Ordering Information
Speed
(ns)
45
Package
Diagram
Ordering Code
Package Type
CY62138FLL-45SXI
51-85081 32-pin Small Outline Integrated Circuit (Pb-free)
CY62138FLL-45ZSXI
51-85095 32-pin Thin Small Outline Package II (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 3
8
F
LL - 45
XX X
I
Temperature Grade: I = Industrial
Pb-free
Package Type: XX = S or ZS
S = 32-pin SOIC
ZS = 32-pin TSOP II
Speed Grade: 45 ns
LL = Low Power
F = Process Technology 90 nm
Bus width = × 8
Density = 2-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document #: 001-13194 Rev. *E
Page 11 of 15
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CY62138F MoBL®
Package Diagrams
Figure 9. 32-pin (450 Mil) Molded SOIC, 51-85081
51-85081 *C
Document #: 001-13194 Rev. *E
Page 12 of 15
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CY62138F MoBL®
Package Diagrams (continued)
Figure 10. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32, 51-85095
51-85095 *B
Acronyms
Acronym
Documents Conventions
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
I/O
input/output
°C
degree Celsius
Symbol
Unit of Measure
OE
output enable
MHz
Mega Hertz
SOIC
small outline integrated circuit
A
micro Amperes
SRAM
static random access memory
s
micro seconds
TSOP
thin small outline package
mA
milli Amperes
WE
write enable
ns
nano seconds

ohms
%
percent
pF
pico Farads
V
Volts
W
Watts
Document #: 001-13194 Rev. *E
Page 13 of 15
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CY62138F MoBL®
Document History Page
Document Title: CY62138F MoBL®, 2-Mbit (256 K × 8) Static RAM
Document Number: 001-13194
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
797956
See ECN
VKN
New Data Sheet
*A
940341
See ECN
VKN
Added footnote #7 related to ISB2 and ICCDR
*B
3055174
13/10/2010
RAME
Updated As per new template
Added Acronyms and Units of Measure table.
Added Ordering Code Definitions.
Footnotes updated
Updated Package Diagram Figure 9 and Figure 10.
*C
3061313
15/10/2010
RAME
Minor change: Corrected “IO” to “I/O”
*D
3232735
04/18/2011
RAME
Removed the Note “For best practice recommendations, refer to the Cypress
application note “System Design Guidelines” at http://www.cypress.com ” in
page 1.
*E
3287636
06/20/2011
RAME
Updated Package Diagrams.
Updated in new template.
Document #: 001-13194 Rev. *E
Page 14 of 15
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CY62138F MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-13194 Rev. *E
Revised June 20, 2011
Page 15 of 15
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective
holders.
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