ZILOG Z8FMC04100

Z8 Encore!® Motor Control Flash MCUs
Z8FMC16100 Series
Product Specification
PS024604-1005
PRELIMINARY
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PS024604-1005
PRELIMINARY
Z8FMC16100 Series Flash MCU
Product Specification
iii
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z8FMC16100 Series Flash MCU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse-Width Modulator for Motor Control Applications . . . . . . . . . . . . . . . . . . . . . .
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Random Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART with LIN and IrDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
2
3
3
3
4
4
4
4
4
4
4
5
5
5
5
5
5
5
Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
14
14
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset and Stop-Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS024604-1005
PRELIMINARY
23
23
24
25
Table of Contents
Z8FMC16100 Series Flash MCU
Product Specification
iv
PS024604-1005
Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watch-Dog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Reset Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Detect Logic Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop-Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop-Mode Recovery Using Watch-Dog Timer Time-Out . . . . . . . . . . . . . . . . . . .
Stop-Mode Recovery Using a GPIO Port Pin Transition . . . . . . . . . . . . . . . . . . . . .
PWM Fault0 and Reset pin selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
26
27
27
27
27
28
28
28
29
29
29
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral-Level Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
32
33
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A-C Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–C Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A-C Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–C Output Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
35
35
36
39
39
40
41
48
49
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt and System Exception Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
51
53
53
54
54
54
55
55
55
57
PRELIMINARY
Table of Contents
Z8FMC16100 Series Flash MCU
Product Specification
v
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PS024604-1005
Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watch-Dog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watch-Dog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watch-Dog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watch-Dog Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . .
63
63
64
64
65
65
Pulse-Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Off State and Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Channel Pair Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Reload Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Period and Count Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Duty Cycle Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Independent and Complementary PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual Off-State Control of PWM Output Channels . . . . . . . . . . . . . . . . . . . . . . .
Deadband Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum PWM Pulse Width Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization of PWM and Analog-to-Digital Converter . . . . . . . . . . . . . . . . . .
PWM Timer and Fault Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Detection and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Operation in CPU Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Operation in CPU Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Observing the State of PWM Output Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM 0–2 Duty Cycle High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . .
PWM Control 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Deadband Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Minimum Pulse Width Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Fault Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Fault Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Fault Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Input Sample Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
67
68
69
69
69
70
70
72
72
72
72
73
73
74
74
74
75
75
75
76
77
78
80
81
82
82
83
85
86
87
PRELIMINARY
Table of Contents
Z8FMC16100 Series Flash MCU
Product Specification
vi
Current Sense ADC Trigger Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
General-Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Timer 0 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Timer 0 Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Timer 0 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Timer 0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
LIN-UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format for Standard UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . .
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . . .
Clear To Send Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Protocol Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Mode Select and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Control 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . .
111
111
112
113
114
115
116
117
117
118
118
120
124
127
127
128
128
130
130
130
131
133
134
136
140
140
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
PS024604-1005
PRELIMINARY
Table of Contents
Z8FMC16100 Series Flash MCU
Product Specification
vii
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . .
145
146
147
148
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multimaster Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
149
149
151
151
152
154
155
155
156
156
157
158
159
160
161
162
I2C Master/Slave Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Master/Slave Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparison with the Master Mode Only I2C Controller . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
163
163
165
165
166
166
167
169
169
169
177
184
184
186
187
188
192
193
Comparator and Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
PS024604-1005
PRELIMINARY
Table of Contents
Z8FMC16100 Series Flash MCU
Product Specification
viii
Comparator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational Amplifier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparator and Op Amp Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
196
196
197
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Timer 0 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calibration and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Raw Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Settling Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Clock Prescale Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Timer Capture High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Timer Capture Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
199
199
200
201
202
202
202
202
203
203
204
204
205
206
206
207
208
208
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Write/Erase Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
211
212
213
213
213
214
215
216
216
216
216
217
218
218
219
220
Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
PS024604-1005
PRELIMINARY
Table of Contents
Z8FMC16100 Series Flash MCU
Product Specification
ix
Option Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trim Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trim Bit Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trim Bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trim Bit Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trim Bit Address 0002H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trim Bit Address 0003H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
223
223
223
224
224
224
225
227
227
228
228
229
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Selection Following System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Failure Detection and Recovery for Primary Oscillator . . . . . . . . . . . . . . . .
Clock Failure Detection and Recovery for WDT Oscillator . . . . . . . . . . . . . . . . .
Oscillator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Divide Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
231
231
231
232
232
233
233
234
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Break Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCDCNTR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Reload Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS024604-1005
PRELIMINARY
241
241
241
243
243
244
244
245
245
246
247
252
254
255
Table of Contents
Z8FMC16100 Series Flash MCU
Product Specification
x
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . .
General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . . . . . . .
General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
257
257
257
258
264
265
271
272
273
274
eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
277
277
278
279
281
282
286
295
Op Code Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Appendix A—Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse-Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN-UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trim Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS024604-1005
PRELIMINARY
307
307
307
315
332
336
338
342
347
348
Table of Contents
Z8FMC16100 Series Flash MCU
Product Specification
xi
Comparator and Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset and Watch-Dog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Op Code Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
349
350
355
356
358
360
362
365
365
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
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Table of Contents
Z8FMC16100 Series Flash MCU
Product Specification
xii
PS024604-1005
PRELIMINARY
Table of Contents
Z8FMC16100 Series Flash MCU
Product Specification
xiii
List of Figures
Figure 1. Z8FMC16100 Series Flash MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Z8FMC16100 Series Flash MCU in 32-Pin QFN and LQFP Package . . . . . . . 8
Figure 3. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 4. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 5. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 6. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 7. PWM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 8. Edge-Aligned PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 9. Center-Aligned PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 10. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 11. LIN-UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 12. LIN-UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . 113
Figure 13. LIN-UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . 113
Figure 14. LIN-UART Driver Enable Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 15. LIN-UART Asynchronous Multiprocessor Mode Data Format . . . . . . . . . 119
Figure 16. LIN-UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . 126
Figure 17. Noise Filter System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 18. Noise Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 19. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . . 145
Figure 20. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 21. Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 22. SPI Configured as a Master in a Single Master, Single Slave System . . . . 149
Figure 23. SPI Configured as a Master in a Single Master, Multiple Slave System . . . 150
Figure 24. SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 25. SPI Timing When Phase is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 26. SPI Timing When Phase is 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 27. I2C Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 28. Data Transfer Format—Master Write Transaction with a 7-Bit Address . . 171
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PRELIMINARY
List of Figures
Z8FMC16100 Series Flash MCU
Product Specification
xiv
Figure 29. Data Transfer Format—Master Write Transaction with a 10-Bit Address . 172
Figure 30. Data Transfer Format—Master Read Transaction with a 7-Bit Address . . . 174
Figure 31. Data Transfer Format—Master Read Transaction with a 10-Bit Address . . 175
Figure 32. Data Transfer Format—Slave Receive Transaction with 7-Bit Address . . . 179
Figure 33. Data Transfer Format—Slave Receive Transaction with 10-Bit Address . . 180
Figure 34. Data Transfer Format—Slave Transmit Transaction with 7-bit Address . . 181
Figure 35. Data Transfer Format—Slave Transmit Transaction with 10-Bit Address . 182
Figure 36. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 37. ADC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 38. ADC Convert Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 39. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 40. Recommended 20MHz Crystal Oscillator Configuration . . . . . . . . . . . . . . 237
Figure 41. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 42. Interfacing the On-Chip Debugger’s DBG Pin with
an RS-232 Interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 43. Interfacing the On-Chip Debugger’s DBG Pin with
an RS-232 Interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 44. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 45. Typical Active Mode IDD Versus System Clock Frequency . . . . . . . . . . . . 261
Figure 46. Maximum Active Mode IDD Versus System Clock Frequency . . . . . . . . . . 261
Figure 47. Typical Halt Mode IDD Versus System Clock Frequency . . . . . . . . . . . . . . 262
Figure 48. Maximum Halt Mode ICC Versus System Clock Frequency . . . . . . . . . . . . 262
Figure 49. Maximum Stop Mode IDD with VBO enabled versus Supply Voltage . . . . 263
Figure 50. Maximum Stop Mode IDD with VBO Disabled vs. Supply Voltage . . . . . . 264
Figure 51. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 52. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 53. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 54. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 55. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Figure 56. Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 57. Op Code Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
PS024604-1005
PRELIMINARY
List of Figures
Z8FMC16100 Series Flash MCU
Product Specification
xv
Figure 58. First Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 59. Second Op Code Map After 1Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 60. 32-Pin Quad Flat No Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 61. 32-Pin Low Quad Flat Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
PS024604-1005
PRELIMINARY
List of Figures
Z8FMC16100 Series Flash MCU
Product Specification
xvi
PS024604-1005
PRELIMINARY
List of Figures
Z8FMC16100 Series Flash MCU
Product Specification
xvii
List of Tables
Table 1. Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Pin Characteristics of the Z8FMC16100 Series Flash MCU . . . . . . . . . . . . . . . 11
Table 3. Z8FMC16100 Series Flash MCU Program Memory Maps . . . . . . . . . . . . . . . . 14
Table 4. Z8FMC16100 Series Information Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Reset and Stop-Mode Recovery Characteristics and Latency . . . . . . . . . . . . . . 23
Table 7. System Reset Sources and Resulting Reset Action . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Stop-Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . . . . . 28
Table 9. Reset Status and Control Register (RSTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Reset Status Register Values Following Reset. . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Power Control Register 0(PWRCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. Port Alternate Function Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. GPIO Port Registers and Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15. Port A–C GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Port Control Subregisters by Port Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. Port A–C Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. Port A–C Data Direction Sub-Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. Port A–B Alternate Function 0 Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. Port A–C Output Control Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 21. Port A–C High Drive Enable Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 22. Port A–C STOP Mode Recovery Source Enable Sub-Registers . . . . . . . . . . . 45
Table 23. Port A–C Pull-Up Enable Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 24. Interrupt Edge Select Sub-Register (IRQES). . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. Interrupt Port Select Sub-Register (IRQPS). . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 26. Port A–B Alternate Function 1 Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 27. Port A-C Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 28. Port A-C Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 29. Reset, System Exception, and Interrupt Vectors in Order of Priority . . . . . . . 52
Table 30. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 31. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 32. IRQ0 Enable and Priority Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 33. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PS024604-1005
PRELIMINARY
List of Tables
Z8FMC16100 Series Flash MCU
Product Specification
xviii
Table 34. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 35. IRQ1 Enable and Priority Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 36. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 37. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 38. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 39. Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . . . 64
Table 40. Watch-Dog Timer Reload High Byte Register (WDTH). . . . . . . . . . . . . . . . . 66
Table 41. Watch-Dog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . . . 66
Table 42. PWM High Byte Register (PWMH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 43. PWM Reload High Byte Register (PWMRH) . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 44. PWM Low Byte Register (PWML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 45. PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH). . 77
Table 46. PWM Reload Low Byte Register (PWMRL). . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 47. PWM Control 0 Register (PWMCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 48. PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL) . . 78
Table 49. PWM Control 1 Register (PWMCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 50. PWM Dead-Band Register (PWMDB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 51. PWM Minimum Pulse Width Filter (PWMMPF) . . . . . . . . . . . . . . . . . . . . . . 82
Table 52. PWM Fault Mask Register (PWMFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 53. PWM Fault Status Register (PWMFSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 54. PWM Fault Control Register (PWMFCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 55. PWM Input Sample Register (PWMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 56. PWM Output Control Register (PWMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 57. Current-Sense Trigger Control Register (PWMSHC) . . . . . . . . . . . . . . . . . . . 88
Table 58. Timer 0 High Byte Register (T0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 59. Timer 0 Low Byte Register (T0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 60. Timer 0 Reload High Byte Register (T0RH) . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 61. Timer 0 Reload Low Byte Register (T0RL) . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 62. Timer 0 PWM High Byte Register (T0PWMH) . . . . . . . . . . . . . . . . . . . . . . 105
Table 63. Timer 0 PWM Low Byte Register (T0PWML) . . . . . . . . . . . . . . . . . . . . . . . 105
Table 64. Timer 0 Control 0 Register (T0CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 65. Timer 0 Control 1 Register (T0CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 66. LIN-UART Transmit Data Register (U0TXD) . . . . . . . . . . . . . . . . . . . . . . . 130
Table 67. LIN-UART Receive Data Register (U0RXD) . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 68. LIN-UART Status 0 Register - standard UART mode (U0STAT0) . . . . . . . 131
Table 69. LIN-UART Status 0 Register - LIN mode (U0STAT0). . . . . . . . . . . . . . . . . 132
PS024604-1005
PRELIMINARY
List of Tables
Z8FMC16100 Series Flash MCU
Product Specification
xix
Table 70. LIN-UART Mode Select and Status Register (U0MDSTAT) . . . . . . . . . . . .
Table 71. LIN-UART Control 0 Register (U0CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 72. MultiProcessor Control Register (U0CTL1 with MSEL = 000b) . . . . . . . . .
Table 73. Noise Filter Control Register (U0CTL1 with MSEL = 001b) . . . . . . . . . . . .
Table 74. LIN Control Register (U0CTL1 with MSEL = 010b) . . . . . . . . . . . . . . . . . .
Table 75. LIN-UART Address Compare Register (U0ADDR) . . . . . . . . . . . . . . . . . . .
Table 76. LIN-UART Baud Rate High Byte Register (U0BRH). . . . . . . . . . . . . . . . . .
Table 77. LIN-UART Baud Rate Low Byte Register (U0BRL) . . . . . . . . . . . . . . . . . .
Table 78. LIN-UART Baud Rates, 20.0 MHz System Clock . . . . . . . . . . . . . . . . . . . .
Table 79. LIN-UART Baud Rates, 10.0 MHz System Clock. . . . . . . . . . . . . . . . . . . . .
Table 80. LIN-UART Baud Rates, 5.5296 MHz System Clock . . . . . . . . . . . . . . . . . .
Table 81. LIN-UART Baud Rates, 3.579545 MHz System Clock . . . . . . . . . . . . . . . .
Table 82. LIN-UART Baud Rates, 1.8432 MHz System Clock . . . . . . . . . . . . . . . . . .
Table 83. SPI Clock Phase and Clock Polarity Operation . . . . . . . . . . . . . . . . . . . . . . .
Table 84. SPI Data Register (SPIDATA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 85. SPI Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 86. SPI Status Register (SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 87. SPI Mode Register (SPIMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 88. SPI Diagnostic State Register (SPIDST) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 89. SPI Baud Rate High Byte Register (SPIBRH). . . . . . . . . . . . . . . . . . . . . . . .
Table 90. SPI Baud Rate Low Byte Register (SPIBRL) . . . . . . . . . . . . . . . . . . . . . . . .
Table 91. I2C Master/Slave Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 92. I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 93. I2C Interrupt Status Register (I2CISTAT). . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 94. I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 95. I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . . . . . . . . . . . . . . . .
Table 96. I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . . . . . . . . . . . . . . . .
Table 97. I2C State Register (I2CSTATE) - Description when DIAG = 0 . . . . . . . . . .
Table 98. I2C State Register (I2CSTATE) - Description when DIAG = 1 . . . . . . . . . .
Table 99. I2CSTATE_H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 100. I2CSTATE_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 101. I2C Mode Register (I2CMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 102. I2C Slave Address Register (I2CSLVAD). . . . . . . . . . . . . . . . . . . . . . . . . .
Table 103. Comparator and Op Amp Control Register (CMPOPC) . . . . . . . . . . . . . . .
Table 104. ADC Control Register 0 (ADCCT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 105. ADC Raw Data High Byte Register (ADCRD_H) . . . . . . . . . . . . . . . . . . .
PS024604-1005
PRELIMINARY
133
135
136
138
139
140
140
141
142
142
143
143
143
153
157
158
159
160
161
162
162
165
184
185
186
188
188
189
190
190
191
192
193
197
203
204
List of Tables
Z8FMC16100 Series Flash MCU
Product Specification
xx
Table 106. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . .
Table 107. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 108. Sample and Settling Time (ADCSST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 109. Sample Hold Time (ADCST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 110. ADC Clock Prescale Register (ADCCP) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 111. ADC Timer Capture High Byte Register (ADCTCAP_H) . . . . . . . . . . . . .
Table 112. ADC Timer Capture Low Byte Register (ADCTCAP_L) . . . . . . . . . . . . . .
Table 113. Flash Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 114. Flash Memory Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 115. Z8FMC16100 Series Flash MCU Information Area Map . . . . . . . . . . . . . .
Table 116. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 117. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 118. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 119. Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 120. Flash Frequency High Byte Register (FFREQH). . . . . . . . . . . . . . . . . . . . .
Table 121. Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . .
Table 122. User Option Bits at Program Memory Address 0000H . . . . . . . . . . . . . . . .
Table 123. Options Bits at Program Memory Address 0001H . . . . . . . . . . . . . . . . . . .
Table 124. Trim Bit Address Register (TRMADR). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 125. Trim Bit Data Register (TRMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 126. IPO Trim Option Bits at 0001H (IPO_TRIM) . . . . . . . . . . . . . . . . . . . . . . .
Table 127. IPO Trim1 Option Bits at 0002H (IPO_TRIM1) . . . . . . . . . . . . . . . . . . . . .
Table 128. Trim Option Bits at 0004H (ADCCAL). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 129. Oscillator Configuration and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 130. Oscillator Control Register (OSCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 131. Oscillator Divide Register (OSCDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 132. Recommended Crystal Oscillator Specifications (20MHz Operation) . . . .
Table 133. OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 134. On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 135. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 136. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 137. Baud Reload Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 138. Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 139. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 140. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 141. POR and VBO Electrical Characteristics and Timing . . . . . . . . . . . . . . . . .
PS024604-1005
PRELIMINARY
205
205
206
207
207
208
209
211
211
213
217
218
219
219
220
221
224
225
227
227
228
228
229
232
233
235
238
244
247
253
254
255
257
258
264
265
List of Tables
Z8FMC16100 Series Flash MCU
Product Specification
xxi
Table 142. External RC Oscillator Electrical Characteristics and Timing. . . . . . . . . . .
Table 143. Internal Precision Oscillator Electrical Characteristics and Timing . . . . . .
Table 144. Watch-Dog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . .
Table 145. Reset and Stop-Mode Recovery Pin Timing . . . . . . . . . . . . . . . . . . . . . . . .
Table 146. Analog-to-Digital Converter Electrical Characteristics and Timing . . . . . .
Table 147. Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 148. Operational Amplifier Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .
Table 149. GPIO Port Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 150. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 151. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 152. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 153. UART Timing without CTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 154. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 155. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 156. Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 157. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 158. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 159. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 160. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 161. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 162. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 163. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 164. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 165. eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 166. Op Code Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 167. Z8FMC16100 Series Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . .
Table 168. Ordering Information for the Z8FMC16100 Series Products* . . . . . . . . . .
Table 169. Current-Sense Trigger Control Register (PWMSHC) . . . . . . . . . . . . . . . . .
PS024604-1005
PRELIMINARY
266
266
267
267
267
268
269
271
272
273
274
275
279
280
281
282
283
283
284
284
285
285
285
286
297
302
303
323
List of Tables
Z8FMC16100 Series Flash MCU
Product Specification
xxii
PS024604-1005
PRELIMINARY
List of Tables
Z8FMC16100 Series Flash MCU
Product Specification
1
Introduction
The Z8FMC16100 Series Flash MCU is based on ZiLOG’s advanced eZ8 8-bit CPU core
and is optimized for motor control applications. It supports control of single- and multiphase variable speed motors. Target applications are consumer appliances, HVAC, factory automation, refrigeration, and automotive applications, among others.
Z8FMC16100 Series Flash MCU Features
PS024604-1005
•
•
•
•
•
20 MHz ZiLOG eZ8 CPU core
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16-bit timer with capture/compare/PWM capability
Up to 16 KB Flash program memory
512 B register RAM
Fast 8-channel 10-bit analog-to-digital converter
12-bit PWM module with three complementary pairs or six independent PWM outputs
with deadband generation and fault trip input
Analog comparator
Operational amplifier
I2C controller supports master, slave, and multimaster modes
UART with interface support for LIN and IrDA
SPI controller
Internal precision oscillator
On-chip oscillator supports external crystals, ceramic resonators, and clock drivers
17 General Purpose I/O pins (GPIO)
Voltage Brown-Out/Power On Reset (VBO/POR)
Watch-Dog Timer (WDT) with internal RC oscillator
On-chip debugger
In-circuit serial programming
Operating at 2.7 to 3.6 volts
32-pin packages
Lead-free packaging
Standard and extended temperature ranges: 0° to 70° (S) and –40° to 105°C (E)
Up to 20 interrupts with configurable priority
PRELIMINARY
Z8FMC16100 Series Flash MCU Features
Z8 Encore!® Motor Control Flash MCUs
Product Specification
2
Block Diagram
Figure 1 illustrates the architecture of the Z8FMC16100 Series Flash MCU.
3
8
Port A
Analog Supply
and Reference
Digital Supply
UART with LIN
and IrDA
Interrupt Control
I2C
Master/Slave
Reset Control
SPI
Watch-Dog Timer
Comparator
RC Oscillator
Operational
Amplifier
Fault
Shutdown
2
1
Internal Precision
Oscillator
Oscillator Control
Internal/External
2
8-Channel
Multiplexer
8
Port B
Sample and Hold
eZ8
20 MHz CPU
A/D Converter
Debugger
1
6
16-Bit Counter/
Timer/PWM
Port C
12-Bit PWM Module
for Motor Control
1
Register File (RAM)
512B x 8
Flash Program
Memory
Up to 16K x 8
Figure 1. Z8FMC16100 Series Flash MCU Block Diagram
Introduction
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
3
CPU and Peripheral Overview
The eZ8 CPU, ZiLOG’s latest 8-bit central processing unit, meets the continuing demand
for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of
the original Z8® instruction set. The eZ8 CPU features include:
•
Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory
•
Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks
•
•
Compatible with existing Z8® assembly code
•
•
Pipelined instruction fetch and execution
•
•
•
•
•
New instructions support 12-bit linear addressing of the Register File
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL
Up to 10 MIPS operation
C-Compiler friendly
2-9 clock cycles per instruction
For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual
(UM0128), available for download at www.zilog.com.
Pulse-Width Modulator for Motor Control Applications
To rotate a 3-phase motor three voltage and current signals must be supplied, each 120°
shifted from each other. To control a 3-phase motor the MCU must provide 6 PWM outputs.
The Z8FMC16100 Series Flash MCU features a flexible PWM module with three complementary pairs or six independent PWM outputs supporting deadband operation and fault
protection trip input. These features provide multiphase control capability for a variety of
motor types and ensure safe operation of the motor by providing immediate shutdown of
the PWM pins during fault condition.
10-Bit Analog-to-Digital Converter
The Z8FMC16100 Series Flash MCU devices feature up to eight channels of 10-bit A/D
conversion.
PS024604-1005
PRELIMINARY
CPU and Peripheral Overview
Z8 Encore!® Motor Control Flash MCUs
Product Specification
4
Analog Comparator
The Z8FMC16100 Series Flash MCU features an on-chip analog comparator with external
input pins.
Operational Amplifier
The Z8FMC16100 Series Flash MCU features a two-input, one-output operational amplifier.
General Purpose I/O
The Z8FMC16100 Series Flash MCU features 17 general purpose I/O (GPIO). Each pin is
individually programmable.
Flash Controller
The Flash Controller programs and erases the Flash memory. The Z8FMC16100 Series
Flash MCU products contain 16KB of on-chip Flash memory. A sector protection scheme
allows for flexible protection of user code.
Random Access Memory (RAM)
512B of internal RAM provides storage space for data, variables, and stack operations.
UART with LIN and IrDA
A full-duplex 9-bit UART provides serial, asynchronous communication and supports the
Local Interconnect Network (LIN) serial communications protocol. UART communication is full-duplex and capable of handling asynchronous data transfers. The UARTs support 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver Driver
Enable signal for controlling a multitransceiver bus, such as RS-485. The LIN bus is a
cost-efficient single master, multiple slave organization that supports speeds up to 20K/
bits.
Serial Peripheral Interface
The serial peripheral interface (SPI) allows the Z8 Encore!® to exchange data between
other peripheral devices such as EEPROMs, A/D converters and ISDN devices. The SPI is
a full-duplex, synchronous, character-oriented channel that supports a four-wire interface.
Introduction
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
5
I2C
The inter-integrated circuit (I2C) controller makes the Z8 Encore! compatible with the I2C
protocol. The I2C controller consists of two bidirectional bus lines, a serial data (SDA)
line and a serial clock (SCL) line. The I2C can operate as a master and/or slave and supports multimaster bus arbitration.
Internal Precision Oscillator
The Internal Precision Oscillator (IPO) provides a stable, accurate time base without the
requirement for external components. This can reduce system cost in many applications
by eliminating the requirement for external crystals or ceramic resonators. IPO frequency
is 5.5296MHz.
Crystal Oscillator
The on-chip crystal oscillator features programmable gain to support crystals and ceramic
resonators from 32KHz to 20MHz. The oscillator can also be used with clock drivers.
Standard Timer
The 16-bit reloadable timer can be used for timing/counting events and PWM signal generation. This timer provides a 16-bit programmable reload counter and operate in OneShot, Continuous, Gated, Capture, Compare, Capture and Compare, and PWM modes.
This timer can measure velocity from a tachometer wheel or read sensor outputs for rotor
position for brushless DC motor commutation. The standard timer can also be used for
general purpose timing and counting operations.
Interrupt Controller
The Z8FMC16100 Series Flash MCU products support 3 levels of programmable interrupt
priority. The interrupt sources include internal peripherals, general-purpose I/O pins, and
system fault detection.
Reset Controller
The Z8FMC16100 Series Flash MCU can be reset using the RESET pin, power-on reset,
Watch-Dog Timer (WDT), Stop-Mode Recovery, or Voltage Brown-Out (VBO) warning
signal.
On-Chip Debugger
The Z8FMC16100 Series Flash MCU features an integrated On-Chip Debugger (OCD).
The single-pin OCD interface provides a rich set of debugging capabilities, such as read-
PS024604-1005
PRELIMINARY
I 2C
Z8 Encore!® Motor Control Flash MCUs
Product Specification
6
ing and writing registers, programming the Flash, setting break points and executing code.
OCD simplifies code development and allows easy in-circuit programming.
Introduction
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
7
Signal and Pin Descriptions
The Z8FMC16100 Series Flash MCU products are available in a variety of package styles
and pin configurations. This chapter describes the signals and available pin configurations
for each of the package styles. For information regarding the physical package specifications, please refer to the Packaging chapter on page 301.
PS024604-1005
PRELIMINARY
Z8 Encore!® Motor Control Flash MCUs
Product Specification
8
Pin Configurations
PB3/ANA3/OPOUT
PB4/ANA4/CINN
PB5/ANA5
PB6/ANA6
PB7/ANA7
PA6/CTS/SS /SDA
PA5/TXD/MOSI
PA4/RXD/MISO
32
31
30
29
28
27
26
25
Figure 2 illustrates the pin configuration for the packages available in the Z8FMC16100
Series Flash MCU. Refer to Table 1 for a description of the signals.
XOUT
AVSS
5
20
VSS
VREF
6
19
PWM0h
PA0/OPINN
7
18
PWM0L
PA1/OPINP/CINN
8
17
PWM1H
PA2/CINP
16
21
PWM1L
4
15
AVDD
PWM2H
XIN
14
22
PWM2L
3
13
PB0/ANA0/T0IN0
PC0/T0OUT
VDD
12
23
DBG
2
11
PB1/ANA1/T0IN1
RESET/FAULT0
PA3/TXDE/SCK /SCL
10
24
PA7/FAULT1/T0OUT/ COMPOUT
1
9
PB2/ANA2/T0IN2
Figure 2. Z8FMC16100 Series Flash MCU in 32-Pin QFN and LQFP Package
Signal and Pin Descriptions
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
9
Signal Descriptions
This section describes the Z8FMC16100 Series Flash MCU signals.
Table 1. Signal Descriptions
Signal Mnemonic
I/O
Description
General-Purpose I/O Ports A-H
PA[7:0]
I/O
Port A[7:0]. These pins are used for general-purpose I/O.
PB[7:0]
I/O
Port B[7:0]. These pins are used for general-purpose I/O.
PC[0]
I/O
Port C[0]. These pins are used for general-purpose I/O.
Pulse-Width Modulator for Motor Control
PWM0h/PWM1H
PWM2H
O
PWM High output.
PWM0L/PWM1L
PWM2L
O
PWM Low output.
FAULT0/FAULT1
I
PWM FAULT condition input. FAULT0 is active low, FAULT1 is active
high
SPI
MISO
I/O
Master In, Slave Out
MOSI
I/O
Master Out, Slave In.
SCLK
I/O
SPI Clock.
SS
I
Slave Select
T0OUT, T0OUT
O
General-Purpose Timer Outputs.
T0INx
I
General-Purpose Timer Input. This signal is used as the capture, gating
and counter inputs.
TXD
O
Transmit Data. This signal is the transmit output from the UART and
IrDA.
RXD
I
Receive Data. This signal is the receiver input for the UART and IrDA.
CTS
I
Clear To Send signal from the receiving device that ready to receive
data.
TXDE
O
Driver Enable. This signal allows automatic control of external RS-485
drivers. The DE signal may be used to ensure an external RS-485 driver
is enabled when data is transmitted by the UART.
Timers
UART Controller
PS024604-1005
PRELIMINARY
Signal Descriptions
Z8 Encore!® Motor Control Flash MCUs
Product Specification
10
Table 1. Signal Descriptions (Continued)
Signal Mnemonic
I/O
Description
Analog
ANA[7:0]
VREF
I
Analog Input. These signals are inputs to the analog-to-digital converter
(ADC).
I/O
Voltage buffer output. This signal provides reference voltage for external
components.
Caution
If using the internal reference voltage generator, a 10 µF capacitor must
be placed on this pin to Ground.
CINP
I
Comparator positive input.
CINN
I
Comparator negative input.
COMPOUT
O
Comparator output.
OPINP
I
Operational amplifier positive input.
OPINN
I
Operational amplifier negative input.
OPOUT
O
Operational amplifier output.
XIN
I
The External Crystal Input is the input pin to the crystal oscillator. A
crystal can be connected between it and the XOUT pin to form the
oscillator. In addition, this pin is used with external RC networks or
external clock drivers to provide the system clock.
XOUT
O
External Crystal Output. This pin is the output of the crystal oscillator. A
crystal can be connected between it and the XIN pin to form the oscillator.
This pin must be left unconnected when not using a crystal.
I/O
Debug. This open-drain pin provides the single-pin control and data
interface to the On-Chip Debugger. For operation of the On-chip
Debugger, all power pins (VDD) must be supplied with power, and all
ground pins (VSS) must be grounded.
Oscillators
On-Chip Debugger
DBG
Caution
This pin is open-drain and must have an external pull-up resistor to
ensure proper operation.
Reset-PWM Fault
RESET/FAULT0
I/O
Signal and Pin Descriptions
RESET input pin generates a Reset or PWM fault when asserted (driven
Low). The function selection is determined by the FLTSEL bit of the User
Options Bits at Program Memory Address 0001h, and the FAULTSEL bit
in the Reset Status and Control Register.
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
11
Table 1. Signal Descriptions (Continued)
Signal Mnemonic
I/O
Description
Power Supply
VDD , AVDD
I
Power Supply.
VSS , AVSS
I
Ground.
Pin Characteristics
Table 2 lists the characteristics for each of the Z8FMC16100 Series Flash MCU’s 32 pins.
Data in Table 2 is sorted alphabetically by the pin symbol mnemonic.
Table 2. Pin Characteristics of the Z8FMC16100 Series Flash MCU
Symbol
Mnemonic
Reset
Direction Direction
Active Low
or
Active High
Tri-State
Output
Internal Pullup
or Pull-down
Schmitt
Trigger
Input
Open Drain
Output
DBG
I/O
I
N/A
Yes
Pull-up
Yes
Yes
PA[7:0]
I/O
I
N/A
Yes
Pull-up,
Programmable
Yes
Yes,
Programmable
PB[7:0]
I/O
I
N/A
Yes
Pull-up,
Programmable
Yes
Yes,
Programmable
PC[0]
I/O
I
N/A
Yes
Pull-up,
Programmable
Yes
Yes,
Programmable
PWMxH
I/O
Tristate
N/A
Yes
No
Yes
No
PWMxL
I/O
Tristate
N/A
Yes
No
Yes
No
RESET
I
I
Low
N/A
Pull-up
Yes
N/A
XIN
I
I
N/A
N/A
No
No
N/A
I/O
I
N/A
Yes
N/A
N/A
N/A
VDD, AVDD
Supply
N/A
N/A
N/A
No
No
N/A
VSS, AVSS
Supply
N/A
N/A
N/A
No
No
N/A
VREF
Note: x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer.
PS024604-1005
PRELIMINARY
Pin Characteristics
Z8 Encore!® Motor Control Flash MCUs
Product Specification
12
Signal and Pin Descriptions
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
13
Address Space
The eZ8 CPU can access three distinct address spaces:
•
The Register File contains addresses for the general-purpose registers and the eZ8
CPU, peripheral, and general-purpose I/O port control registers.
•
The Program Memory contains addresses for all memory locations having executable
code and/or data.
•
The Data Memory contains addresses for all memory locations that hold data only.
These three address spaces are covered briefly in the following subsections. For more
detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU
User Manual (UM0128), available for download at www.zilog.com.
Register File
The Z8FMC16100 Series Flash MCU supports up to 512B of internal RAM within the
Register File address space. The Register File is composed of two sections—control registers and general-purpose registers (RAM). When instructions are executed, registers are
read from when defined as sources and written to when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose registers to function as accumulators,
address pointers, index registers, stack areas, or scratch pad memory.
The upper 256 bytes of the 4KB Register File address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00h to FFFh. Some of the addresses within the 256-byte control register
section are reserved (unavailable). Reading from an reserved Register File addresses
returns an undefined value.
Caution: Writing to reserved Register File addresses is not recommended and can produce unpredictable results.
The on-chip RAM always begins at address 000h in the Register File address space. The
Z8FMC16100 Series Flash MCU devices provide 512B of on-chip RAM depending upon
the device. Reading from Register File addresses outside the available RAM addresses
(and not within the control register address space) returns an undefined value. Writing to
these Register File addresses produces no effect. See the Ordering Information for the
Z8FMC16100 Series Products* section on page 303 to determine the amount of RAM
available for the specific Z8FMC16100 Series Flash MCU device.
PS024604-1005
PRELIMINARY
Register File
Z8 Encore!® Motor Control Flash MCUs
Product Specification
14
Program Memory
The Z8FMC16100 Series Flash MCU products contain 16 KB of on-chip Flash memory in
the Program Memory address space, depending upon the device (FMC08100 has 8 KB
and FMC04100 has 4 KB). Reading from Program Memory addresses outside the available Flash memory addresses returns FFh. Writing to these unimplemented Program
Memory addresses produces no effect. Table 3 describes the Program Memory Maps for
the Z8FMC16100 Series Flash MCU products.
Table 3. Z8FMC16100 Series Flash MCU Program Memory Maps
Program Memory Address (Hex)
Function
Z8FMC16000 Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0007
System Exception Vectors
0008-003F
Interrupt Vectors
0040-3FFF
Program Memory
Note: See Table 29 on page 52 for a list of the interrupt vectors.
Data Memory
The Z8FMC16100 Series Flash MCU does not use the eZ8 CPU’s 64KB Data Memory
address space.
Information Area
Table 4 describes the Z8FMC16100 Series Flash MCU Information Area. This 512-byte
Information Area is accessed by setting bit 7 of the Flash Page Select Register to 1. When
access is enabled, the Information Area is mapped into the Program Memory and overlays
the 512 bytes at addresses FE00h to FFFFh. When the Information Area access is enabled,
execution of LDC and LDCI instruction from these Program Memory addresses return the
Information Area data rather than the Program Memory data. Reads of these addresses
through the On-Chip Debugger also returns the Information Area data. Execution of code
from these addresses continues to correctly use the Program Memory. Access to the Information Area is read-only.
Address Space
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
15
Table 4. Z8FMC16100 Series Information Area Map
PS024604-1005
Program Memory Address (Hex)
Function
FE00h–FE3Fh
Reserved.
FE40h–FE5Fh
Part Number
20-character ASCII alphanumeric code
Left justified and filled with zeros (ASCII Null
character).
FE60h–FFFFh
Reserved.
PRELIMINARY
Information Area
Z8 Encore!® Motor Control Flash MCUs
Product Specification
16
Address Space
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
17
Register File Address Map
Table 5 provides the address map for the Register File of the Z8FMC16100 Series Flash
MCU.
Table 5. Register File Address Map
Address
(Hex)
Register Description
Mnemonic
Reset (Hex)
Page #
13
General Purpose RAM—Z8FMC16 devices with 512B On-Chip RAM
000–1FF
General-Purpose Register File RAM
—
XX
200–EFF
Reserved
—
XX
Timer 0
F00
Timer 0 High Byte Register (T0H)
T0H
00
103
F01
Timer 0 Low Byte Register (T0L)
T0L
01
103
F02
Timer 0 Reload High Byte Register (T0RH)
T0RH
FF
104
F03
Timer 0 Reload Low Byte Register (T0RL)
T0RL
FF
104
F04
Timer 0 PWM High Byte Register (T0PWMH)
T0PWMH
00
105
F05
Timer 0 PWM Low Byte Register (T0PWML)
T0PWML
00
105
F06
Timer 0 Control 0 Register (T0CTL0)
T0CTL0
00
106
F07
Timer 0 Control 1 Register (T0CTL1)
T0CTL1
00
107
F08
ADC Timer 0 Capture Register, High Byte
ADCTCAP_H
XX
208
F09
ADC Timer 0 Capture Register, Low Byte
ADCTCAP_L
XX
209
F0A–F1F
Reserved
—
XX
Pulse-Width Modulator
F20
PWM Control 0 Register
PWMCTL0
00
78
F21
PWM Control 1 Register
PWMCTL1
00
80
F22
PWM Deadband Register
PWMDB
00
81
F23
PWM Minimum Pulse Width Filter
PWMMPF
00
82
F24
PWM Fault Mask Register
PWMFM
00
82
F25
PWM Fault Status Register
PWMFSTAT
X0X0-0XXXb
83
Note: XX = undefined.
PS024604-1005
PRELIMINARY
Z8 Encore!® Motor Control Flash MCUs
Product Specification
18
Table 5. Register File Address Map (Continued)
Address
(Hex)
Register Description
F26
PWM Input Sample Register
F27
Mnemonic
Reset (Hex)
Page #
PWMIN
00
86
PWM Output Control Register
PWMOUT
00
87
F28
PWM Fault Control Register
PWMFCTL
00
85
F29
Current Sense ADC Trigger Control Register
PWMSHC
00
87
F2A–B
Reserved
—
XX
F2C
PWM High Byte Register (PWMH)
PWMH
00
75
F2D
PWM Low Byte Register (PWML)
PWML
00
76
F2E
PWM Reload High Byte Register (PWMRH)
PWMRH
0F
76
F2F
PWM Reload Low Byte Register (PWMRL)
PWMRL
FF
77
F30
PWM 0 High Side Duty Cycle High Byte
PWMH0Dh
00
77
F31
PWM 0 High Side Duty Cycle Low Byte
PWMH0DL
00
78
F32
PWM 0 Low Side Duty Cycle High Byte
PWML0Dh
00
77
F33
PWM 0 Low Side Duty Cycle Low Byte
PWML0DL
00
78
F34
PWM 1 High Side Duty Cycle High Byte
PWMH1DH
00
77
F35
PWM 1 High Side Duty Cycle Low Byte
PWMH1DL
00
78
F36
PWM 1 Low Side Duty Cycle High Byte
PWML1DH
00
77
F37
PWM 1 Low Side Duty Cycle Low Byte
PWML1DL
00
78
F38
PWM 2 High Side Duty Cycle High Byte
PWMH2DH
00
77
F39
PWM 2 High Side Duty Cycle Low Byte
PWMH2DL
00
78
F3A
PWM 2 Low Side Duty Cycle High Byte
PWML2DH
00
77
F3B
PWM 2 Low Side Duty Cycle Low Byte
PWML2DL
00
78
F3C–F3F
Reserved
—
XX
Note: XX = undefined.
Register File Address Map
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
19
Table 5. Register File Address Map (Continued)
Address
(Hex)
Register Description
Mnemonic
Reset (Hex)
Page #
LIN-UART Transmit Data Register
U0TXD
XX
130
LIN-UART Receive Data Register
U0RXD
XX
130
LIN-UART
F40
F41
LIN-UART Status 0 Register
U0STAT0
0000_011Xb
131
F42
LIN-UART Control 0 Register
U0CTL0
00
134
F43
LIN-UART Control 1
U0CTL1
00
136
F44
LIN-UART Mode Select and Status
U0MDSTAT
00
133
F45
LIN-UART Address Compare
U0ADDR
00
140
F46
LIN-UART Baud Rate High Byte
U0BRH
FF
140
F47
LIN-UART Baud Rate Low Byte
U0BRL
FF
141
F48–F5F
Reserved
—
XX
I 2C
F50
I2C Data Register
I2CDATA
00
184
F51
I2C Interrupt Status Register
I2CISTAT
80
184
F52
I2C Control Register
I2CCTL
00
186
F53
I2C Baud Rate High Byte Register (I2CBRH)
I2CBRH
FF
188
F54
I2C Baud Rate Low Byte Register (I2CBRL)
I2CBRL
FF
188
F55
I2C State Register (I2CSTATE) - Description
when DIAG = 0
I2CSTATE
0X
189
I2C State Register (I2CSTATE) - Description
when DIAG = 1
I2CSTATE
00
190
F56
I2C Mode Register
I2CMODE
00
192
F57
I2C Slave Address Register
I2CSLVAD
00
193
F58–F5F
Reserved
—
XX
SPIDATA
XX
157
SPI
F60
SPI Data Register
F61
SPI Control Register
SPICTL
00
158
F62
SPI Status Register
SPISTAT
01
159
Note: XX = undefined.
PS024604-1005
PRELIMINARY
Z8 Encore!® Motor Control Flash MCUs
Product Specification
20
Table 5. Register File Address Map (Continued)
Address
(Hex)
Register Description
Mnemonic
Reset (Hex)
Page #
F63
SPI Mode Register
SPIMODE
00
160
F64
SPI Diagnostic State Register
SPIDST
00
161
F65
Reserved
—
XX
F66
SPI Baud Rate High Byte Register (SPIBRH)
SPIBRH
FF
162
F67
SPI Baud Rate Low Byte Register (SPIBRL)
SPIBRL
FF
162
F68–F6F
Reserved
—
XX
Analog-to-Digital Converter (ADC)
F70
ADC Control Register 0
ADCCTL0
20
203
F71
ADC Raw Data High Byte Register
ADCRD_H
XX
204
F72
ADC Data High Byte Register
ADCD_H
XX
204
F73
ADC Data Low Bits Register
ADCD_L
XX
205
F74
Sample Settling Time Register
ADCSST
1F
206
F75
Sample Time Register
ADCST
A0
206
F76
ADC Clock Prescale Register
ADCCP
00
207
F77–F85
Reserved
—
XX
Oscillator Control
F86
Oscillator Control Register
OSCCTL
A0
233
F87
Oscillator Divide Register
OSCDIV
00
234
—
XX
CMPOPC
00
—
XX
IRQ0
00
55
Trim Control
F88–F8F
Reserved
Comparator and Op Amp
F90
Comparator and Op Amp Control Register
F91–FBF
Reserved
197
Interrupt Controller
FC0
Interrupt Request 0 Register
FC1
IRQ0 Enable High Bit Register (IRQ0ENH)
IRQ0ENH
00
58
FC2
IRQ0 Enable Low Bit Register (IRQ0ENL)
IRQ0ENL
00
59
Note: XX = undefined.
Register File Address Map
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
21
Table 5. Register File Address Map (Continued)
Address
(Hex)
Register Description
FC3
Interrupt Request 1 Register
FC4
FC5
Mnemonic
Reset (Hex)
Page #
IRQ1
00
57
IRQ1 Enable High Bit Register (IRQ1ENH)
IRQ1ENH
00
60
IRQ1 Enable Low Bit Register (IRQ1ENL)
IRQ1ENL
00
60
—
XX
IRQCTL
00
61
FC9–FCE Reserved
FCF
Interrupt Control Register
GPIO Port A
FD0
Port A Address
PAADDR
00
40
FD1
Port A Control
PACTL
00
41
FD2
Port A Input Data
PAIN
XX
48
FD3
Port A Output Data
PAOUT
00
49
GPIO Port B
FD4
Port B Address
PBADDR
00
40
FD5
Port B Control
PBCTL
00
41
FD6
Port B Input Data
PBIN
XX
48
FD7
Port B Output Data
PBOUT
00
49
GPIO Port C
FD8
Port C Address
PCADDR
00
40
FD9
Port C Control
PCCTL
00
41
FDA
Port C Input Data
PCIN
XX
48
FDB
Port C Output Data
PCOUT
00
49
RSTSTAT
see Table 10
29
—
XX
Reset and Watch-Dog Timer (WDT)
FF0
Reset Status and Control Register
FF1
Reserved
FF2
Watch-Dog Timer Reload High Byte Register
(WDTH)
WDTH
04
66
FF3
Watch-Dog Timer Reload Low Byte Register
(WDTL)
WDTL
00
66
FF4–FF5
Reserved
—
XX
Note: XX = undefined.
PS024604-1005
PRELIMINARY
Z8 Encore!® Motor Control Flash MCUs
Product Specification
22
Table 5. Register File Address Map (Continued)
Address
(Hex)
Register Description
Mnemonic
Reset (Hex)
Page #
TRMADR
00
227
TRMDR
00
227
Trim
FF6
Trim Bit Address Register
FF7
Trim Bit Data Register
Flash Memory Controller
FF8
Flash Control Register
FCTL
00
217
FF8
Flash Status Register
FSTAT
00
218
FF9
Flash Page Select Register
FPS
00
218
FF9 (if
enabled)
Flash Sector Protect Register
FPROT
00
219
FFA
Flash Frequency High Byte Register
(FFREQH)
FFREQH
00
220
FFB
Flash Frequency Low Byte Register (FFREQL)
FFREQL
00
221
FLAGS
XX
RP
XX
Refer to the
eZ8 CPU
User Manual
(UM0128).
eZ8 CPU
FFC
Flags
FFD
Register Pointer
FFE
Stack Pointer High Byte
SPH
XX
FFF
Stack Pointer Low Byte
SPL
XX
Note: XX = undefined.
Register File Address Map
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
23
Reset and Stop-Mode Recovery
The Reset Controller within the Z8FMC16100 Series Flash MCU controls RESET and
Stop-Mode Recovery operation. In typical operation, the following events cause a RESET
to occur:
•
•
•
Power-On Reset (POR)
•
•
•
External RESET pin assertion
Voltage Brown-Out (VBO)
Watch-Dog Timer time-out (when configured via the WDT_RES Option Bit to initiate a
Reset)
On-Chip Debugger initiated RESET (OCDCTL[0] set to 1)
Fault detect logic
When the Z8FMC16100 Series Flash MCU is in STOP mode, a Stop-Mode Recovery is
initiated by either of the following:
•
•
Watch-Dog Timer time-out
GPIO port input pin transition on an enabled Stop-Mode Recovery source
Reset Types
The Z8FMC16100 Series Flash MCU provides two different types of reset operation (System Reset and Stop-Mode Recovery). The type of reset is a function of both the current
operating mode of the Z8FMC16100 Series Flash MCU and the source of the reset. Table
6 lists the types of reset and their operating characteristics.
Table 6. Reset and Stop-Mode Recovery Characteristics and Latency
Reset Characteristics and Latency
Reset Type
Peripheral Control
Registers
eZ8 CPU Reset Latency (Delay)
System Reset
Reset (as
applicable)
RESET
A minimum of 66 Internal Precision Oscillator cycles.
Stop-Mode
Recovery
Unaffected, except
RSTSRC and
OSCCTL registers
Reset
A minimum of 66 Internal Precision Oscillator cycles.
PS024604-1005
PRELIMINARY
Reset Types
Z8 Encore!® Motor Control Flash MCUs
Product Specification
24
System Reset
During a system reset, the Z8FMC16100 Series Flash MCU is held in RESET for 66
cycles of the Internal Precision Oscillator. At the beginning of RESET, all GPIO pins are
configured as inputs. All GPIO programmable pull-ups are disabled.
At the start of a System Reset, the motor control PWM outputs are forced to high-impedance momentarily. When the Option Bits that control the off-state have been properly
evaluated the PWM outputs are forced to the programmed off-state.
During RESET, the eZ8 CPU and on-chip peripherals are idle; however, the Internal Precision Oscillator and Watch-Dog Timer oscillator continue to run. During the first 50 clock
cycles the internal option bit registers are initialized, after which the system clock for the
core and peripherals begins operating. The eZ8 CPU and on-chip peripherals remain idle
through the next 16 cycles of the system clock after which time the internal reset signal is
deasserted.
Upon RESET, control registers within the Register File that have a defined reset value are
loaded with their reset values. Other control registers (including the Flags) and generalpurpose RAM are undefined following RESET. The eZ8 CPU fetches the RESET vector
at Program Memory addresses 0002h and 0003h and loads that value into the Program
Counter. Program execution begins at the RESET vector address.
Table 7 lists the system reset sources as a function of the operating mode. The text following provides more detailed information on the individual RESET sources. Please note that
a Power-On Reset/Voltage Brown-Out event always has priority over all other possible
reset sources to ensure a full system reset occurs.
Table 7. System Reset Sources and Resulting Reset Action
Operating Mode System Reset Source
Action
Normal or HALT
modes
Power-On Reset/Voltage Brown-Out
System Reset.
Watch-Dog Timer time-out when
configured for reset.
System Reset.
RESET pin assertion.
System Reset.
Write OCDCTL[0] to 1.
System Reset except the On-Chip
Debugger is not reset.
Fault detect logic reset.
System Reset.
Power-On Reset/Voltage Brown-Out.
System Reset.
RESET pin assertion.
System Reset.
Fault detect logic reset.
System Reset.
STOP mode
Reset and Stop-Mode Recovery
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
25
Power-On Reset
Each device in the Z8FMC16100 Series Flash MCU contains an internal Power-On Reset
(POR) circuit. The POR circuit monitors the supply voltage and holds the device in the
Reset state until the supply voltage reaches a safe operating level. After the supply voltage
exceeds the POR voltage threshold (VPOR) and has stabilized, the POR Counter is enabled
and counts 50 cycles of the Internal Precision Oscillator. At this point the System Clock is
enabled and the POR Counter counts a total of 16 system clock pulses. The device is held
in the Reset state until this second POR Counter sequence has timed out. After the
Z8FMC16100 Series Flash MCU exits the Power-On Reset state, the eZ8 CPU fetches the
Reset vector. Following Power-On Reset, the POR status bit in the Reset Status and Control Register is set to 1.
Figure 3 illustrates Power-On Reset operation. Refer to the On-Chip Peripheral AC and
DC Electrical Characteristics section on page 265 for the POR threshold voltage
(VPOR).
VCC = 3.3V
VPOR
VVBO
Program Execution
VCC = 0.0V
System Clock
Internal Precision
Oscillator
Oscillator
Startup
Internal RESET
Signal
Option Bit
Counter Delay
System Clock
Counter Delay
Figure 3. Power-On Reset Operation
Voltage Brown-Out Reset
The Z8FMC16100 Series Flash MCU provides low Voltage Brown-Out (VBO) protection.
The VBO circuit senses when the supply voltage drops to an unsafe level (below the VBO
PS024604-1005
PRELIMINARY
Power-On Reset
Z8 Encore!® Motor Control Flash MCUs
Product Specification
26
threshold voltage) and forces the device into the Reset state. While the supply voltage
remains below the Power-On Reset voltage threshold (VPOR), the VBO holds the device in
the Reset state.
After the supply voltage again exceeds the Power-On Reset voltage threshold and stabilized, the device progresses through a full System Reset sequence, as described in the
Power-On Reset section. Following Power-On Reset, the POR status bit in the Reset
Source register is set to 1. Figure 4 illustrates Voltage Brown-Out operation. Refer to the
On-Chip Peripheral AC and DC Electrical Characteristics section on page 265 for the
VBO and POR threshold voltages (VVBO and VPOR).
The Voltage Brown-Out circuit can be either enabled or disabled during STOP mode.
Operation during STOP mode is controlled by the VBO_AO Option Bit. Refer to the Option
Bits chapter for information on configuring VBO_AO.
VCC = 3.3V
VCC = 3.3V
VPOR
VVBO
Program
Execution
Voltage
Brown-Out
Program Execution
System Clock
Internal Precision
Oscillator
Internal RESET
Signal
Option Bit
Counter Delay
System Clock
Counter Delay
Figure 4. Voltage Brown-Out Reset Operation
Watch-Dog Timer Reset
If the device is in normal or HALT mode, the Watch-Dog Timer can initiate a System
Reset at time-out if the WDT_RES Option Bit is set to 1. This setting is the default (unprogrammed) setting of the WDT_RES Option Bit. The WDT status bit in the Reset Status and
Control Register is set to signify that the reset was initiated by the Watch-Dog Timer.
Reset and Stop-Mode Recovery
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
27
External Pin Reset
The input-only RESET pin has a Schmitt-triggered input, an internal pull-up, an analog
filter and a digital filter to reject noise. Once the RESET pin is asserted for at least 4 system clock cycles, the device progresses through the System Reset sequence. While the
RESET input pin is asserted Low, the Z8FMC16100 Series Flash MCU device continues
to be held in the Reset state. If the RESET pin is held Low beyond the System Reset timeout, the device exits the Reset state 16 system clock cycles following RESET pin deassertion. If the RESET pin is released before the System Reset time-out, the RESET pin is
driven Low by the chip until the completion of the time-out as described in the next section. In STOP mode the digital filter is bypassed because the System Clock is disabled.
Following a System Reset initiated by the external RESET pin, the EXT status bit in the
Reset Status and Control Register is set to 1.
External Reset Indicator
During System Reset, the RESET pin functions as an open drain (active Low) reset mode
indicator in addition to the input functionality. This reset output feature allows a
Z8FMC16100 Series Flash MCU device to reset other components to which it is connected, even if the reset is caused by internal sources such as POR, VBO, or WDT events
and as an indication of when the reset sequence completes.
Once an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in Table 6 has elapsed.
On-Chip Debugger Initiated Reset
A System Reset may be initiated via the On-Chip Debugger by setting RST bit of the
OCDCTL register. The On-Chip Debugger is not reset but the rest of the chip goes
through a normal system reset. The RST bit automatically clears during the system reset.
Following the system reset, the POR bit in the Reset Status and Control Register is set.
Fault Detect Logic Reset
Fault detect circuitry exists to detect illegal state changes which may be caused by transient power or electrostatic discharge events. When such a fault is detected, a system reset
is forced. Following the system reset, the FLTD bit in the Reset Status and Control Register
is set.
PS024604-1005
PRELIMINARY
External Pin Reset
Z8 Encore!® Motor Control Flash MCUs
Product Specification
28
Stop-Mode Recovery
STOP mode is entered by execution of a STOP instruction by the eZ8 CPU. Refer to the
Low-Power Modes chapter on page 31 for detailed STOP mode information. During StopMode Recovery, the device is held in reset for 66 cycles of the Internal Precision Oscillator. Stop-Mode Recovery only affects the contents of the Reset Status and Control Register and Oscillator Control Register. Stop-Mode Recovery does not affect any other values
in the Register File, including the Stack Pointer, Register Pointer, Flags, peripheral control
registers, and general-purpose RAM.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002h and 0003h
and loads that value into the Program Counter. Program execution begins at the Reset vector address. Following Stop-Mode Recovery, the STOP bit in the Reset Status and Control
Register is set to 1. Table 8 lists the Stop-Mode Recovery sources and resulting actions.
The text following provides more detailed information on each of the Stop-Mode Recovery sources
Table 8. Stop-Mode Recovery Sources and Resulting Action
Operating Mode
Stop-Mode Recovery Source
Action
Stop Mode
Watch-Dog Timer time-out when
configured for Reset
Stop-Mode Recovery
Watch-Dog Timer time-out when
configured for System Exception
Stop-Mode Recovery followed by WDT
System Exception
Data transition on any GPIO port pin
enabled as a Stop-Mode Recovery
source
Stop-Mode Recovery
Stop-Mode Recovery Using Watch-Dog Timer Time-Out
If the Watch-Dog Timer times out during STOP mode, the device undergoes a Stop-Mode
Recovery sequence. In the Reset Status and Control Register, the WDT and STOP bits are
set to 1. If the Watch-Dog Timer is configured to generate a System Exception upon timeout, the eZ8 CPU services the Watch-Dog Timer System Exception following the normal
Stop-Mode Recovery sequence.
Stop-Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO port pins may be configured as a Stop-Mode Recovery input source. On
any GPIO pin enabled as a Stop-Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop-Mode Recovery. The GPIO StopMode Recovery signals are filtered to reject pulses less than 10ns (typical) in duration. In
the Reset Status and Control Register, the STOP bit is set to 1.
Reset and Stop-Mode Recovery
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Caution: Short pulses on the Port pin can initiate Stop-Mode Recovery without initiating an interrupt (if enabled for that pin).
PWM Fault0 and Reset pin selection
The RESET pin can be set to function as a PWM Fault input. When selected, the RESET
input function is disabled. The FLTSEL bit in the Reset Status and Control Register allows
software selection of the RESET pin function. The pin function is selected by writing the
the unlock sequence followed by the mode to this register. A software write to the FLTSEL
bit will override the value set by the FLTSEL user option bit
Reset Control Register Definitions
Writing the 14h, 92h unlock sequence to the Reset Status and Control Register address
unlocks access to the FLTSEL bit. The locking mechanism prevents spurious writes to this
bit. The following sequence is required to unlock this register and write the FLTSEL bit.
1. Write 14h to the Reset Status and Control Register (RSTSTAT).
2. Write 92h to the Reset Status and Control Register (RSTSTAT).
3. Write the FLTSEL bit.
All steps of the unlock sequence must be written in the order listed.
Reset Status and Control Register
The Reset Status (RSTSTAT) Register, shown in Table 9, records the cause of the most
recent Reset or Stop-Mode Recovery. All status bits are updated on each Reset or StopMode Recovery event. Table 10 indicates the possible states of the Reset status bits following a Reset or Stop-Mode Recovery event. The RESET pin function is also select with
FLTSEL bit.
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Table 9. Reset Status and Control Register (RSTSCR)
BITS
7
6
5
4
3
FIELD
POR
STOP
WDT
EXT
FLT
1
0
Reserved
FLTSEL
See Table 10 below
RESET
R/W
2
R
R
R
0
R
R
R
R/W
FF0H
ADDR
The FLTSEL bit in this register allows software selection of the RESET pin. The pin function is selected by writing the unlock sequence followed by the mode to this register. A
software write to the FLTSEL bit will override the value set by the FLTSEL user option bit.
0 = RESET/Fault0 pin is configured as RESET input.
1= RESET/Fault0 pin is configured as Fault0 input.
Table 10. Reset Status Register Values Following Reset
Reset or Stop-Mode Recovery Event
POR
STOP
WDT
EXT
FLT
Power-On Reset
1
0
0
0
0
Reset using RESET pin assertion
0
0
0
1
0
Reset using Watch-Dog Timer time-out
0
0
1
1
0
Reset by OCD writing OCDCTL[0] to 1
1
0
0
1
0
Reset from Fault Detect Logic
0
0
0
1
1
Stop-Mode Recovery using GPIO pin transition
0
1
0
0
0
Stop-Mode Recovery using Watch-Dog Timer time-out
0
1
1
0
0
Note: Additional bits may be set depending on the number of resets simultaneously occurring.
Reset and Stop-Mode Recovery
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Low-Power Modes
The Z8FMC16100 Series Flash MCU products contain power-saving features. The highest level of power reduction is provided by STOP mode. The next level of power reduction
is provided by the HALT mode.
Stop Mode
Execution of the eZ8 CPU’s STOP instruction places the Z8FMC16100 Series Flash MCU
into STOP mode. In STOP mode, the operating characteristics are:
•
•
•
•
•
Primary crystal oscillator and IPO are stopped; XIN and XOUT pins are driven to VSS.
•
If enabled for operation in STOP mode through the associated Option Bit, the Voltage
Brown-Out protection circuit continues to operate.
•
•
Comparators and voltage reference operate unless disabled.
System clock is stopped
eZ8 CPU is stopped
Program counter (PC) stops incrementing
If enabled for operation during STOP mode, the Watch-Dog Timer and its internal RC
oscillator continue to operate.
All other on-chip peripherals are idle
To minimize current in STOP mode, all GPIO pins that are configured as digital inputs
must be driven to one of the supply rails (VCC or GND), the Voltage Brown-Out protection
and the Watch-Dog Timer must be disabled. The device can be brought out of STOP mode
using Stop-Mode Recovery. For more information refer to the Reset and Stop-Mode
Recovery chapter on page 23.
Caution: To prevent excess current consumption, STOP mode must not be used if the device is
driven with an external clock source.
Halt Mode
Execution of the eZ8 CPU’s HALT instruction places the device into HALT mode. In
HALT mode, the operating characteristics are:
•
PS024604-1005
Primary crystal oscillator is enabled and continues to operate
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Stop Mode
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•
•
•
•
•
•
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watch-Dog Timer’s internal RC oscillator continues to operate
If enabled, the Watch-Dog Timer continues to operate
All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
•
•
•
•
•
•
Interrupt or System Exception
Watch-Dog Timer time-out (System Exception or reset)
Power-on reset
Voltage-brown out reset
External RESET pin assertion
Halt Mode Recovery time is less than 5 µs.
To minimize current in HALT mode, all GPIO pins which are configured as inputs must be
driven to one of the supply rails (VCC or GND).
Peripheral-Level Power Control
In addition to the STOP and HALT modes, it is possible to disable unused on-chip analog
peripherals of the Z8FMC16100 Series Flash MCU device during operation. Disabling an
unused analog peripheral minimizes power consumption. Power consumption of the
unused on-chip digital peripherals is automatically minimized when not in use.
Low-Power Modes
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Power Control Register 0
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block.
Table 11. Power Control Register 0(PWRCTL0)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
Reserved
Reserved
VBODIS
Reserved
Reserved
Reserved
Reserved
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F80H
ADDR
Bit
Position
Value
(H)
Description
[7:5]
Reserved
Must be 0.
[4]
VBODIS
0
Voltage Brownout Detector Disable
(This bit and the VBO_AO Option Bit must be enabled for the VBO to be active.
Voltage Brownout Detector is enabled.
1
Voltage Brownout Detector is disabled.
[3:0]
Reserved
PS024604-1005
Must be 0.
PRELIMINARY
Power Control Register 0
Z8 Encore!® Motor Control Flash MCUs
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Low-Power Modes
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General-Purpose I/O
The Z8FMC16100 Series Flash MCU contains general-purpose input/output pins (GPIO)
arranged as Ports A–C. Each port contains control and data registers. The GPIO control
registers are used to determine data direction, open-drain, output drive current, pull-up,
and alternate pin functions. Each port pin is individually programmable.
GPIO Port Availability By Device
Table 12 lists the port pins available with each device and package type.
Table 12. Port Availability by Device and Package Type
Package
Port A
Port B
Port C
32-pin
[7:0]
[7:0]
[0]
Architecture
Figure 5 illustrates a simplified block diagram of a GPIO port pin. In this figure, the ability to accommodate alternate functions and variable port current drive strength are not
illustrated.
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VDD
Pull-Up Enable
On-Chip
Peripheral
Alternate Function
Digital Input
Port Input
Data Register
Q
Analog In/Out
Schmitt Trigger
D
System Clock
Port Output Control
Port Output
Data Register
Data Bus
D
Q
Port
Pin
System Clock
Port Data Direction
GND
Figure 5. GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins can be used as both general-purpose I/O and to provide access
to on-chip peripheral functions, such as timers and serial communication devices. The Port
A-C Alternate Function subregisters configure these pins for either general-purpose I/O or
alternate function operation. When a pin is configured for alternate function, control of the
port pin direction (input/output) is passed from the Port A-C Data Direction registers to
the alternate function assigned to this pin. For peripherals with digital input alternate functions (for example, a Timer input T0IN0), selecting the alternate function is not required.
Table 13 lists the alternate functions associated with each port pin and the required alternate function (AF0 and AF1) subregister settings. In general, enabling an analog alternate
General-Purpose I/O
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function automatically disables the digital Schmitt-trigger input for the associated port
input.
Table 13. Port Alternate Function Mapping
Port
Pin
Mnemonic
Port A
PA7
PA7
0
0
GPIO.
T0OUT
0
1
Timer 0 output (active Low).
FAULT1
1
0
Fault Input.
COMPOUT
1
1
Comparator output.
PA6
0
0
GPIO.
SS
0
1
SPI Slave Select.
CTS
1
0
UART Clear to Send.
SDA
1
1
I2C Serial Data.
PA5
0
0
GPIO.
MOSI
0
1
SPI Master Out Slave In.
TXD
1
0
UART Transmit data.
1
1
Reserved; do not use.
PA4
0
0
GPIO.
MISO
0
1
SPI Master In Slave Out.
RXD
1
0
UART Receive data.
1
1
Reserved; do not use.
PA3
0
0
GPIO.
SCK
0
1
SPI Serial Clock.
TXDE
1
0
UART Driver Enable.
SCL
1
1
I2C serial clock.
PA2
0
0
GPIO.
0
1
Reserved; do not use.
1
0
Comparator Positive Input.
1
1
Reserved; do not use.
PA6
PA5
PA4
PA3
PA2
CINP
PS024604-1005
AF0
AF1 Alternate Function Description
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Table 13. Port Alternate Function Mapping (Continued)
Port
Pin
Mnemonic
Port A
PA1
PA1
0
GPIO.
0
1
Reserved; do not use.
1
0
Op amp positive input and comparator negative
input.
1
1
Reserved; do not use.
0
0
GPIO.
0
1
Reserved; do not use.
1
0
Op amp negative input.
1
1
Reserved; do not use.
0
0
GPIO.
0
1
Reserved; do not use.
1
0
ADC analog input 7.
1
1
Reserved; do not use.
0
0
GPIO.
0
1
Reserved; do not use.
1
0
ADC analog input 6.
1
1
Reserved; do not use.
0
0
GPIO.
0
1
Reserved; do not use.
1
0
ADC analog input 5.
1
1
Reserved; do not use.
0
0
GPIO.
0
1
Reserved; do not use.
1
0
ADC analog input 4 (also CINN if CPSEL=1).
1
1
Reserved; do not use.
PB3
0
0
GPIO.
PB3INT
0
1
GPIO with edge interrupt.
ANA3 and OPOUT
1
0
ADC analog input 3 and op amp output.
1
1
Reserved; do not use.
PA0
OPINN
Port B
PB7
PB7
ANA7
PB6
PB6
ANA6
PB5
PB5
ANA5
PB4
PB4
ANA4
PB3
AF1 Alternate Function Description
0
OPINP and CINN
PA0
AF0
General-Purpose I/O
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Table 13. Port Alternate Function Mapping (Continued)
Port
Pin
Mnemonic
Port B
PB2
PB2
0
0
GPIO/Timer 0 input 2.
PB2INT
0
1
GPIO/Timer 0 input 2—edge interrupt enabled.
ANA2
1
0
ADC analog input 2.
T0IN2
1
1
Timer 0 input 2; dedicated input.
PB1
0
0
GPIO/Timer 0 input 1.
PB1INT
0
1
GPIO/Timer 0 input 1—edge interrupt enabled.
ANA1
1
0
ADC analog input 1.
1
1
Reserved; do not use.
PB0
0
0
GPIO/Timer 0 input 0.
PB0INT
0
1
GPIO/Timer 0 input 0—edge interrupt enabled.
ANA0
1
0
ADC analog input 0.
1
1
Reserved; do not use.
0
0
GPIO.
0
1
Reserved; do not use.
1
0
Timer 0 output.
1
1
Reserved; do not use.
PB1
PB0
Port C
PC0
PC0
T0OUT
AF0
AF1 Alternate Function Description
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. The Port A[7:0] pins can be
configured to generate an interrupt request on either the rising edge or falling edge of the
pin input signal. The Port B[3:0] pins can be configured to generate an interrupt request on
both the rising and falling edges of the pin input signal. For Port A, the GPIO interrupt
edge selection is controlled by the Interrupt Edge Select subregister. Enabling and disabling of the Port Interrupts is handled in the Interrupt Controller. Port B[3:0], with dual
edge interrupt capability, is selected by AF1, AF0. Refer to the Interrupt Controller chapter on page 51 for more information.
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 14 lists these Port registers. Use the Port A–C Address and Control registers
together to provide access to subregisters for Port configuration and control.
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Table 14. GPIO Port Registers and Subregisters
Port Register Mnemonic
Port Register Name
PxADDR
Port A–C Address Register—selects subregisters.
PxCTL
Port A–C Control Register—provides access to
subregisters.
PxIN
Port A–C Input Data Register.
PxOUT
Port A–C Output Data Register.
Port Subregister Mnemonic
Port Register Name
PxDD
Data Direction
PxAF0
Alternate Function 0
PxAF1
Alternate Function 1—Ports A and B only.
PxOC
Output Control (open-drain).
PxHDE
High Drive Enable.
PxSMRE
Stop-Mode Recovery Source Enable.
PxPUE
Pull-Up Enable.
PxIRQES
Interrupt Edge Select—Ports A and C only.
IRQPSEL
Interrupt Port Select—Port A only.
Port A-C Address Registers
The Port A–C Address registers select the GPIO port functionality accessible through the
Port A–C Control registers. The Port A–C Address and Control registers combine to provide access to all GPIO port control. See Table 15.
Table 15. Port A–C GPIO Address Registers (PxADDR)
BITS
7
6
5
4
3
FIELD
PADDR[7:0]
RESET
00H
R/W
R/W
ADDR
FD0H, FD4H, FD8H
2
1
0
Table 16 lists the Port Control subregisters that are accessible via the Port A–C Control
registers.
General-Purpose I/O
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Table 16. Port Control Subregisters by Port Address
Port
Address
Port Control Subregisters
00h
No function; provides some protection against accidental port
reconfiguration.
01h
Data direction.
02h
Alternate Function 0
03h
Output Control (open-drain).
04h
High Drive Enable.
05h
Stop-mode recovery source enable.
06h
Pull-up enable.
07h
Alternate Function 1—ports A and B only.
08h
Interrupt Edge Select - Port A and Port C only
09h
Port Interrupt Select Register - Port A only
0Ah–FFh
No Function
Port A–C Control Registers
The Port A–C Control registers set the GPIO port operation. The value in the corresponding Port A–C Address register determines the control subregisters accessible using the
Port A–C Control registers, shown in Table 17. The Port Control registers provide access
to all subregisters that configure GPIO port operation.
Table 17. Port A–C Control Registers (PxCTL)
BITS
7
6
5
4
3
FIELD
PCTL
RESET
00H
R/W
R/W
ADDR
FD1H, FD5H, FD9H
2
1
0
Port A–C Data Direction Subregisters
The Port A–C Data Direction subregisters are accessed through the Port A–C Control registers by writing 01h to the Port A–C Address registers. See Table 18.
PS024604-1005
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In each of these three data direction subregisters, bits [7:0] control the direction of the
associated port pin. Port Alternate Function operation overrides the Data Direction Register setting.
If the value of the bit is 0, the direction is output, and data in the Port A–C Output Data
registers is driven onto the port pin.
If the value of the bit is 1, the direction is input. The port pin is sampled, the value is written into the Port A–C Input Data registers, and the output driver is tristated.
Table 18. Port A–C Data Direction Sub-Registers
BITS
7
6
5
4
3
2
1
0
FIELD
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
RESET
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
Bit
Position
[7:0]
Data
Direction
If 01H in Port A–C Address Register, accessible through the Port A-C Control Register
Value
(H)
Description
These bits control the direction of the associated port pin. Port Alternate Function
operation overrides the Data Direction register setting.
Output. Data in the Port A–C Output Data register is driven onto the port pin.
0
1
Input. The port pin is sampled and the value written into the Port A–C Input Data
Register. The output driver is tristated
Port A–B Alternate Function 0 Subregisters
The Port A–B Alternate Function subregisters, shown in Table 19, are accessed through
the Port A–B Control registers by writing 02h to the Port A–B Address registers. The Port
A–B Alternate Function subregisters select the alternate functions for the selected pins.
Refer to the GPIO Alternate Functions section on page 36 to determine the alternate function associated with each port pin.
Caution: Do not enable alternate function for GPIO port pins which do not have an associated alternate function. Failure to follow this guideline may result in unpredictable operation.
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Table 19. Port A–B Alternate Function 0 Sub-Registers
BITS
7
6
5
4
3
2
1
0
FIELD
AF0_7
AF0_6
AF0_5
AF0_4
AF0_3
AF0_2
AF0_1
AF0_0
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 02H in Port A-C Address Register, accessible through the Port A-C Control Register
ADDR
Bit
Position
Value
(H)
Description
[7:0]
AF0
0
Port Alternate Function 0 select.
The alternate function 0 function is not selected.
1
The alternate function 0 function is selected.
Port A–C Output Control Subregisters
The Port A–C Output Control subregisters, shown in Table 20, are accessed through the
Port A–C Control registers by writing 03h to the Port A–C Address registers. Setting the
bits in the Port A–C Output Control subregisters to 1 configures the specified port pins for
open-drain operation. These subregisters affect the pins directly and, as a result, alternate
functions are also affected.
Table 20. Port A–C Output Control Sub-Registers
BITS
7
6
5
4
3
2
1
0
FIELD
POC7
POC6
POC5
POC4
POC3
POC2
POC1
POC0
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 03H in Port A–C Address Register, accessible through the Port A–C Control Register
ADDR
Bit
Position
Value
(H)
[7:0]
POC
0
1
PS024604-1005
Description
Port Output Control
These bits function independently of the alternate function bit and disable the
drains if set to 1.
The drains are enabled for any output mode.
The drain of the associated pin is disabled (open-drain mode).
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Port A–C High Drive Enable Subregisters
The Port A–C High Drive Enable subregisters, shown in Table 21, are accessed through
the Port A-C Control registers by writing 04h to the Port A–C Address registers. Setting
the bits in the Port A–C High Drive Enable subregisters to 1 configures the specified port
pins for high current output drive operation. The Port A–C High Drive Enable subregisters
affect the pins directly and, as a result, alternate functions are also affected.
Table 21. Port A–C High Drive Enable Sub-Registers
BITS
7
6
5
4
3
2
1
0
FIELD
PHDE7
PHDE6
PHDE5
PHDE4
PHDE3
PHDE2
PHDE1
PHDE0
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 04H in Port A-C Address Register, accessible through the Port A-C Control Register
ADDR
Bit
Position
Value
(H)
Description
[7:0]
PHDE
0
Port High Drive Enable
The Port pin is configured for standard output current drive.
1
The Port pin is configured for high output current drive.
Port A–C Stop-Mode Recovery Source Enable Subregisters
The Port A–C Stop-Mode Recovery Source Enable subregisters, shown in Table 22, are
accessed through the Port A–C Control registers by writing 05h to the Port A-C Address
registers. Setting the bits in the Port A–C Stop-Mode Recovery Source Enable subregisters
to 1 configures the specified port pins as a Stop-Mode Recovery source. During STOP
mode, any logic transition on a port pin enabled as a Stop-Mode Recovery source initiates
Stop-Mode Recovery.
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Table 22. Port A–C STOP Mode Recovery Source Enable Sub-Registers
BITS
7
6
5
4
3
2
1
0
FIELD
PSMRE7
PSMRE6
PSMRE5
PSMRE4
PSMRE3
PSMRE2
PSMRE1
PSMRE0
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 05H in Port A–C Address Register, accessible through the Port A–C Control Register
ADDR
Bit
Position
Value
(H)
[7:0]
PSMRE
0
1
Description
Port STOP Mode Recovery Source Enable
The Port pin is not configured as a STOP Mode Recovery source. Transitions on
this pin during STOP mode do not initiate STOP Mode Recovery.
The Port pin is configured as a STOP Mode Recovery source. Any logic
transition on this pin during STOP mode initiates STOP Mode Recovery.
Port A–C Pull-Up Enable Subregisters
The Port A–C Pull-Up Enable subregisters, shown in Table 23, are accessed through the
Port A–C Control registers by writing 06h to the Port A–C Address registers. Setting the
bits in the Port A–C Pull-Up Enable subregisters enables a weak internal resistive pull-up
on the specified port pins.
PS024604-1005
PRELIMINARY
Port A–C Control Registers
Z8 Encore!® Motor Control Flash MCUs
Product Specification
46
Table 23. Port A–C Pull-Up Enable Sub-Registers
BITS
7
6
5
4
3
2
1
0
FIELD
PPUE7
PPUE6
PPUE5
PPUE4
PPUE3
PPUE2
PPUE1
PPUE0
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
If 06H in Port A–C Address Register, accessible through the Port A–C Control Register
Bit
Position
Value
(H)
Description
[7:0]
PPUE
0
Port Pull-Up Enable
The weak pull-up on the Port pin is disabled.
1
The weak pull-up on the Port pin is enabled.
Port A Interrupt Edge Select Subregister
The Interrupt Edge Select (IRQES) Subregister, shown in Table 24, determines whether an
interrupt is generated for the rising edge or falling edge on the selected GPIO Port A input
pin.
Table 24. Interrupt Edge Select Sub-Register (IRQES)
BITS
7
6
5
4
Reserved
FIELD
3
2
1
0
IES3
IES2
IES1
IES0
RESET
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R/W
R/W
R/W
R/W
ADDR
If 08H in Port A Address Register, accessible through the Port A and Port C Control Register
Bit
Position
Value
(H)
[3:0]
IESx
0
1
General-Purpose I/O
Description
Interrupt Edge Select x
An interrupt request is generated on the falling edge of the PAx input.
An interrupt request is generated on the rising edge of the PAx input,
where x indicates the specific GPIO Port pin number (0 through 7).
PRELIMINARY
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Interrupt Port Select Register
The Interrupt Port Select Register, shown in Table 25, is used to select which Port A pins
are used as interrupts.
Table 25. Interrupt Port Select Sub-Register (IRQPS)
BITS
7
6
5
4
Reserved
FIELD
3
2
1
0
PA73SEL
PA62SEL
PA51SEL
PA40SEL
RESET
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R/W
R/W
R/W
R/W
ADDR
If 09H in Port A Address Register, accessible through the Port A and Port C Control Register
Bit
Position
Value
(H)
Description
[3:0]
PAxxSEL
0
Interrupt Port Select x
An interrupt request is generated on PAx, where x indicates (0 through 3)
1
An interrupt request is generated on PAx, where x indicates (4 through 7)
Port B Alternate Function 1 Subregisters
The Port B Alternate Function Subregisters, shown in Table 26, is accessed through the
Port B Control Register by writing 08H to the Port B Address Register. The Port B Alternate Function subregister selects the alternate functions for the selected pins. Refer to the
GPIO Alternate Functions section on page 36 to determine the alternate function associated with each port pin.
Caution: Do not enable alternate function for GPIO port pins which do not have an associated alternate function. Failure to follow this guideline may result in unpredictable operation.
PS024604-1005
PRELIMINARY
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Product Specification
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Table 26. Port A–B Alternate Function 1 Sub-Registers
BITS
7
6
5
4
3
2
1
0
FIELD
AF1_7
AF1_6
AF1_5
AF1_4
AF1_3
AF1_2
AF1_1
AF1_0
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 07H in Port A-C Address Register, accessible through the Port A-C Control Register
ADDR
Bit
Position
Value
(H)
Description
[7:0]
AF1
0
Port Alternate Function 1 select.
The alternate function 1 function is not selected.
1
The alternate function 1 function is selected.
Port A-C Input Data Registers
Reading from the Port A–C Input Data registers, shown in Table 27, return the sampled
values from the corresponding port pins. The Port A–C Input Data registers are read-only.
Sampled data are from the corresponding port pin input.
Table 27. Port A-C Input Data Registers (PxIN)
BITS
7
6
5
4
3
2
1
0
FIELD
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
RESET
X
X
X
X
X
X
X
X
R/W
R
R
R
R
R
R
R
R
FD2H, FD6H, FDAH
ADDR
Bit
Position
Value
(H)
[7:0]
PIN
0
Port Input Data x
Input data is a logical 0 (Low).
1
Input data is a logical 1 (High).
General-Purpose I/O
Description
PRELIMINARY
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Z8FMC16100 Series Flash MCU
Product Specification
49
Port A–C Output Data Registers
The Port A–C Output Data registers, shown in Table 28, write output data to the pins.
These bits contain the data to be driven out from the port pins. The values are only driven
if the corresponding pin is configured as an output and the pin is not configured for alternate function operation.
Table 28. Port A-C Output Data Register (PxOUT)
BITS
7
6
5
4
3
2
1
0
FIELD
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD3H, FD7H, FDBH
ADDR
Bit
Position
Value
(H)
[7:0]
POUT
0
1
PS024604-1005
Description
Port Output Data x
Drive is a logical 0 (Low).
Drive is a logical 1 (High). High value is not driven if the drain has been disabled
by setting the corresponding Port Output Control register bit to 1.
PRELIMINARY
Port A–C Output Data Registers
Z8 Encore!® Motor Control Flash MCUs
Product Specification
50
General-Purpose I/O
PRELIMINARY
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Interrupt Controller
The interrupt controller on the Z8FMC16100 Series Flash MCU prioritizes the system
exceptions and interrupt requests from the on-chip peripherals and the GPIO port pins.
The features of the interrupt controller include the following:
•
•
•
•
•
Multiple GPIO interrupts
Interrupts for on-chip peripherals
Nonmaskable system exceptions
Three levels of individually programmable interrupt priority
20 sources of interrupts for the interrupt controller, 9 of the sources can be configured
from GPIO pins
System exceptions (SEs) and interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start a service routine.
Interrupt service routines are involved with the exchange of data, status information, or
control information between the CPU and the interrupting peripheral. When the service
routine is completed, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt controller has no effect on operation. Refer to the eZ8 CPU User Manual
(UM0128) for more information regarding interrupt servicing by the eZ8 CPU. The eZ8
CPU User Manual is available for download at www.zilog.com.
Interrupt and System Exception Vector Listing
Table 29 lists the system exceptions and the interrupts in order of priority. Reset and system exceptions always have priority over interrupts. The system exception and interrupt
vectors are stored with the most significant byte (MSB) at the even Program Memory
address and the least significant byte (LSB) at the following odd Program Memory
address.
Note:
PS024604-1005
Port interrupts are only available in those packages which support the associated port pins.
PRELIMINARY
Interrupt and System Exception Vector Listing
Z8 Encore!® Motor Control Flash MCUs
Product Specification
52
Table 29. Reset, System Exception, and Interrupt Vectors in Order of Priority
Priority
Program Memory
Vector Base
Address
Programmable
Priority?
Interrupt or Trap Source
Reset and System Exceptions
0002h
No
Reset
0004h
No
Watch-Dog Timer (see the Watch-Dog Timer chapter on
page 63)
003AH
No
Primary Oscillator Fail Trap
003CH
No
Watch-Dog Timer Oscillator Fail Trap
0006h
No
Illegal Instruction Trap
Highest 0008h
Yes
PWM Timer
000Ah
Yes
PWM Fault
000Ch
Yes
ADC
000Eh
Yes
Comparator output rising and falling edge
0010h
Yes
Timer 0
0012H
Yes
UART 0 receiver
0014H
Yes
UART 0 transmitter
0016H
Yes
SPI
0018H
Yes
I2C
001AH
Yes
Reserved
001CH
Yes
Port C0 with selectable rising or falling input edge
001EH
Yes
Port B[3:0] rising and fall input edge
0020h
Yes
Port A7/A3 with selectable rising or falling input edge
0022H
Yes
Port A6/A2 with selectable rising or falling input edge
0024H
Yes
Port A5/A1 with selectable rising or falling input edge
0026H
Yes
Port A4/A0 with selectable rising or falling input edge
0028H–0039H
N/A
Reserved
Interrupts (maskable)
Lowest
Interrupt Controller
PRELIMINARY
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Z8FMC16100 Series Flash MCU
Product Specification
53
Architecture
Figure 6 illustrates a block diagram of the interrupt controller.
Internal Interrupts
System Exceptions
High
Priority
Interrupt Request Latches and Control
Port Interrupts
Vector
Medium
Priority
Priority
Mix
Service Request
Low
Priority
Figure 6. Interrupt Controller Block Diagram
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
•
•
Execution of an Enable Interrupt (EI) instruction
Execution of a Return from Interrupt (IRET) instruction
Writing a 1 to the IRQE bit in the Interrupt Control Register
Interrupts are globally disabled by any of the following actions:
•
•
•
•
PS024604-1005
Execution of a Disable Interrupt (DI) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
Writing a 0 to the IRQE bit in the Interrupt Control Register
Reset
PRELIMINARY
Architecture
Z8 Encore!® Motor Control Flash MCUs
Product Specification
54
•
•
Execution of a Trap instruction
Illegal Instruction trap
System Exceptions
The Z8FMC16100 Series Flash MCU supports multiple system exceptions. System
exceptions are generated for the following events:
•
•
•
•
Illegal Instruction trap
Watch-Dog Timer interrupt
Watch-Dog Timer RC oscillator failure
Primary oscillator failure
System exceptions, excluding the Watch-Dog Timer interrupt, are nonmaskable and therefore cannot be disabled by the interrupt controller (setting IRQE to 0 has no effect).
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 interrupts are
always higher priority than Level 2 interrupts. Level 2 interrupts are always higher priority
than Level 1 interrupts. Within each interrupt priority level (Level 1, Level 2, or Level 3),
priority is assigned as specified in Table 29.
Interrupt Assertion
When an interrupt request occurs, the corresponding bit in the Interrupt Request Register
is set. This bit is automatically cleared when the eZ8 CPU vectors to the Interrupt Service
Routine (ISR). Writing a 0 to the corresponding bit in the Interrupt Request Register also
clears the interrupt request.
Caution: If an interrupt is disabled, software can poll the appropriate interrupt request register bit
and clear the bit directly. The following style of coding to clear bits in the Interrupt Request registers is not recommended. All incoming interrupts that are received between
execution of the first LDX command and the last LDX command are lost.
The following code segment is an example of a poor coding style that can result in lost
interrupt requests:
LDX r0, IRQ0
AND r0, MASK
Q0, r0
Interrupt Controller
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
55
To avoid missing interrupts, ZiLOG recommends the following style of coding to clear
bits in the Interrupt Request 0 Register:
ANDX IRQ0, MASK
Software Interrupt Assertion
Program code can generate interrupts directly. Writing a 1 to the appropriate bit in the
Interrupt Request Register triggers an interrupt (assuming that interrupt is enabled). This
bit is automatically cleared when the eZ8 CPU vectors to the Interrupt Service Routine
(ISR).
Caution: The following style of coding to generate software interrupts by setting bits in the Interrupt Request registers is not recommended. All incoming interrupts that are received between execution of the first LDX command and the last LDX command are lost.
The following code segment is an example of a poor coding style that can result in lost
interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, ZiLOG recommends the following style of coding to set
bits in the Interrupt Request registers:
ORX IRQ0, MASK
Interrupt Control Register Definitions
The interrupt control registers enable individual interrupts, set interrupt priorities, and
indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) Register, shown in Table 30, stores the interrupt requests
for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are globally
enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8
CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the
Interrupt Request 0 register to determine if any interrupt requests are pending.
PS024604-1005
PRELIMINARY
Software Interrupt Assertion
Z8 Encore!® Motor Control Flash MCUs
Product Specification
56
Table 30. Interrupt Request 0 Register (IRQ0)
BITS
7
6
5
4
3
2
1
0
FIELD
PWMI
FLTI
ADCI
CMPI
T0I
U0RXI
U0TXI
SPII
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC0H
ADDR
Bit
Position
Value
(H)
[7]
PWMI
0
PWM Timer Interrupt Request
No interrupt request is pending for the Pulse-Width Modulator.
1
An interrupt request from the Pulse-Width Modulator is awaiting service.
[6]
FLTI
[5]
ADCI
[4]
CMPI
[3]
T0I
[2]
U0RXI
[1]
U0TXI
[0]
SPII
0
Description
Fault Interrupt Request. The fault interrupt is generated in the PWM module and
originates from the Fault0 pin, Fault1 pin or the Comparator output. An interrupt
enable for each of these sources exists in the PWM module.
No Fault interrupt request is pending.
1
A Fault interrupt request is awaiting service.
0
ADC Interrupt Request
No interrupt request is pending for the Analog to Digital Converter.
1
An interrupt request from the Analog to Digital Converter is awaiting service.
0
Comparator Interrupt Request
No interrupt request is pending for the Comparators.
1
An interrupt request from the Comparators is awaiting service.
0
Timer 0 Interrupt Request
No interrupt request is pending for Timer 0.
1
An interrupt request from Timer 0 is awaiting service.
0
UART 0 Receiver Interrupt Request
No interrupt request is pending for the UART 0 receiver.
1
An interrupt request from the UART 0 receiver is awaiting service.
0
UART 0 Transmitter Interrupt Request
No interrupt request is pending for the UART 0 transmitter.
1
An interrupt request from the UART 0 transmitter is awaiting service.
0
SPI Interrupt Request
No interrupt request is pending for the SPI.
1
An interrupt request from the SPI is awaiting service.
Interrupt Controller
PRELIMINARY
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Z8FMC16100 Series Flash MCU
Product Specification
57
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) Register, shown in Table 31, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt
Request 1 Register to determine if any interrupt requests are pending.
Table 31. Interrupt Request 1 Register (IRQ1)
BITS
7
6
5
4
3
2
1
0
FIELD
I2CI
Reserved
PC0I
PBI
PA73I
PA62I
PA51I
PA40I
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
FC3H
ADDR
Bit
Position
Value
(H)
[7]
I2CI
0
I2C Interrupt Request
No interrupt request is pending for I2C.
1
An interrupt request from I2C is awaiting service.
0
PC0 Interrupt Request — Logic in the Port C GPIO module selects either the
rising or falling edge.
No interrupt request is pending for PC0.
1
An interrupt request from PC0 is awaiting service.
0
PB3 – PB0 Interrupt Request
No interrupt request is pending for any PB3 – PB0.
1
An interrupt request from PB3 – PB0 is awaiting service.
0
PA7 or PA3 Interrupt Request — Logic in the Port A GPIO module selects either
PA7 or PA3 and either rising or falling edge.
No interrupt request is pending for PA7 or PA3
1
An interrupt request from PA7 or PA3 is awaiting service.
0
PA6 or PA2 Interrupt Request — Logic in the Port A GPIO module selects either
PA6 or PA2 and either rising or falling edge.
No interrupt request is pending for PA6 or PA2
1
An interrupt request from PA6 or PA2 is awaiting service.
[5]
PC0I
[4]
PBI
[3]
PA73I
[2]
PA62I
PS024604-1005
Description
PRELIMINARY
Interrupt Request 1 Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
58
Bit
Position
Value
(H)
Description
[1]
PA51I
0
PA5 or PA1 Interrupt Request — Logic in the Port A GPIO module selects either
PA5 or PA1 and either rising or falling edge.
No interrupt request is pending for PA5 or PA1
1
An interrupt request from PA5 or PA1 is awaiting service.
0
PA4 or PA0 Interrupt Request — Logic in the Port A GPIO module selects either
PA4 or PA0 and either rising or falling edge.
No interrupt request is pending for PA4 or PA0
1
An interrupt request from PA4 or PA0 is awaiting service.
[0]
PA40I
IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit registers, shown in Tables 33 and 34, form a priority
encoded enabling for interrupts in the Interrupt Request 0 Register. Priority is generated
by setting bits in each register. Table 32 describes the priority control for IRQ0.
Table 32. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
Note: x indicates the register bits from 0 through 7.
Table 33. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
7
6
5
4
3
2
1
0
FIELD
PWMENH
FLTENH
ADCENH
CMPENH
T0ENH
U0RENH
U0TENH
SPIENH
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC1H
ADDR
PWMENH—Pulse-Width Modulator Interrupt Request Enable High Bit
FLTENH—Fault Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
CMPENH—Comparator Interrupt Request Enable High Bit
Interrupt Controller
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
59
T0ENH—Timer 1 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
SPIENH—SPI Interrupt Request Enable High Bit
Table 34. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
7
6
5
4
3
2
1
0
FIELD
PWMENL
FLTENL
ADCENL
CMPENL
T0ENL
U0RENL
U0TENL
SPIENL
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC2H
ADDR
PWMENL—Pulse-Width Modulator Interrupt Request Enable Low Bit
FLTENL—Fault Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
CMPENL—Comparator Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
SPIENL—SPI Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
The IRQ1 Enable High and Low Bit registers, shown in Tables 36 and 37, form a priority
encoded enabling for interrupts in the Interrupt Request 1 register. Priority is generated by
setting bits in each register. Table 35 describes the priority control for IRQ1.
Table 35. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x] Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
x indicates the register bits from 0 through 7.
PS024604-1005
PRELIMINARY
IRQ1 Enable High and Low Bit Registers
Z8 Encore!® Motor Control Flash MCUs
Product Specification
60
Table 36. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS
7
6
5
4
3
2
1
0
FIELD
I2CENH
Reserved
PC0ENH
PBENH
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
2
1
0
PA73ENH PA62ENH PA51ENH PA40ENH
FC4H
ADDR
Bit
Name
Position
Description
[7]
I2CENH
I2C Interrupt Request Enable High Bit
[5]
PC0ENH Port C0Interrupt Request Enable High Bit
[4]
PBENH
[3]
PA73ENH Port A73 Interrupt Request Enable High Bit
[2]
PA62ENH Port A62 Interrupt Request Enable High Bit
[1]
PA51ENH Port A51 Interrupt Request Enable High Bit
[0]
PA40ENH Port A40 Interrupt Request Enable High Bit
Port B[3:0] Interrupt Request Enable High Bit
Table 37. IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS
7
6
5
4
3
FIELD
I2CENL
Reserved
PC0ENL
PBENL
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
PA73ENL PA62ENL PA51ENL PA40ENL
FC5H
ADDR
Bit
Name
Position
Description
[7]
I2CENL
I2C Interrupt Request Enable Low Bit
[5]
PC0ENL
Port C0Interrupt Request Enable Low Bit
[4]
PBENL
Port B[3:0] Interrupt Request Enable Low Bit
Interrupt Controller
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
61
Bit
Name
Position
Description
[3]
PA73ENL Port A73 Interrupt Request Enable Low Bit
[2]
PA62ENL Port A62 Interrupt Request Enable Low Bit
[1]
PA51ENL Port A51 Interrupt Request Enable Low Bit
[0]
PA40ENL Port A40 Interrupt Request Enable Low Bit
Interrupt Control Register
The Interrupt Control (IRQCTL) Register, shown in Table 38, contains the Master Enable
Bit (IRQE) for all interrupts.
Table 38. Interrupt Control Register (IRQCTL)
BITS
7
6
5
4
FIELD
IRQE
RESET
0
0
0
0
R/W
R/W
R
R
R
3
2
1
0
0
0
0
0
R
R
R
R
Reserved
FCFH
ADDR
IRQE—Interrupt Request Enable
This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request or system exception,
Reset, or direct register write to 0.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved—Must be 0.
PS024604-1005
PRELIMINARY
Interrupt Control Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
62
Interrupt Controller
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
63
Watch-Dog Timer
The Watch-Dog Timer (WDT) helps protect against corrupted or unreliable software and
other system-level problems which may place the Z8FMC16100 Series Flash MCU into
unsuitable operating states. The Watch-Dog Timer includes the following features:
•
•
•
On-chip RC oscillator
A selectable time-out response: Reset or System Exception
16-bit programmable time-out value
Operation
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets or interrupts the
Z8FMC16100 Series Flash MCU when the WDT reaches its terminal count. The WatchDog Timer uses its own dedicated on-chip RC oscillator as its clock source. The WatchDog Timer has only two modes of operation—on and off. Once enabled, it always counts
and must be refreshed to prevent a time-out. An enable can be performed by executing the
WDT instruction or by setting the WDT_AO Option Bit. The WDT_AO bit enables the WatchDog Timer to operate all the time, even if a WDT instruction has not been executed.
To minimize power consumption, the RC oscillator can be disabled. The RC oscillator is
disabled by clearing the WDTEN bit in the Oscillator Control Register. If the RC oscillator
is disabled, the WDT will not operate.
The Watch-Dog Timer is a 16-bit reloadable downcounter that uses two 8-bit registers in
the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
calculated by the following equation:
WDT Time-Out Period (ms) =
WDT Reload Value
10
where the WDT reload value is assigned by {WDTH[7:0], WDTL[7:0]} and the typical
Watch-Dog Timer RC oscillator frequency is 10 KHz. The user should consider system
requirements when selecting the time out delay. Table 39 provides information on approximate time-out delays for the default and maximum WDT reload values.
PS024604-1005
PRELIMINARY
Operation
Z8 Encore!® Motor Control Flash MCUs
Product Specification
64
Table 39. Watch-Dog Timer Approximate Time-Out Delays
Approximate Time-Out Delay
(with 10 KHz Typical WDT Oscillator Frequency)
WDT Reload
Value (Hex)
WDT Reload
Value
(Decimal)
Typical
Description
0400
1024
102 ms
Reset default value time-out delay.
FFFF
65,536
6.55 s
Maximum time-out delay.
Watch-Dog Timer Refresh
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog
Timer Reload registers. The Watch-Dog Timer then counts down to 0000h unless a WDT
instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog Timer Reload
registers. Counting resumes following the reload operation.
When the Z8FMC16100 Series Flash MCU is operating in DEBUG Mode (through the
On-Chip Debugger), the Watch-Dog Timer is continuously refreshed to prevent spurious
Watch-Dog Timer time-outs.
Watch-Dog Timer Time-Out Response
The Watch-Dog Timer times out when the counter reaches 0000h. A time-out of the
Watch-Dog Timer generates either a system exception or a Reset. The WDT_RES Option
Bit determines the time-out response of the Watch-Dog Timer. Refer to the Option Bits
chapter for information regarding programming of the WDT_RES Option Bit.
WDT System Exception in Normal Operation
If configured to generate a system exception when a time-out occurs, the Watch-Dog
Timer issues an exception request to the interrupt controller. The eZ8 CPU responds to the
request by fetching the System Exception vector and executing code from the vector
address. After time-out and system exception generation, the Watch-Dog Timer is
reloaded automatically and continues counting.
WDT System Exception in Stop Mode
If configured to generate a system exception when a time-out occurs and the
Z8FMC16100 Series Flash MCU is in STOP mode, the Watch-Dog Timer automatically
initiates a Stop-Mode Recovery and generates a system exception request. Both the WDT
status bit and the STOP bit in the Reset Status and Control Register section on page 29 are
set to 1 following WDT time-out in STOP mode. Refer to the Reset and Stop-Mode
Recovery chapter on page 23 for more information.
Watch-Dog Timer
PRELIMINARY
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Z8FMC16100 Series Flash MCU
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Following completion of the Stop-Mode Recovery the eZ8 CPU responds to the system
exception request by fetching the System Exception vector and executing code from the
vector address.
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the
device into the Reset state. The WDT status bit in the Reset Status and Control Register is
set to 1. Refer to the Reset and Stop-Mode Recovery chapter on page 23 for more information on Reset and the WDT status bit. Following a Reset sequence, the WDT Counter is initialized with its reset value.
WDT Reset in Stop Mode
If enabled in STOP mode and configured to generate a Reset when a time-out occurs and
the device is in STOP mode, the Watch-Dog Timer initiates a Stop-Mode Recovery. Both
the WDT status bit and the STOP bit in the Reset Status and Control Register are set to 1
following WDT time-out in STOP mode. Refer to the Reset and Stop-Mode Recovery
chapter on page 23 for more information.
Watch-Dog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watch-Dog Timer Reload High (WDTH) Register
address unlocks the two Watch-Dog Timer Reload registers (WDTH and WDTL) to allow
changes to the time-out period. These write operations to the WDTH register address produce no effect on the bits in the WDTH register. The locking mechanism prevents spurious
writes to the Reload registers. The following sequence is required to unlock the WatchDog Timer Reload registers (WDTH and WDTL) for write access.
1. Write 55H to the Watch-Dog Timer Reload High register (WDTH).
2. Write AAH to the Watch-Dog Timer Reload High register (WDTH).
3. Write the appropriate value to the Watch-Dog Timer Reload High register (WDTH).
4. Write the appropriate value to the Watch-Dog Timer Reload Low register (WDTL).
All steps of the Watch-Dog Timer Reload Unlock sequence must be written in the order
just listed. The value in the Watch-Dog Timer Reload registers is loaded into the counter
every time a WDT instruction is executed.
Watch-Dog Timer Reload High and Low Byte Registers
The Watch-Dog Timer Reload High and Low Byte (WDTH, WDTL) registers, shown in
Table 40 through Table 41, form the 16-bit reload value that is loaded into the Watch-Dog
Timer when a WDT instruction executes. The 16-bit reload value is {WDTH[7:0],
WDTL[7:0]}. Writing to these registers following the unlock sequence sets the appropri-
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PRELIMINARY
Watch-Dog Timer Reload Unlock Sequence
Z8 Encore!® Motor Control Flash MCUs
Product Specification
66
ate Reload Value. Reading from these registers returns the current Watch-Dog Timer count
value.
Table 40. Watch-Dog Timer Reload High Byte Register (WDTH)
BITS
7
6
5
4
3
FIELD
WDTH
RESET
04H
R/W
R/W*
ADDR
FF2H
2
1
0
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTH—WDT Reload High Byte
Most significant byte (MSB), Bits[15:8], of the 16-bit WDT reload value.
Table 41. Watch-Dog Timer Reload Low Byte Register (WDTL)
BITS
7
6
5
4
3
FIELD
WDTL
RESET
00H
R/W
R/W*
ADDR
FF3H
2
1
0
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTL—WDT Reload Low
Least significant byte (LSB), Bits[7:0], of the 16-bit WDT reload value.
Watch-Dog Timer
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Z8FMC16100 Series Flash MCU
Product Specification
67
Pulse-Width Modulator
The Z8FMC16100 Series Flash MCU includes a Pulse-Width Modulator (PWM) optimized for Motor Control applications. The PWM features include:
•
•
•
•
•
•
6 independent PWM outputs or 3 complementary PWM output pairs
•
•
•
•
•
•
FAULT inputs generate pulse-by-pulse or hard shutdown
Programmable deadband insertion for complementary output pairs
Edge-aligned or center-aligned PWM signal generation
PWM OFF state is option-bit-programmable
PWM outputs driven to OFF state on System Reset
Asynchronous disabling of PWM outputs on system fault; outputs are forced to OFF
state
12-bit reload counter with 1-, 2-, 4-, or 8-bit programmable clock prescaler
High current source and sink on all PWM outputs
PWM pairs can be used as general-purpose inputs when outputs are disabled
Analog-to-digital converter synchronized with PWM period
Narrow pulse suppression with programmable threshold
Architecture
The PWM unit consists of a master timer to generate the modulator time base and six independent compare registers to set the pulse-width modulation for each output. The six outputs are designed to provide control signals for inverter drive circuits. As such, the outputs
are grouped into pairs consisting of a High driver and a Low driver output. The output
pairs are programmable to operate independently or as complementary signals. In complementary output mode, a programmable dead time is inserted to ensure nonoverlapping signal transitions. The master count and compare values feed into modulator logic that
generates the proper transitions in the output states. Output polarity and fault/OFF state
control logic allows programming of the default OFF states, which forces the outputs to a
safe state in the event a fault in the motor drive is detected.
Figure 7 illustrates the architecture of the PWM modulator.
PS024604-1005
PRELIMINARY
Architecture
Z8 Encore!® Motor Control Flash MCUs
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12-Bit Counter
with Prescaler
Control
Logic
ISense S/H
IRQ
ADC Trigger
Fault Inputs
PWM Deadband
PWM0HD
Data Bus
System Clock
PWM
State
Logic
Fault
Polarity
Logic
PWM0H
PWM
State
Logic
Fault
Polarity
Logic
PWM1H
PWM
State
Logic
Fault
Polarity
Logic
PWM2H
PWM0L
PWM0LD
PWM1HD
PWM1L
PWM1LD
PWM2HD
PWM2L
PWM2LD
Figure 7. PWM Block Diagram
PWM Option Bits
To protect the configuration of critical PWM parameters, the settings to enable the output
channels, and the default OFF state, are maintained as user option bits. These values are
set when the user program code is written to the part, and cannot be changed by software.
See the Option Bits chapter on page 223.
Pulse-Width Modulator
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
69
PWM Off State and Output Polarity
The default OFF state and the polarity of the PWM outputs are controlled by the PWMHI
and PWMLO option bits. The PWMHI option controls the OFF state and the polarity for the
PWM High outputs 0H, 1H, and 2H. The PWMLO option controls the OFF state and the
polarity for the Low outputs 0L, 1L, and 2L.
The OFF state is the value programmed in the option bit. For example, programming
PWMHI to a 1 sets the OFF state of PWM0H, 1H, and 2H to a High logic value and the
active state a Low logic value. Conversely, programming PWMHI to a 0 causes the OFF
state to be a Low logic value. PWMLO is programmed in a similar manner.
The relative polarity of the PWM channel pairs is controlled by the POLx bits in the PWM
Control 1 Register (PWMCTL1). These bits do not affect the OFF state programmed by
the option bits. Setting these bits inverts the High and Low of the selected channels. The
relative channel polarity controls the order in which the signals of a given PWM pair toggle. If a POLx bit is reset to zero, the High will first go active at the start of a PWM period.
Alternately., if the bit is set, the Low will go active first. A switching of the POLx bits is
synchronized with the PWM reload event (see below). In complementary mode, the
switch is additionally delayed until the end of the programmed deadband time.
PWM Channel Pair Enable
Following a Power-On Reset (POR), the PWM pins enter a high-impedance state. As the
internal reset proceeds, the PWM outputs are forced to the OFF state as determined by the
PWMHI and PWMLO OFF state option bits.
The PWM0EN, PWM1EN, and PWM2EN option bits enable the PWM0, PWM1, and PWM2
output pairs, respectively. If a PWM channel pair is not enabled, it remains in a highimpedance state after reset, and can be used as a general-purpose input.
PWM Reload Event
To prevent erroneous PWM pulse-widths and periods, registers that control the timing of
the output are buffered. Buffering causes all of the PWM compare values to update at the
same time. In other words, the registers that control the duty cycle and clock source prescaler only take effect upon a PWM reload event. A PWM reload event can be configured
to occur at the end of each PWM period, or only every 2, 4, or 8 PWM periods by setting
the RELFREQ bits in the PWM Control 1 Register (PWMCTL1). The software must indicate that all new values are ready by setting the READY bit in the PWM Control 0 Register
(PWMCTL0) to 1. After this READY bit has been set to 1, the buffered values take effect
at the next reload event.
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PRELIMINARY
PWM Off State and Output Polarity
Z8 Encore!® Motor Control Flash MCUs
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PWM Prescaler
The prescaler allows the PWM clock signal to be decreased by factors of 1, 2, 4, or 8 with
respect to the system clock. The PRES[1:0] bit field in the PWM Control 1 Register
(PWMCTL1) controls prescaler operation. This 2-bit PRES field is buffered so that the
prescale value only changes upon a PWM reload event.
PWM Period and Count Resolution
The PWM counter operates in two modes to allow edge-aligned outputs and centeraligned outputs. Figures 8 and 9 illustrate edge- and center-aligned PWM outputs. The
period of the PWM outputs, PERIOD, is determined by which mode the PWM counter is
operating. The active time of a PWM output is determined by the programmed duty cycle,
PWMDC, and the programmed deadband time, PWMDB.
The sections that follow these two figures describe the PWM timer modes and the registers that control the duty cycle and deadband time.
PWMxH
No Deadband
PWMxL
Period
PWMxH
Deadband Insertion
PWMxL
PWMDB
PWMDC
PWMDB
Figure 8. Edge-Aligned PWM Output
Pulse-Width Modulator
PRELIMINARY
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Z8FMC16100 Series Flash MCU
Product Specification
71
PWMxH
No Deadband
PWMxL
Period
PWMxH
Deadband Insertion
PWMxL
PWMDC
PWMDB
PWMDB
Figure 9. Center-Aligned PWM Output
Edge-Aligned Mode
In Edge-Aligned PWM mode, a 12-bit up counter creates the PWM period with a minimum resolution equal to the PWM clock source period. The counter counts up to the
reload value, resets to 000h, and then resumes counting.
Edge-Aligned PWM Mode Period =
Prescaler x (Reload Value +1)
fSYSTEMCLK
Center-Aligned Mode
In Center-Aligned PWM mode, a 12-bit up/down counter creates the PWM period with a
minimum resolution equal to twice the PWM clock source period. The counter counts up
to the reload value and then counts down to 0.
Center-Aligned PWM Mode Period =
PS024604-1005
2 x Prescaler x (Reload Value +1)
PRELIMINARY
fSYSTEMCLK
PWM Period and Count Resolution
Z8 Encore!® Motor Control Flash MCUs
Product Specification
72
PWM Duty Cycle Registers
The PWM Duty Cycle registers (PWM0HD, PWM0LD, PWM1HD, PWM1LD,
PWM2HD, PWM2LD) contain a 16-bit signed value, in which bit 15 is the sign bit. The
Duty Cycle value is compared to the current 12-bit unsigned PWM count value. If the
PWM Duty Cycle value is set less than or equal to 0, the PWM output is deasserted for the
full PWM period. If the PWM Duty Cycle value is set to a value greater than the PWM
reload value, the PWM output is asserted for the full PWM period.
Independent and Complementary PWM Outputs
The six PWM outputs are configurable to operate independently, or as three complementary pairs. Operation as six independent PWM channels is enabled by setting the INDEN
bit in the PWM Control 1 Register (PWMCTL1). The PWEN bit must be cleared to alter
this bit. In independent mode, each PWM output uses its own PWM duty cycle value.
When configured to operate as three complementary pairs, the PWM duty cycle values
PWM0HD, PWM1HD, and PWM2HD control the modulator output. In complementary
output mode, deadband time is also inserted.
The POLx bits in the PWM Control 1 Register (PWMCTL1) select the relative polarity of
the High and Low signals. As illustrated in Figures 8 and 9, when the POLx bits are
cleared to 0, the High PWM output will start in the ON state and transition to the OFF
state when the PWM timer count reaches the programmed duty cycle. The Low PWM
value starts in the OFF state and transitions to the ON state as the PWM timer count
reaches the value in the associated duty cycle register. Alternately, setting the POLx
causes the High output to start in the OFF state and the Low output to start in the ON state.
Manual Off-State Control of PWM Output Channels
Each PWM output can be controlled directly by the modulator logic or set to the OFF
state. To manually set the PWM outputs to the OFF state, set the OUTCTL bit and the associated OUTx bits in the PWM Output Control Register (PWMOUT). OFF state control
operates individually by channel. For example, suppressing the single output of a pair
allows the complementary channel to continue operating. Similarly, if the outputs are
operating independently, disabling one output channel has no effect on the other PWM
outputs.
Deadband Insertion
When the PWM outputs are configured to operate as complementary pairs, an 8-bit deadband value can be defined in the PWM Deadband Register (PWMDB). Inserting deadband
time causes the modulator to separate the deassertion of one PWM signal from the assertion of its complement. This separation is essential for many motor control applications in
that it prevents simultaneous turn-on of the High and Low drive transistors. The deadband
Pulse-Width Modulator
PRELIMINARY
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Z8FMC16100 Series Flash MCU
Product Specification
73
counter directly counts system clock cycles and is unaffected by PWM prescaler settings.
The width of this deadband is attributed to the number of system clock cycles specified in
the PWM Deadband Register (PWMDB). The minimum deadband duration is one system
clock, and the maximum duration is 255 system clocks. During the deadband period, both
PWM outputs of a complementary pair are deasserted. The generation of deadband time
does not alter the PWM period; instead, the deadband time is subtracted from the active
time of the PWM outputs. Figures 8 and 9 show the effect of deadband insertion on the
PWM output.
Minimum PWM Pulse Width Filter
The PWM modulator is capable of producing pulses as narrow as a single system clock
cycle in width. Because the response time of external drive circuits may be slower than the
period of a system clock, a filter is implemented to enforce a minimum-width pulse on the
PWM output pins. All output pulses, whether High or Low, must be at least the minimum
number of PWM clock cycles (see the PWM Prescaler section on page 70 for more information) in width as specified in the PWM Minimum Pulse Width Filter (PWMMPF) Register. If the expected pulse width is less than the threshold, the associated PWM output
does not change state until the duty cycle value has changed sufficiently to allow pulse
generation of an acceptable width. The minimum pulse width filter also accounts for the
duty cycle variation caused by the deadband insertion. The PWM output pulse is filtered
even if the programmed duty cycle is greater than the threshold, but the pulse width
decrease because of deadband insertion causes the pulse to be too narrow. The pulse width
filter value is calculated as:
roundup(PWMMPF) =
TMINPULSEOUT
TSYSTEMCLOCK x PWMPRESCALER
where TMINPULSEOUT is the shortest allowed pulse width on the PWM outputs, in seconds.
The PWM Minimum Pulse Width Filter Register can only be written when the PWEN bit is
cleared. Values written to this register when PWEN is set will be ignored.
Synchronization of PWM and Analog-to-Digital Converter
The analog-to-digital converter (ADC) on the Z8FMC16100 Series Flash MCU can be
synchronized with the PWM period. Enabling the PWM ADC trigger causes the PWM to
generate an ADC conversion signal at the end of each PWM period. Additionally, in center-aligned mode, the PWM will generate a trigger at the center of the period. Setting the
ADCTRIG bit in the PWM Control 0 Register (PWMCTL0) enables ADC synchronization.
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Minimum PWM Pulse Width Filter
Z8 Encore!® Motor Control Flash MCUs
Product Specification
74
PWM Timer and Fault Interrupts
The PWM generates interrupts to the eZ8 CPU upon any of the following events:
PWM Reload. The interrupt is generated at the end of a PWM period when a PWM register reload occurs (the READY bit is set).
PWM Fault. A fault condition is indicated by asserting any of the FAULT pins, or by the
assertion of the comparator.
Fault Detection and Protection
The Z8FMC16100 Series Flash MCU contains hardware and software fault controls that
allow rapid deassertion of all enabled PWM output signals. A logic Low on an external
fault pin (FAULT0 or FAULT1), or the assertion of the overcurrent comparator, forces the
PWM outputs to a predefined OFF state.
Similar deassertion of the PWM outputs can be accomplished in software by writing to the
PWMOFF bit in the PWM Control 0 Register. The PWM counter continues to operate while
the outputs are deasserted (made inactive) due to one of these fault conditions.
The fault inputs can be individually enabled through the PWM Fault Control Register. If a
fault condition is detected and the source is enabled, a fault interrupt is generated. The
PWM Fault Status Register (PWMFSTAT) is read to determine which fault source has
caused the interrupt.
After a fault has been detected, and after the PWM outputs are disabled, modulator control
of the PWM outputs can be reenabled either by software, or by deassertion of the FAULT
input signal. Selection of either method is made via the PWM Fault Control Register
(PWMFCTL). Configuration of the fault modes and reenable methods allows pulse-bypulse limiting and hard shutdown. When configured in automatic restart mode, the PWM
outputs are reengaged at beginning of the next PWM cycle (the master timer value is equal
to 0) if all fault signals are deasserted. In a software-controlled restart, all fault inputs must
be deasserted and all fault flags cleared.
The fault input pin is Schmitt-triggered. The input signal from the pin, as well as the comparators, pass though an analog filter to reject high-frequency noise.
The logic path from the fault sources to the PWM outputs is asynchronous, which ensures
that the fault inputs will force the PWM outputs to their OFF state, even if the system
clock is stopped.
PWM Operation in CPU Halt Mode
When the eZ8 CPU is operating in HALT mode, the Pulse-Width Modulator continues to
operate, if enabled. To minimize the current in HALT mode, the Pulse-Width Modulator
must be disabled by clearing the PWMEN bit to 0.
Pulse-Width Modulator
PRELIMINARY
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75
PWM Operation in CPU Stop Mode
When the eZ8 CPU is operating in STOP mode, the Pulse-Width Modulator is disabled,
because the system clock ceases to operate in STOP mode. The PWM outputs remain in
the same state as they were prior to entering STOP mode. In normal operation, the PWM
outputs must be disabled by the software prior to the CPU entering STOP mode. A fault
condition detected in STOP mode forces the PWM outputs to a predefined OFF state.
Observing the State of PWM Output Channels
The logic value of the PWM outputs can be sampled by reading the PWMIN register. If a
PWM channel pair is disabled (an option bit is not set), the associated PWM outputs are
forced to high-impedance, and can be used as general-purpose inputs.
PWM High and Low Byte Registers
The PWM High and Low Byte (PWMH and PWML) registers, shown in Tables 42 and
43, contain the current 12-bit PWM count value. Reads from PWMH cause the value in
PWML to be stored in a temporary holding register. A read from PWML always returns
this temporary register value.
Caution: Writing to the PWM High and Low Byte registers while the PWM is enabled is not recommended. There are no temporary holding registers for Write operations, so simultaneous 12-bit Writes are not possible.
If either the PWM High or Low Byte registers are written during counting, the 8-bit written value is placed in the counter (High or Low byte) at the next clock edge. The counter
continues counting from the new value.
Table 42. PWM High Byte Register (PWMH)
BITS
7
6
5
4
3
2
1
FIELD
Reserved
PWMH
RESET
0H
0H
R/W
R/W
R/W
ADDR
PS024604-1005
0
F2CH
PRELIMINARY
PWM Operation in CPU Stop Mode
Z8 Encore!® Motor Control Flash MCUs
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Table 43. PWM Low Byte Register (PWML)
BITS
7
6
5
4
3
FIELD
PWML
RESET
00H
R/W
R/W
ADDR
F2DH
2
1
0
PWMH and PWML—PWM High and Low Bytes
These 2 bytes, {PWMH[3:0], PWML[7:0]}, contain the current 12-bit PWM count value.
PWM Reload High and Low Byte Registers
The PWM Reload High and Low Byte (PWMRH and PWMRL) registers, shown in Table
44 and Table 45, store a 12-bit reload value, {PWMRH[3:0], PWMRL[7:0]}. The PWM
reload value is held in buffer registers. The PWM reload value written to the buffer registers is not used by the PWM generator until the next PWM reload event occurs. Reads
from these registers always return the values from the buffer registers.
Edge-Aligned PWM Mode Period =
Center-Aligned PWM Mode Period =
Prescaler x Reload Value
fPWMCLK
2 x Prescaler x Reload Value
fPWMCLK
Table 44. PWM Reload High Byte Register (PWMRH)
BITS
7
6
5
4
3
2
1
FIELD
Reserved
PWMRH
RESET
0H
FH
R/W
R/W
R/W
ADDR
Pulse-Width Modulator
0
F2EH
PRELIMINARY
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Z8FMC16100 Series Flash MCU
Product Specification
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Table 45. PWM Reload Low Byte Register (PWMRL)
BITS
7
6
5
4
3
FIELD
PWMRL
RESET
FF
R/W
R/W
ADDR
F2FH
2
1
0
PWMRH and PWMRL—PWM Reload Register High and Low
These two bytes form the 12-bit Reload value, {PWMRH[3:0], PWMRL[7:0]}. This value
sets the PWM period.
PWM 0–2 Duty Cycle High and Low Byte Registers
The PWM 0–2 H/L Duty Cycle High and Low Byte (PWMxDH and PWMxDL) registers,
shown in Table 46 and Table 47, set the duty cycle of the PWM signal. This 14-bit signed
value is compared to the PWM count value to determine the PWM output. Reads from
these registers always return the values from the temporary holding registers. The PWM
duty cycle value is not used by the PWM generator until the next PWM reload event
occurs.
PWM Duty Cycle Value
PWM Duty Cycle =
PWM Reload Value
Writing a negative value (DUTYH[7] = 1) forces the PWM to be OFF for the full PWM
period. Writing a positive value greater than the 12-bit PWM reload value forces the PWM
to be ON for the full PWM period.
Table 46. PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH)
BITS
7
FIELD
SIGN
Reserved
DUTYH
RESET
0
00
0_0000
R/W
R/W
R/W
R/W
ADDR
PS024604-1005
6
5
4
3
2
1
0
F30H, F32H, F34H, F36H, F38H, F3AH
PRELIMINARY
PWM 0–2 Duty Cycle High and Low Byte
Z8 Encore!® Motor Control Flash MCUs
Product Specification
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Table 47. PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)
BITS
7
6
5
4
3
2
FIELD
DUTYL
RESET
00H
R/W
R/W
ADDR
F31H, F33H, F35H, F37H, F39H, F3BH
Bit
Position
Value
(H)
[7]
SIGN
0
1
0
Description
Duty Cycle Sign
Duty Cycle is a positive two’s complement number.
1
Duty Cycle is a negative two’s complement number. Output is forced to the offstate.
[6:0], [7:0]
DUTYH and
DUTYL
PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5
and 6 of the High Byte are always 0). The value is compared to the current 12-bit
PWM count.
PWM Control 0 Register
The PWM Control 0 (PWMCTL0) Register, shown in Table 48, controls PWM operation.
Table 48. PWM Control 0 Register (PWMCTL0)
BITS
7
6
5
FIELD
PWMOFF
OUTCTL
ALIGN
RESET
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
Pulse-Width Modulator
4
3
2
1
0
READY
PWMEN
0
0
0
R/W
R/W
R/W
Reserved ADCTRIG Reserved
F20H
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
79
Bit
Position
Value
(H)
[7]
PWMOFF
0
Place PWM outputs in off-state
Disable modulator control of PWM pins. Outputs are in predefined off-state. This
is not dependent on the reload event.
1
Re-enable modulator control of PWM pins at next PWM reload event.
0
PWM Output Control
PWM outputs are controlled by the Pulse-Width Modulator.
[6]
OUTCTL
1
[5]
ALIGN
PWM outputs selectively disabled (set to off-state) according to values in the
OUTx bits of the PWMOUT register.
0
PWM Edge Alignment
PWM outputs are edge aligned.
1
PWM outputs are center aligned.
[4]
Reserved
[3]
ADCTRIG
Description
Reserved
ADC Trigger Enable
0
No ADC trigger pulses.
1
ADC trigger enabled.
[2]
Reserved
0
[1]
READY
0
PWM values (pre-scale, period, and duty cycle) are not ready. Do not use
values in holding registers at next PWM reload event
1
PWM values (pre-scale, period, and duty cycle) are ready. Transfer all values
from temporary holding registers to working registers at next PWM reload event.
[0]
PWMEN
Reserved
Values Ready for Next Reload Event
0
1
PS024604-1005
PWM Enable
Pulse-width modulator is disabled and enabled PWM output pins are forced to
default off-state. PWM master counter is stopped. Certain control registers may
only written in this state.
Pulse-width modulator is enabled and PWM output pins are enabled as outputs.
PRELIMINARY
PWM Control 0 Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
80
PWM Control 1 Register
The PWM Control 1 (PWMCTL1) Register, shown in Table 49, controls portions of PWM
operation.
Table 49. PWM Control 1 Register (PWMCTL1)
BITS
7
6
5
4
3
2
1
0
FIELD
RLFREQ[1:0]
INDEN
Pol45
Pol23
Pol10
PRES[1:0]
RESET
00
0
0
0
0
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F21H
ADDR
Bit
Position
Value
(H)
[7:6]
RLFREQ[1:0]
00
01
10
11
[5]
INDEN
Description
Reload Event Frequency
This bit field is buffered. Changes to the reload event frequency takes effect at
the end of the current PWM period. Reads always return the bit values from the
temporary holding register.
PWM reload event occurs at the end of every PWM period.
PWM reload event occurs once every 2 PWM periods.
PWM reload event occurs once every 4 PWM periods.
PWM reload event occurs once every 8 PWM periods.
0
Independent PWM Mode Enable
This bit may only be altered when PWEN (PWMCTL0) cleared.
PWM outputs operate as 3 complementary pairs.
1
PWM outputs operate as 6 independent channels.
1
Invert Ouput polarity for channel pair PWM2.
0
Non-inverted polarity for channel pair PWM2.
[3]
Pol1
1
Invert Ouput polarity for channel pair PWM1.
0
Non-inverted polarity for channel pair PWM1.
[2]
Pol0
1
Invert Ouput polarity for channel pair PWM0.
0
Non-inverted polarity for channel pair PWM0.
[4]
Pol2
Pulse-Width Modulator
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
81
Bit
Position
Value
(H)
[1:0]
PRES
00
01
10
11
Description
PWM Prescaler
The prescaler divides down the PWM input clock (either the system clock or the
PWMIN external input). This field is buffered. Changes to this field take effect at
the next PWM reload event. Reads always return the values from the
temporary holding register.
Divide by 1
Divide by 2
Divide by 4
Divide by 8
PWM Deadband Register
The PWM Deadband (PWMDB) Register, shown in Table 50, stores the 8-bit PWM deadband value. This register determines the number of system clock cycles inserted as deadtime in complementary output mode. The minimum deadband value is 1.
Table 50. PWM Dead-Band Register (PWMDB)
BITS
7
6
5
4
3
FIELD
PWMDB[7:0]
RESET
01H
R/W
R/W
ADDR
F22H
Bit
Position
[7:0]
PWMDB
Value
(H)
2
1
0
Description
PWM Dead band
Sets the PWM dead band period for which both PWM outputs of a
complementary PWM output pair are deasserted.
Note: This register can only be written when PWEN is cleared.
PS024604-1005
PRELIMINARY
PWM Deadband Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
82
PWM Minimum Pulse Width Filter
The value in the PWM Minimum Pulse Width Filter (PWMMPF) Register, shown in Table
51, determines the minimum width pulse, either high or low, that can be generated by the
PWM module. The minimum pulse width period is calculated as:
TMINPULSEOUT =
PWMDB + PWMMPF
TSYSTEMCLOCK x PWMPrescale
Caution: A Value other than 00H must be written to the PWMMPF registor or the PWM output
waveform will be distorted!
Table 51. PWM Minimum Pulse Width Filter (PWMMPF)
BITS
7
6
5
4
3
FIELD
PWMMPF[7:0]
RESET
00H
R/W
R/W
ADDR
F23H
Bit
Position
Value
(H)
2
1
0
Description
[7:0]
PWMMPF
PWM Minimum Pulse Filter
Sets the minimum allowed output pulse width in PWM clock cycles.
Note: This register can only be written when PWEN is cleared.
PWM Fault Mask Register
The PWM Fault Mask (PWMFM) Register, shown in Table 52, enables individual fault
sources. PWM behaviour when an input is asserted is determined by the PWM Fault Control Register (PWMFCTL).
Table 52. PWM Fault Mask Register (PWMFM)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
DBGMSK
Reserved
F1MASK
C0MASK
FMASK
RESET
00
0
000
0
0
0
R/W
R
R/W
R
R/W
R/W
R/W
ADDR
Pulse-Width Modulator
F24H
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
83
Bit
Position
Value
(H)
[7:6]
Reserved
[5]
DBGMSK
Must be 0.
0
Debug Entry Fault Mask
Entering CPU DEBUG Mode generates a PWM fault.
1
Entering CPU DEBUG mode does not generate a PWM fault.
[4:3]
Reserved
[2]
F1MASK
[1]
C0MASK
[0]
F0MASK
Description
Must be 0.
0
Fault 1 Fault Mask
Fault 1 generates a PWM fault.
1
Fault 1 does not generate a PWM fault.
0
Comparator Fault Mask
Comparator generates a PWM fault.
1
Comparator does not generate a PWM fault.
0
Fault Pin Mask
Fault0 pin generates a PWM fault.
1
Fault0 pin does not generate a PWM fault.
Note: This register can only be written when PWEN is cleared.
PWM Fault Status Register
The PWM Fault Status (PWMFSTA) Register, shown in Table 53, provides status of fault
inputs and timer reload.. The fault flags indicate which fault source is active. If a fault
source is masked the flag in this register will not be set if the source is asserted. The
reload flag is set when the timer compare vaules are updated. Clear flags by writing a 1 to
the flag bits. Fault flag bits can only be cleared if the associated fault source has deasserted.
PS024604-1005
PRELIMINARY
PWM Fault Status Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
84
Table 53. PWM Fault Status Register (PWMFSTAT)
BITS
7
6
FIELD
RLDFlag
RESET
U
0
R/W
R/W1C
R
5
2
1
0
Reserved
F1FLAG
C0FLAG
FFLAG
U
00
U
U
U
R/W1C
R
R/W1C
R/W1C
R/W1C
Reserved DBGFLAG
Value
(H)
[7]
RLDFlag
[6]
Reserved
Description
Reload Flag
This bit is set and latched when a PWM timer reload occurs. Writing a 1 to this bit
clears the flag.
0
[5]
DBGFLAG
[4:3]
Reserved
3
F25H
ADDR
Bit
Position
4
Reserved
Always reads 0.
Debug Flag
This bit is set and latched when DEBUG mode is entered. Writing a 1 to this bit
clears the flag.
0
Reserved
Always reads 0.
[2]
F1FLAG
Fault1 Flag
This bit is set and latched when Fault1 is asserted. Writing a 1 to this bit clears
the flag.
[1]
C0FLAG
Comparator 0 Flag
This bit is set and latched when Comparator is asserted. Writing a 1 to this bit
clears the flag.
[0]
FFLAG
Fault Flag
This bit is set and latched when the FAULT0 input is asserted. Writing a 1 to this
bit clears the flag.
Note: For this register, W1C means you must write one to clear the flag.
Pulse-Width Modulator
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
85
PWM Fault Control Register
The PWM Fault Control (PWMFCTL) Register, shown in Table 54, determines how the
PWM recovers from a fault condition. Settings in this register select automatic or software
controlled PWM restart.
Table 54. PWM Fault Control Register (PWMFCTL)
BITS
7
6
5
FIELD
Reserved
DBGRST
RESET
0
0
0
R/W
R/W
R/W
R/W
4
Value
(H)
[7]
Reserved
0
[6]
DBGRST
0
CMPINT
CMPRST
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Fault0INT Fault0RST
Description
DebugRestart
Automatic recovery. PWM resumes control of outputs when all fault sources have
deasstered and a new PWM period begins.
Software controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted and all fault flags are cleared and a PWM reload occurs
Fault 1 Interrupt
0
Interrupt on comparator assertion disabled.
1
Interrupt on comparator assertion enabled.
0
Fault 1 Restart
Automatic recovery. PWM resumes control of outputs when all fault sources have
deasstered.
1
[2]
CMP0RST
0
Reserved.
1
[3
CMP0INT
1
F28H
Bit
Position
[4]
Fault1RST
2
Fault1INT Fault1RST
ADDR
[5]
Fault1INT
3
Software controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted and all fault flags are cleared and a PWM reload occurs
Comparator 0 Interrupt
0
Interrupt on comparator 0 assertion disabled.
1
Interrupt on comparator 0 assertion enabled.
0
Comparator 0 Restart
Automatic recovery. PWM resumes control of outputs when all fault sources have
deasstered.
1
PS024604-1005
Software controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted and all fault flags are cleared and a PWM reload occurs
PRELIMINARY
PWM Fault Control Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
86
Bit
Position
Value
(H)
Description
[1]
Fault0INT
0
Interrupt on Fault0 pin assertion disabled.
1
Interrupt on Fault0 pin assertion enabled.
0
Fault 0 Restart
Automatic recovery. PWM resumes control of outputs when all fault sources have
deasstered.
Fault 0 Interrupt
[0]
Fault0RST
Software controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted and all fault flags are cleared and a PWM reload occurs
1
Note: This register can only be written when PWEN is cleared.
PWM Input Sample Register
PWM pin values are sampled by reading the PWM Input Sample Register, shown in Table
55.
Table 55. PWM Input Sample Register (PWMIN)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
FAULT
IN2L
IN2H
IN1L
IN1H
IN0L
IN0H
RESET
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F26H
ADDR
Bit
Position
Value
(H)
[7]
Reserved
[6]
FAULT
[5:0]
IN2L/IN2H/
IN1L/IN1H/
IN0L/IN0H
Description
Must be 0.
0
Sample Fault0 pin
A Low level signal was read on the FAULT pin.
1
A High level signal was read on the FAULT pin.
0
Sample PWM pins
A Low level signal was read on the pins.
1
A High level signal was read on the pins.
Pulse-Width Modulator
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
87
PWM Output Control Register
The PWM Output Control (PWMOUT) Register, shown in Table 56, enables modulator
control of the six PWM output signals. Output control is enabled by the OUTCTL bit in
the PWMCTL0 register. The Pulse-Width Modulator continues to operate, but has no
effect on the disabled PWM pins. If a fault condition is detected all PWM outputs are
forced to their selected OFF state.
.
Table 56. PWM Output Control Register (PWMOUT)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
Reserved
OUT2L
OUT2H
OUT1L
OUT1H
OUT0L
OUT0H
RESET
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
F27H
ADDR
Bit
Position
Value
(H)
[7,6]
Reserved
[5, 3, 1]
OUT2L/
OUT1L/
OUT0L
[4, 2, 0]
OUT2H/
OUT1H/
OUT0H
Description
Must be 0.
0
PWM 2L/1L/0L Output Configuration
PWM 2L/1L/0L output signal is enabled and controlled by PWM.
1
PWM 2L/1L/0L output signal is in low-side off-state.
0
PWM 2H/1H/0H Output Configuration
PWM 2H/1H/0H output signal is enabled and controlled by PWM.
1
PWM 2H/1H/0H output signal is in high-side off-state.
Current Sense ADC Trigger Control Register
An ADC trigger is generated when the PWM output signals match the state specified by
the Current-Sense ADC-Trigger control register. The match logic is an AND-OR tree that
will solve to true if based on the register settings. An ADC conversion will be triggered on
the rising edge of this signal. The logic equation for the adc-trigger is:
ADCTRIGGER = CSTPOL ^ (
( HEN & PWM0H &PWM1H & PWM2H) |
( LEN & PWM0L &PWM1L & PWM2L) |
( nHEN & !PWM0H &!PWM1H & !PWM2H) |
( nLEN & !PWM0H & !PWM1H & !PWM2H) )
PS024604-1005
PRELIMINARY
PWM Output Control Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
88
where
•
•
•
•
the ^ symbol indicates a logical exclusive OR (XOR) function
the & symbol indicates a logical AND function
the | symbol indicates a logical OR function
the ! symbol indicates a logical NOT function
The combinations of polarity, enable, and PWM signals allow the logic to generate a
ADC-trigger under a wide variety of operating conditions. The HEN, LEN, nHEN, and
nLEN bits enable a group in the or logic. The CSTWMx bits allow the level of the PWM
output signals to control the equation. If a CSTPWMx bit is cleared, the value of the associated PWMx output will always evaluate to a TRUE condition in the equation. Note that
these bits DO NOT affect the actual PWM outputs.
.
Table 57. Current-Sense Trigger Control Register (PWMSHC)
BITS
7
6
5
4
3
2
1
0
FIELD
CSTPOL
HEN
NHEN
LEN
NLEN
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CSTPWM2 CSTPWM1 CSTPWM0
F29H
ADDR
Bit
Position
Value
(H)
Description
[7]
CSTPOL
0
Sample Hold Polarity
Hold when terms are active
1
Hold when terms are not active
0
High Side Active enable
Ignore Product of PWM0H, PWM1H, PWM2H in Sample/Hold equation
1
Hold when PWM0H, PWM1H, PWM2H are all active
0
High Side inactive enable
Ignore Product of PWM0H, PWM1H, PWM2H in Sample/Hold equation
1
Hold when are all active
0
Low Side Active enable
Ignore Product of PWM0L, PWM1L, PWM2L in Sample/Hold equation
1
Hold when PWM0L, PWM1L, PWM2L are all active
[6]
HEN
[5]
NHEN
[4]
LEN
Pulse-Width Modulator
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
89
Bit
Position
Value
(H)
[3]
NLEN
0
Low Side Inactive enable
Ignore Product of PWM0L, PWM1L, PWM2L in Sample/Hold equation
1
Hold when PWM0L, PWM1L, PWM2L are all active
0
PWM Channel2 Sample/Hold Enable
Channel 2 terms are not used in Sample/Hold Equation
1
Channel 2 terms are used in Sample/Hold Equation
0
PWM Channel1 Sample/Hold Enable
Channel 1 terms are not used in Sample/Hold Equation
1
Channel 1 terms are used in Sample/Hold Equation
0
PWM Channel0 Sample/Hold Enable
Channel 0 terms are not used in Sample/Hold Equation
1
Channel 0 terms are used in Sample/Hold Equation
[2]
CSTPWM2
[1]
CSTPWM1
[0]
CSTPWM0
PS024604-1005
Description
PRELIMINARY
Current Sense ADC Trigger Control Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
90
Pulse-Width Modulator
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
91
General-Purpose Timer
The Z8FMC16100 Series Flash MCU contains one 16-bit reloadable timer that can be
used for timing, event counting, or generation of pulse-width modulated (PWM) signals.
Features
•
•
•
•
•
•
•
16-bit reload counter
Programmable prescaler with prescale values from 1 to 128
PWM output generation (single or differential)
Capture and compare capability
External input pin for event counting, clock gating, or capture signal
Complementary Timer Output pins
Timer interrupt
Architecture
Capture and compare capability measures the velocity from a tachometer wheel or reads
sensor outputs for rotor position for brushless DC motor commutation. Figure 10 illustrates the architecture of the timer.
PS024604-1005
PRELIMINARY
Features
Z8 Encore!® Motor Control Flash MCUs
Product Specification
92
Timer Block
Data
Bus
Timer Control
16-Bit
Reload Register
System
Clock
Compare
Block
Control
Interrupt,
PWM, and
Timer Output
Control
Timer
Interrupt
TOUT
TOUT
Gate Input
16-Bit
PWM/Compare
Compare
16-Bit Counter
with Prescaler
Timer
Input
Capture Input
Figure 10. Timer Block Diagram
Operation
The general-purpose timer is a 16-bit up-counter. In normal operation, the timer is initialized to 0001h. After it is enabled, the timer counts up to the value contained in the Reload
High and Low Byte registers, then resets to 0001h. The counter either halts or continues,
depending on its current mode of operation.
Minimum time-out delay (1 system clock in duration) is set by loading the value 0001h
into the Timer Reload High and Low Byte registers and setting the prescale value to 1.
Maximum time-out delay (216 x 27 system clocks) is set by loading the value 0000h into
the Timer Reload High and Low Byte registers and setting the prescale value to 128.
When the timer reaches FFFFh, the timer rolls over to 0000h.
If the reload register is set to a value less than the current counter value, the counter continues counting until reaching FFFFh, rolls over to 0000h, and continues counting until
reaching the reload value, then resets to 0001h.
General-Purpose Timer
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
93
Timer Operating Modes
The timers can be configured to operate in the following eleven modes, each of which is
described in this section:
•
•
•
•
•
•
•
•
•
•
•
ONE-SHOT mode
TRIGGERED ONE-SHOT mode
CONTINUOUS mode
COUNTER mode
COMPARATOR COUNTER mode
PWM SINGLE OUTPUT mode
PWM DUAL OUTPUT mode
CAPTURE RESTART mode
CAPTURE COMPARE mode
COMPARE mode
GATED mode
One-Shot Mode
In ONE-SHOT mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. The Timer Input is the system clock. After reaching
this reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001h. The timer is automatically disabled and stops
counting.
If the Timer Output alternate function is enabled, the Timer Output pin changes state for
one system clock cycle (from Low to High, then back to Low if TPOL = 0) at timer reload.
If the user chooses, the Timer Output can undergo a permanent state change upon OneShot time-out, as follows:
1. Set the TPOL bit in the Timer Control 1 Register to the start value before beginning
ONE-SHOT mode.
2. After starting the timer, set TPOL to the opposite value.
The steps for configuring a timer for ONE-SHOT mode and initiating a count are as follows:
1. Write to the Timer Control registers to:
a. Disable the timer.
b. Configure the timer for ONE-SHOT mode.
c. Set the prescale value.
PS024604-1005
PRELIMINARY
Timer Operating Modes
Z8 Encore!® Motor Control Flash MCUs
Product Specification
94
d. If using the Timer Output alternate function, set the initial output level (High or
Low) using the TPOL bit.
e. Set the interrupt mode.
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
The timer period is calculated by the following equation (Start Value is typically = 1):
One-Shot Mode Time-Out Period(s) =
(Reload Value – Start Value + 1) x Prescaler
System Clock Frequency (Hz)
Triggered One-Shot Mode
In TRIGGERED ONE-SHOT mode, the timer operates as follows:
1. The Timer idles until a trigger is received. The timer trigger is taken from the Timer
Input pin. The TPOL bit in the Timer Control 1 Register selects whether the trigger
occurs on the rising edge or the falling edge of the Timer Input signal.
2. Following the trigger event, the timer counts system clocks up to the 16-bit reload
value stored in the Timer Reload High and Low Byte registers.
3. Upon reaching the reload value, the timer outputs a pulse on the Timer Output pin,
generates an interrupt, and resets the count value in the Timer High and Low Byte registers to 0001h. The duration of the output pulse is a single system clock. The TPOL
bit also sets the polarity of the output pulse.
4. The timer idles until the next trigger event. Trigger events that occur while the timer is
responding to a previous trigger are ignored.
The steps for configuring Timer 0 in TRIGGERED ONE-SHOT mode and initiating operation are as follows:
1. Write to the Timer Control registers to:
a. Disable the timer.
b. Configure the timer for TRIGGERED ONE-SHOT mode.
General-Purpose Timer
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
95
c. Set the prescale value.
d. If using the Timer Output alternate function, set the initial output level (High or
Low) via the TPOL bit.
e. Set the INTERRUPT mode.
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 Register to enable the timer. Counting does not start until
the appropriate input transition occurs.
The timer period is calculated by the following equation (Start Value is typically = 1):
Triggered One-Shot Mode Time-Out Period(s) =
Note:
(Reload Value – Start Value + 1) x Prescaler
System Clock Frequency (Hz)
The one-shot delay from input trigger to output includes the above-defined time-out
period, plus an additional delay of 2–3 system clock cycles, due to the synchronization of
the input trigger.
Continuous Mode
In CONTINUOUS mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. After reaching the reload value, the timer generates
an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h,
and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer
Output pin changes state (from Low to High or from High to Low) after timer reload.
The steps for configuring a timer for CONTINUOUS mode and initiating the count are as
follows:
1. Write to the Timer Control registers to:
a. Disable the timer.
b. Configure the timer for CONTINUOUS mode.
c. Set the prescale value.
PS024604-1005
PRELIMINARY
Timer Operating Modes
Z8 Encore!® Motor Control Flash MCUs
Product Specification
96
d. If using the Timer Output alternate function, set the initial output level (High or
Low) via TPOL.
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001h). This setting only affects the first pass in CONTINUOUS mode. After the first
timer reload in CONTINUOUS mode, counting begins at the reset value of 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload period.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
The timer period is calculated by the following equation:
Continuous Mode Time-Out Period(s) =
Reload Value x Prescaler
System Clock Frequency (Hz)
If an initial starting value other than 0001h is loaded into the Timer High and Low Byte
registers, use the ONE-SHOT mode equation to determine the first time-out period.
Counter and Comparator Counter Modes
In COUNTER mode, the timer counts input transitions from a GPIO port pin. The Timer
Input is taken from the associated GPIO port pin. The TPOL bit in the Timer Control 1
Register selects whether the count occurs on the rising edge or the falling edge of the
Timer Input signal. In COUNTER mode, the prescaler is disabled.
Caution: The input frequency of the Timer Input signal must not exceed one-fourth the system
clock frequency.
In COMPARATOR COUNTER mode, the timer counts output transitions from an analog
comparator output. Timer 0 takes its input from the output of the comparator. The TPOL bit
in the Timer Control 1 Register selects whether the count occurs on the rising edge or the
falling edge of the comparator output signal. In COMPARATOR COUNTER mode, the
prescaler is disabled.
Caution: The frequency of the comparator output signal must not exceed one-fourth the system
clock frequency.
General-Purpose Timer
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
97
After reaching the reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001h, and counting resumes.
If the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reload.
The steps for configuring a timer for COUNTER and COMPARATOR COUNTER modes
and initiating the count are as follows:
1. Write to the Timer Control registers to:
a. Disable the timer.
b. Configure the timer for COUNTER or COMPARATOR COUNTER mode.
c. Select either the rising edge or falling edge of the Timer Input or comparator output signal for the count. This choice also sets the initial logic level (High or Low)
for the Timer Output alternate function. However, the Timer Output function does
not have to be enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
setting only affects the first pass in the counter modes. After the first timer reload,
counting begins at the reset value of 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function
(COUNTER mode).
6. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
7. Write to the Timer Control 1 Register to enable the timer.
PWM Single and Dual Output Modes
In PWM SINGLE OUTPUT mode, the timer outputs a Pulse-Width Modulator (PWM)
output signal through a GPIO port pin. In PWM DUAL OUTPUT mode, the timer outputs
a Pulse-Width Modulator (PWM) output signal and also its complement through two
GPIO port pins. The timer first counts up to the 16-bit PWM match value stored in the
Timer PWM High and Low Byte registers. When the timer count value matches the PWM
value, the Timer Output toggles. The timer continues counting until it reaches the reload
value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload
value, the timer generates an interrupt, the count value in the Timer High and Low Byte
registers is reset to 0001h, and counting resumes.
PS024604-1005
PRELIMINARY
Timer Operating Modes
Z8 Encore!® Motor Control Flash MCUs
Product Specification
98
The Timer Output signal begins with a value equal to TPOL and then transitions to TPOL
when the timer value matches the PWM value. The Timer Output signal returns to TPOL
after the timer reaches the reload value, and is reset to 0001h.
In PWM DUAL OUTPUT mode, the timer also generates a second PWM output signal,
Timer Output Complement (TOUT). A programmable deadband can be configured (PWMD
field) to delay (0–128 system clock cycles) the Low to a High (inactive to active) output
transitions on these two pins. This configuration ensures a time gap between the deassertion of one PWM output to the assertion of its complement.
The steps for configuring a timer for either PWM SINGLE or DUAL OUTPUT mode and
initiating PWM operation are as follows:
1. Write to the Timer Control registers to:
a. Disable the timer.
b. Configure the timer for the selected PWM mode.
c. Set the prescale value.
d. Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function with the TPOL bit.
e. Set the deadband delay (DUAL OUTPUT mode) with the PWMD field.
2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001h). The starting count value only affects the first pass in PWM mode. After
the first timer reset in PWM mode, counting begins at the reset value of 0001h.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM
period). The reload value must be greater than the PWM value.
5. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
6. Configure the associated GPIO port pin(s) for the Timer Output alternate function.
7. Write to the Timer Control 1 Register to enable the timer and initiate counting.
The PWM period is determined by the following equation:
PWM Period(s) =
Reload Value x Prescaler
System Clock Frequency (Hz)
If an initial starting value other than 0001h is loaded into the Timer High and Low Byte
registers, use the ONE-SHOT mode equation to determine the first PWM time-out period.
General-Purpose Timer
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
99
If TPOL is set to 0, the ratio of the PWM output High time to the total period is determined
by the equation:
PWM Output High Time Ratio (%) =
Reload Value – PWM Value
Reload Value
x 100
If TPOL is set to 1, the ratio of the PWM output High time to the total period is determined
by the equation:
PWM Output High Time Ratio (%) =
PWM Value
Reload Value
x 100
Capture Modes
There are three capture modes that provide slightly different methods for recording the
time of, or time interval between, Timer Input events. These modes are CAPTURE mode,
CAPTURE RESTART mode, and CAPTURE COMPARE mode. In all three modes, when
the appropriate Timer Input transition (capture event) occurs, the timer counter value is
captured and stored in the PWM High and Low Byte registers. The TPOL bit in the Timer
Control 1 Register determines whether the Capture occurs on a rising edge or a falling
edge of the Timer Input signal. The TICONFIG bit determines whether interrupts are generated on capture events, reload events, or both. The INCAP bit in Timer Control 0 Register clears to indicate an interrupt caused by a reload event and sets to indicate the timer
interrupt is caused by an input capture event.
There is a delay from the input event to the timer capture of 2–3 system clock cycles, due
to internal synchronization logic.
If the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reload. The initial value is determined
by the TPOL bit.
Capture Mode. In CAPTURE mode, and after it is enabled, the timer counts continuously
and rolls over from FFFFh to 0000h. When the capture event occurs, the timer counter
value is captured and stored in the PWM High and Low Byte registers, an interrupt is generated, and the timer continues counting. The timer continues counting up to the 16-bit
reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the
reload value, the timer generates an interrupt and continues counting.
Capture Restart Mode. In CAPTURE RESTART mode, after it is enabled, the timer
counts continuously until either the capture event occurs or the timer count reaches the 16bit compare value stored in the Timer Reload High and Low Byte registers. If the capture
event occurs first, the timer counter value is captured and stored in the PWM High and
Low Byte registers, an interrupt is generated, the count value in the Timer High and Low
Byte registers is reset to 0001h, and counting resumes. If no capture event occurs, upon
PS024604-1005
PRELIMINARY
Timer Operating Modes
Z8 Encore!® Motor Control Flash MCUs
Product Specification
100
reaching the reload value, the timer generates an interrupt, the count value in the Timer
High and Low Byte registers is reset to 0001h, and counting resumes.
Capture/Compare Mode. CAPTURE/COMPARE mode is identical to CAPTURE
RESTART mode, except that counting does not start until the first external Timer Input
transition occurs. Every subsequent transition (after the first) of the Timer Input signal
captures the current count value. When the capture event occurs, an interrupt is generated,
the count value in the Timer High and Low Byte registers is reset to 0001h, and counting
resumes. If no capture event occurs, upon reaching the compare value, the timer generates
an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h,
and counting resumes.
The steps for configuring a timer for one of these capture modes and initiating the count
are as follows:
1. Write to the Timer Control registers to:
a. Disable the timer.
b. Configure the timer for the selected capture mode.
c. Set the prescale value.
d. Set the capture edge (rising or falling) for the Timer Input.
e. Configure the timer interrupt to be generated at the input capture event, the reload
event, or both, by setting the TICONFIG field.
2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001h).
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control 1 Register to enable the timer. In CAPTURE and CAPTURE RESTART modes, the timer begins counting. In CAPTURE COMPARE
mode, the timer does not start counting until the first input transition occurs.
In capture modes, the elapsed time from a timer start to a capture event can be calculated
using the following equation (Start Value is typically = 1):
Capture Elapsed Time (s) =
General-Purpose Timer
(Capture Value – Start Value +1) x Prescale
System Clock Frequency (Hz)
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
101
Compare Mode
In COMPARE mode, the timer counts up to the 16-bit compare value stored in the Timer
Reload High and Low Byte registers. After reaching the compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001h). If the
Timer Output alternate function is enabled, the Timer Output pin changes state (from Low
to High or from High to Low).
If the timer reaches FFFFh, the timer rolls over to 0000h and continues counting.
The steps for configuring a timer for COMPARE mode and initiating the count are as follows:
1. Write to the Timer Control registers to:
a. Disable the timer.
b. Configure the timer for COMPARE mode.
c. Set the prescale value.
d. Set the initial logic level (High or Low) for the Timer Output alternate function, if
appropriate.
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
The compare time is calculated by the following equation (Start Value is typically = 1):
Compare Mode Time (s) =
(Compare Value – Start Value +1) x Prescale
System Clock Frequency (Hz)
Gated Mode
In GATED mode, the timer counts only when the Timer Input signal is in its active state,
as determined by the TPOL bit in the Timer Control 1 Register. When the Timer Input signal is active, counting begins. A timer interrupt is generated when the Timer Input signal
transitions from active to inactive state, a timer reload occurs, or both, depending on
TICONFIG[1:0]. To determine if a Timer Input signal deassertion generated the interrupt, read the associated GPIO input value and compare it to the value stored in the TPOL
bit.
PS024604-1005
PRELIMINARY
Timer Operating Modes
Z8 Encore!® Motor Control Flash MCUs
Product Specification
102
The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low
Byte registers. When reaching the reload value, the timer generates an interrupt, the count
value in the Timer High and Low Byte registers is reset to 0001h, and counting continues
as long as the Timer Input signal is active. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer reload.
The steps for configuring a timer for GATED mode and initiating the count are as follows:
1. Write to the Timer Control registers to:
a. Disable the timer.
b. Configure the timer for GATED mode.
c. Set the prescale value.
d. Select the active state of the Timer Input via the TPOL bit.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
setting only affects the first pass in GATED mode. After the first timer reset in
GATED mode, counting begins at the reset value of 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the timer interrupt to be generated only at the input deassertion event, the
reload event, or both, by setting the TICONFIG field of the Timer Control 0 Register.
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control 1 Register to enable the timer.
8. The timer counts when the Timer Input is equal to the TPOL bit.
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This Read has
no effect on timer operation. When the timer is enabled and the Timer High Byte Register
is read, the contents of the Timer Low Byte Register are placed into a holding register. A
subsequent Read from the Timer Low Byte Register returns the value in the holding register. This operation allows accurate Reads of the full 16-bit timer count value while
enabled. When the timer is not enabled, a Read from the Timer Low Byte Register returns
the actual value in the counter.
Timer 0 High and Low Byte Registers
The Timer 0 High and Low Byte (T0H and T0L) registers, shown in Tables 58 and 59,
contain the current 16-bit timer count value. When the timer is enabled, a Read from T0H
General-Purpose Timer
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
103
causes the value in T0L to be stored in a temporary holding register. A Read from T0L
always returns this temporary register when the timer is enabled. When the timer is disabled, Reads from the T0L are direct from this temporary register.
Caution: Writing to the Timer High and Low Byte registers while the timer is enabled is not recommended. There are no temporary holding registers available for Write operations;
therefore, simultaneous 16-bit Writes are not possible.
If either the Timer High or Low Byte registers are written during counting, the 8-bit written value is placed in the counter (High or Low Byte) at the next clock edge. The counter
continues counting from the new value.
Table 58. Timer 0 High Byte Register (T0H)
BITS
7
6
5
4
FIELD
TH
RESET
00H
R/W
R/W
ADDR
F00H
3
2
1
0
3
2
1
0
Table 59. Timer 0 Low Byte Register (T0L)
BITS
7
6
5
4
FIELD
TL
RESET
01H
R/W
R/W
ADDR
F01H
TH and TL—Timer High and Low Bytes
These two bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value.
PS024604-1005
PRELIMINARY
Timer 0 High and Low Byte Registers
Z8 Encore!® Motor Control Flash MCUs
Product Specification
104
Timer 0 Reload High and Low Byte Registers
The Timer 0 Reload High and Low Byte (T0RH and T0RL) registers, shown in Tables 60
and 61, store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer
Reload High Byte Register are stored in a temporary holding register. When a Write to the
Timer Reload Low Byte Register occurs, the temporary holding register value is written to
the Timer High Byte Register. This operation allows simultaneous updates of the 16-bit
timer reload value.
Table 60. Timer 0 Reload High Byte Register (T0RH)
BITS
7
6
5
4
3
FIELD
TRH
RESET
FFH
R/W
R/W
ADDR
F02H
2
1
0
2
1
0
Table 61. Timer 0 Reload Low Byte Register (T0RL)
BITS
7
6
5
4
3
FIELD
TRL
RESET
FF
R/W
R/W
ADDR
F03H
TRH and TRL—Timer Reload Register High and Low
These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets the
maximum count value which initiates a timer reload to 0001H.
General-Purpose Timer
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
105
Timer 0 PWM High and Low Byte Registers
The Timer 0 PWM High and Low Byte (T0PWMH and T0PWML) registers, shown in
Tables 62 and 63, define Pulse-Width Modulator (PWM) operations. These registers also
store the timer counter values for the Capture modes.
The two bytes {PWMH[7:0], PWML[7:0]} form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the Timer Control 1 Register (T0CTL1).
The T0PWMH and T0PWML registers also store the 16-bit captured timer value when
operating in CAPTURE or CAPTURE/COMPARE modes.
Table 62. Timer 0 PWM High Byte Register (T0PWMH)
BITS
7
6
5
4
3
FIELD
PWMH
RESET
00H
R/W
R/W
ADDR
F04H
2
1
0
2
1
0
Table 63. Timer 0 PWM Low Byte Register (T0PWML)
BITS
7
6
5
4
3
FIELD
PWML
RESET
00H
R/W
R/W
ADDR
F05H
PWMH and PWML—Pulse-Width Modulator High and Low Bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the Timer Control 1 register (T0CTL1).
The T0PWMH and T0PWML registers also store the 16-bit captured timer value when
operating in CAPTURE or CAPTURE/COMPARE modes.
PS024604-1005
PRELIMINARY
Timer 0 PWM High and Low Byte Registers
Z8 Encore!® Motor Control Flash MCUs
Product Specification
106
Timer 0 Control Registers
Two Timer 0 control registers determine timer configuration (T0CTL0) and operation
(T0CTL1).
Timer 0 Control 0 Register
The Timer 0 Control 0 (T0CTL0) Register together with the Timer 0 Control 1 (T0CTL1)
Register, determines the timer configuration and operation. See Table 64.
Table 64. Timer 0 Control 0 Register (T0CTL0)
BITS
7
6
5
FIELD
TMODE[3]
TICONFIG
TINSEL
PWMD
INCAP
RESET
0
00
0
000
0
R/W
R/W
R/W
R/W
R/W
R
3
2
1
0
F06H
ADDR
Bit
Position
4
Value
(H)
Description
[7]
TMODE[3]
Timer Mode High Bit
This bit along with the TMODE[2:0] field in the T0CTL1 register determines the
operating mode of the timer. This is the most significant bit of the Timer mode
selection value. See the T0CTL1 register description for additional details.
[6–5]
TICONFIG
Timer Interrupt Configuration—This field configures timer interrupt definitions.
These bits affect all modes. The effect per mode is explained below:
ONE SHOT, CONTINUOUS, COUNTER, PWM, COMPARE, DUAL PWM,
TRIGGERED ONE-SHOT, COMPARATOR COUNTER:
0x Timer interrupt occurs on reload.
10 Timer interrupts are disabled.
11 Timer Interrupt occurs on reload.
GATED:
0x Timer interrupt occurs on reload or inactive gate edge.
10 Timer interrupt occurs on inactive gate edge.
11 Timer interrupt occurs on reload.
CAPTURE, CAPTURE/COMPARE, CAPTURE RESTART:
0x Timer interrupt occurs on reload and capture.
10 Timer interrupt occurs on capture only.
11 Timer interrupt occurs on reload only
General-Purpose Timer
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
107
Bit
Position
[4]
TINSEL
Value
(H)
0
1
Timer Input Select
Timer input is the Timer input pin.
Timer input is the comparator output.
000
001
010
011
100
101
110
111
PWM Delay Value
This field is a programmable delay to control the number of additional system
clock cycles following a PWM or Reload compare before the Timer Output or the
Timer Output Complement is switched to the active state. This field ensures a
time gap between the deassertion of one PWM output to the assertion of its
complement.
No delay
2 cycles delay
4 cycles delay
8 cycles delay
16 cycles delay
32 cycles delay
64 cycles delay
128 cycles delay
0
Input Capture Event
Previous timer interrupt is not a result of a Timer Input Capture Event
1
Previous timer interrupt is a result of a Timer Input Capture Event.
[3–1]
PWMD
[0]
INCAP
Description
Timer 0 Control 1 Register
The Timer 0 Control 1 (T0CTL1) Register, shown in Table 65, enables/disables the timer,
sets the prescaler value, and determines the timer operating mode.
Table 65. Timer 0 Control 1 Register (T0CTL1)
BITS
7
6
FIELD
TEN
TPOL
PRES
TMODE
RESET
0
0
000
000
R/W
R/W
R/W
R/W
R/W
ADDR
PS024604-1005
5
4
3
2
1
0
F07H
PRELIMINARY
Timer 0 Control Registers
Z8 Encore!® Motor Control Flash MCUs
Product Specification
108
Bit
Position
Value
(H)
[7]
TEN
0
Timer Enable
Timer is disabled.
1
Timer enabled.
[6]
TPOL
Description
Timer Input/Output Polarity
This bit is a function of the current operating mode of the timer. It determines the
polarity of the input and/or output signal. When the timer is disabled, the Timer
Output signal is set to the value of this bit.
ONE-SHOT mode–If the timer is enabled the Timer Output signal pulses
(changes state) for one system clock cycle after timer Reload.
CONTINUOUS mode–If the timer is enabled the Timer Output signal is
complemented after timer Reload.
COUNTER mode–If the timer is enabled the Timer Output signal is
complemented after timer reload.
0 = Count occurs on the rising edge of the Timer Input signal.
1 = Count occurs on the falling edge of the Timer Input signal.
PWM SINGLE OUTPUT mode–When enabled, the Timer Output is forced to
TPOL after PWM count match and forced back to TPOL after Reload.
CAPTURE mode–If the timer is enabled the Timer Output signal is
complemented after timer Reload.
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARE mode–The Timer Output signal is complemented after timer
Reload.
GATED mode–The Timer Output signal is complemented after timer Reload.
0 = Timer counts when the Timer Input signal is High and interrupts are
generated on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low and interrupts are
generated on the rising edge of the Timer Input.
CAPTURE/COMPARE mode–If the timer is enabled, the Timer Output signal is
complemented after timer Reload
0 = Counting starts on the first rising edge of the Timer Input signal. The current
count is captured on subsequent rising edges of the Timer Input signal.
1 = Counting starts on the first falling edge of the Timer Input signal. The
current count is captured on subsequent falling edges of the Timer Input signal.
General-Purpose Timer
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
109
Bit
Position
Value
(H)
Description
PWM DUAL OUTPUT mode–If enabled, the Timer Output is set=TPOL after
PWM match and set=TPOL after Reload. If enabled the Timer Output
Complement takes on the opposite value of the Timer Output. The PWMD field
in the T0CTL1 register determines an optional added delay on the assertion
(Low to High) transition of both Timer Output and the Timer Output
Complement for deadband generation.
CAPTURE RESTART mode–If the timer is enabled the Timer Output signal is
complemented after timer Reload.
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARATOR COUNTER mode–If the timer is enabled the Timer Output
signal is complemented after timer Reload.
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
TRIGGERED ONE-SHOT mode–If the timer is enabled the Timer Output signal
is complemented after timer Reload.
0 = The timer triggers on a Low to High transition on the input.
1 = The timer triggers on a High to Low transition on the input.
[5–3]
PRES
000
001
010
011
100
101
110
111
PS024604-1005
The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7.
The prescaler is reset each time the Timer is disabled. This insures proper clock
division each time the Timer is restarted.
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
PRELIMINARY
Timer 0 Control Registers
Z8 Encore!® Motor Control Flash MCUs
Product Specification
110
Bit
Position
Value
(H)
[2–0]
TMODE[2:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
General-Purpose Timer
Description
This field along with the TMODE[3] bit in T0CTL0 register determines the
operating mode of the timer. TMODE[3:0] selects from the following modes:
ONE-SHOT mode
CONTINUOUS mode
COUNTER mode
PWM SINGLE OUTPUT mode
CAPTURE mode
COMPARE mode
GATED mode
CAPTURE/COMPARE mode
PWM DUAL OUTPUT mode
CAPTURE RESTART mode
COMPARATOR COUNTER mode
TRIGGERED ONE-SHOT mode
PRELIMINARY
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Z8FMC16100 Series Flash MCU
Product Specification
111
LIN-UART
The Local Interconnect Network Universal Asynchronous Receiver/Transmitter (LINUART) is a full-duplex communication channel capable of handling asynchronous data
transfers in standard UART applications as well as providing LIN protocol support.
Features of the LIN-UART include:
•
•
•
•
•
•
•
8-bit asynchronous data transfer
•
•
Driver Enable output for external bus transceivers
•
Configurable digital noise filter on Receive Data line.
Selectable even and odd-parity generation and checking
Option of one or two Stop bits
Selectable Multiprocessor (9-bit) mode with three configurable interrupt schemes
Separate transmit and receive interrupts
Framing, parity, overrun and break detection
16-bit Baud Rate Generator (BRG) which may function as a general purpose timer with
interrupt.
LIN protocol support for both master and slave modes
– Break generation and detection
– Selectable Slave Autobaud
– Check Tx vs. Rx data when sending
Architecture
The LIN-UART consists of three primary functional blocks: transmitter, receiver, and
baud rate generator. The LIN-UART’s transmitter and receiver function independently, but
employ the same baud rate and data format. The basic UART operation is enhanced by the
Noise Filter and IrDA blocks. Figure 11 illustrates the LIN-UART architecture.
PS024604-1005
PRELIMINARY
Architecture
Z8 Encore!® Motor Control Flash MCUs
Product Specification
112
Noise Filter
Parity Checker
Rx IRQ
Receiver Control
with Address Compare
Receive Shifter
Receive Data
Register
RxD
Control Registers
IrDA
System Bus
Transmit Data
Register
TxD
Status Registers
Baud Rate
Generator
Transmit Shift
Register
Transmitter Control
Parity Generator
Tx IRQ
CTS
DE
Figure 11. LIN-UART Block Diagram
Data Format for Standard UART Modes
The LIN-UART always transmits and receives data in an 8-bit data format, least-significant bit first. An even or odd parity bit or multiprocessor address/data bit can be optionally
added to the data stream. Each character begins with an active low Start bit and ends with
either 1 or 2 active high Stop bits. Figures 12 and 13 illustrate the asynchronous data format employed by the LIN-UART without parity and with parity, respectively.
LIN-UART
PRELIMINARY
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Z8FMC16100 Series Flash MCU
Product Specification
113
1
Data Field
Idle State
of Line
lsb
Start
Bit 0
msb
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Stop Bit(s)
Bit 7
0
1
2
Figure 12. LIN-UART Asynchronous Data Format without Parity
1
Data Field
Idle State
of Line
lsb
Start
Bit 0
Stop Bit(s)
msb
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Parity
0
1
2
Figure 13. LIN-UART Asynchronous Data Format with Parity
Transmitting Data using the Polled Method
Follow these steps to transmit data using the polled operating method:
1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. If MULTIPROCESSOR mode is appropriate, write to the LIN-UART Control 1 Register to enable MULTIPROCESSOR (9-bit) mode functions.
Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR
mode.
4. Write to the LIN-UART Control 0 Register to:
a. Set the transmit enable bit (TEN) to enable the LIN-UART for data transmission
b. If parity is appropriate and multiprocessor mode is not enabled, set the parity
enable bit (PEN) and select either even or odd parity (PSEL).
c. Set or clear the CTSE bit to enable or disable control from the remote receiver
using the CTS pin.
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5. Check the TDRE bit in the LIN-UART Status 0 register to determine if the Transmit
Data Register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit
Data Register is full (indicated by a 0), continue to monitor the TDRE bit until the
Transmit Data Register becomes available to receive new data.
6. If in MULTIPROCESSOR mode, write the LIN-UART Control 1 Register to select
the outgoing address bit.
Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte; clear it if
sending a data byte.
7. Write the data byte to the LIN-UART Transmit Data Register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data.
8. If appropriate, and if MULTIPROCESSOR mode is enabled, make any changes to the
Multiprocessor Bit Transmitter (MPBT) value.
9. To transmit additional bytes, return to Step 5.
Transmitting Data using the Interrupt-Driven Method
The LIN-UART Transmitter interrupt indicates the availability of the Transmit Data Register to accept new data for transmission. Follow these steps to configure the LIN-UART
for interrupt-driven data transmission:
1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the LIN-UART Transmitter interrupt
and set the appropriate priority.
5. If multiprocessor mode is appropriate, write to the LIN-UART Control 1 Register to
enable Multiprocessor (9-bit) mode functions.
Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR
mode.
6. Write to the LIN-UART Control 0 Register to:
a. Set the transmit enable bit (TEN) to enable the LIN-UART for data transmission
b. If multiprocessor mode is not enabled, enable parity, if appropriate, and select
either even or odd parity.
c. Set or clear the CTSE bit to enable or disable control from the remote receiver via
the CTS pin.
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7. Execute an EI instruction to enable interrupts.
The LIN-UART is now configured for interrupt-driven data transmission. Because the
LIN-UART Transmit Data Register is empty, an interrupt is generated immediately. When
the LIN-UART Transmit interrupt is detected, and there is transmit data ready to send, the
associated interrupt service routine (ISR) performs the following:
1. If in MULTIPROCESSOR mode, write the LIN-UART Control 1 Register to select
the outgoing address bit:
Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if
sending a data byte.
2. Write the data byte to the LIN-UART Transmit Data Register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data.
3. Execute the IRET instruction to return from the interrupt-service routine and wait for
the Transmit Data Register to again become empty.
If a transmit interrupt occurs and there is no transmit data ready to send the interrupt-service routine will execute the IRET instruction. When the application does have data to
transmit, software can set the appropriate interrupt request bit in the Interrupt Controller to
initiate a new transmit interrupt. Another alternative would be for software to write the
data to the Transmit Data Register instead of invoking the interrupt-service routine.
Receiving Data using the Polled Method
Follow these steps to configure the LIN-UART for polled data reception:
1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Write to the LIN-UART Control 1 Register to enable MULTIPROCESSOR mode
functions, if appropriate.
4. Write to the LIN-UART Control 0 Register to:
a. Set the receive enable bit (REN) to enable the LIN-UART for data reception
b. If multiprocessor mode is not enabled, enable parity, if appropriate, and select
either even or odd parity.
5. Check the RDA bit in the LIN-UART Status 0 register to determine if the Receive Data
Register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate
available data, continue to Step 6. If the Receive Data Register is empty (indicated by
a 0), continue to monitor the RDA bit awaiting reception of the valid data.
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6. Read data from the LIN-UART Receive Data Register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may be required depending on the Multiprocessor Mode bits MPMD[1:0].
7. Return to Step 5 to receive additional data.
Receiving Data using the Interrupt-Driven Method
The LIN-UART Receiver interrupt indicates the availability of new data (as well as error
conditions). Follow these steps to configure the LIN-UART receiver for interrupt-driven
operation:
1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the LIN-UART Receiver interrupt and
set the appropriate priority.
5. Clear the LIN-UART Receiver interrupt in the applicable Interrupt Request Register.
6. Write to the LIN-UART Control 1 Register to enable MULTIPROCESSOR (9-bit)
mode functions, if appropriate.
a. Set the MULTIPROCESSOR Mode Select (MPEN) to Enable Multiprocessor
mode.
b. Set the MULTIPROCESSOR Mode Bits, MPMD[1:0], to select the appropriate
address matching scheme.
c. Configure the LIN-UART to interrupt on received data and errors or errors only
(interrupt on errors only is unlikely to be useful for Z8FMC16100 Series Flash
MCU devices without a DMA block),
7. Write the device address to the Address Compare Register (automatic multiprocessor
modes only).
8. Write to the LIN-UART Control 0 Register to:
a. Set the receive enable bit (REN) to enable the LIN-UART for data reception
b. If MULTIPROCESSOR mode is not enabled, enable parity, if appropriate, and
select either even or odd parity.
9. Execute an EI instruction to enable interrupts.
The LIN-UART is now configured for interrupt-driven data reception. When the LINUART Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the following:
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1. Check the LIN-UART Status 0 register to determine the source of the interrupt - error,
break, or received data.
2. If the interrupt was due to data available, read the data from the LIN-UART Receive
Data Register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may
be required depending on the multiprocessor mode bits MPMD[1:0].
3. Execute the IRET instruction to return from the interrupt-service routine and await
more data.
Clear To Send Operation
The Clear To Send (CTS) pin, if enabled by the CTSE bit of the LIN-UART Control 0 Register, performs flow control on the outgoing transmit data stream. The Clear To Send
(CTS) input pin is sampled one system clock before beginning any new character transmission. To delay transmission of the next data character, an external receiver must deassert CTS at least one system clock cycle before a new data transmission begins. For
multiple character transmissions, this operation is typically performed during the Stop Bit
transmission. If CTS deasserts in the middle of a character transmission, the current character is sent completely.
External Driver Enable
The LIN-UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multitransceiver bus, such as RS-485.
Driver Enable is a programmable polarity signal that envelopes the entire transmitted data
frame including parity and Stop bits as illustrated in Figure 14. The Driver Enable signal
asserts when a byte is written to the LIN-UART Transmit Data Register. The Driver
Enable signal asserts at least one bit period and no greater than two bit periods before the
Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver
Enable signal deasserts one system clock period after the last Stop bit is transmitted. This
one system clock delay allows both time for data to clear the transceiver before disabling
it, as well as the ability to determine if another character follows the current character. In
the event of back to back characters (new data must be written to the Transmit Data Register before the previous character is completely transmitted) the DE signal is not deasserted
between characters. The DEPOL bit in the LIN-UART Control Register 1 sets the polarity
of the Driver Enable signal.
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1
DE
0
1
Data Field
Idle State
of Line
lsb
Start
Bit 0
Stop Bit(s)
msb
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Parity
0
1
Figure 14. LIN-UART Driver Enable Signal Timing
(shown with 1 Stop Bit and Parity)
The Driver Enable to START bit set-up time is calculated as follows:
1
Baud Rate (Hz)
ð DE to Start Bit Setup Time(s) ð
2
Baud Rate (Hz)
LIN-UART Special Modes
The special modes of the LIN-UART are:
•
•
Multiprocessor Mode
LIN Mode
The LIN-UART features a common control register (Control 0) that contains a unique register address and several mode-specific control registers (Multiprocessor Control, Noise
Filter Control, and LIN Control) that share a common register address (Control 1). When
the Control 1 address is read or written, the MSEL[2:0] (Mode Select) field of the Mode
Select and Status Register determines which physical register is accessed. Similarly, there
are mode-specific status registers, one of which is returned when the Status 0 Register is
read, depending on the MSEL field.
Multiprocessor Mode
The LIN-UART features a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit
for selective communication when a number of processors share a common UART bus. In
MULTIPROCESSOR mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is
transmitted immediately following the 8-bits of data and immediately preceding the Stop
bit(s) as illustrated in Figure 15. The character format is:
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1
Data Field
Idle State
of Line
lsb
Start
Bit 0
Stop Bit(s)
msb
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MP
0
1
2
Figure 15. LIN-UART Asynchronous Multiprocessor Mode Data Format
In Multiprocessor (9-bit) mode, the Parity bit location (9th bit) becomes the MULTIPROCESSOR control bit. The LIN-UART Control 1 and Status 1 registers provide MULTIPROCESSOR (9-bit) mode control and status information. If an automatic address
matching scheme is enabled, the LIN-UART Address Compare register holds the network
address of the device.
Multiprocessor Mode Receive Interrupts
When MULTIPROCESSOR (9-bit) mode is enabled, the LIN-UART processes only
frames addressed to it. The determination of whether a frame of data is addressed to the
LIN-UART can be made in hardware, software or a combination of the two, depending on
the multiprocessor configuration bits. In general, the address compare feature reduces the
load on the CPU, because it does not need to access the LIN-UART when it receives data
directed to other devices on the multinode network. The following three MULTIPROCESSOR modes are available in hardware:
•
•
•
Interrupt on all address bytes
Interrupt on matched address bytes and correctly framed data bytes
Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0] in the LIN-UART Control 1 Register. For all
multiprocessor modes, bit MPEN of the LIN-UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine checks the address byte that triggered the interrupt. If it matches the LINUART address, the software clears MPMD[0]. At this point, each new incoming byte
interrupts the CPU. The software determines the end of the frame and checks for it by
reading the MPRX bit of the LIN-UART Status 1 Register for each incoming byte. If
MPRX=1, a new frame has begun. If the address of this new frame is different from the
LIN-UART’s address, then MPMD[0] must be set to 1 by software, causing the LINUART interrupts to go inactive until the next address byte. If the new frame’s address
matches the LIN-UART’s, then the data in the new frame is processed as well.
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The second scheme is enabled by setting MPMD[1:0] to 10B and writing the LIN-UART’s
address into the LIN-UART Address Compare Register. This mode introduces more hardware control, interrupting only on frames that match the LIN-UART’s address. When an
incoming address byte does not match the LIN-UART’s address, it is ignored. All successive data bytes in this frame are also ignored. When a matching address byte occurs, an
interrupt is issued and further interrupts occur on each successive data byte. The first data
byte in the frame has NEWFRM=1 in the LIN-UART Status 1 Register. When the next
address byte occurs, the hardware compares it to the LIN-UART’s address. If there is a
match, the interrupt occurs and the NEWFRM bit is set for the first byte of the new frame. If
there is no match, the LIN-UART ignores all incoming bytes until the next address match.
The third scheme is enabled by setting MPMD[1:0] to 11B and by writing the LIN-UART’s
address into the LIN-UART Address Compare Register. This mode is identical to the second scheme, except that there are no interrupts on address bytes. The first data byte of
each frame remains accompanied by a NEWFRM assertion.
LIN Protocol Mode
The LIN (Local Interconnect Network) protocol as supported by the LIN-UART module is
defined in rev 2.0 of the LIN Specification Package. The LIN protocol specification covers all aspects of transferring information between LIN Master and Slave devices using
message frames including error detection and recovery, sleep mode and wake up from
sleep mode. The LIN-UART hardware in LIN mode provides character transfers to support the LIN protocol including BREAK transmission and detection, WAKE-UP transmission and detection, and slave autobauding. Part of the error detection of the LIN protocol
is for both master and slave devices to monitor their receive data when transmitting. If the
receive and transmit data streams do not match, the LIN-UART asserts the PLE bit (physical layer error bit in Status0 register). The message frame time-out aspect of the protocol
is left to software, requiring the use of an additional general purpose timer. The LIN mode
of the LIN-UART does not provide any hardware support for computing/verifying the
checksum field or verifying the contents of the Identifier field. These fields are treated as
data and are not interpreted by hardware. The checksum calculation/verification can easily
be implemented in software via the ADC (Add with Carry) instruction.
The LIN bus contains a single master and one or more slaves. The LIN master is responsible for transmitting the message frame header which consists of the Break, Synch and
Identifier fields. Either the master or one of the slaves transmits the associated response
section of the message which consists of data characters followed by a checksum character.
In LIN mode, the interrupts defined for normal UART operation still apply with the following changes.
•
LIN-UART
Parity Error (PE bit in Status0 register) is redefined as the Physical Layer Error (PLE)
bit. The PLE bit indicates that receive data does not match transmit data when the LINUART is transmitting. This applies to both Master and Slave operating modes.
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•
The Break Detect interrupt (BRKD bit in Status0 register) indicates when a Break is detected by the slave (break condition for at least 11 bit times). Software can use this interrupt to start a timer checking for message frame time-out. The duration of the break
can be read in the RxBreakLength[3:0] field of the Mode Status Register.
•
The Break Detect interrupt (BRKD bit in Status0 register) indicates when a Wake-up
message has been received if the LIN-UART is in LinSleep state.
•
In LIN slave mode, if the BRG counter overflows while measuring the autobaud period
(Start bit to beginning of bit 7 of autobaud character) an Overrun Error is indicated (OE
bit in the Status0 register). In this case, software sets the LinState field back to 10b,
where the Slave ignores the current message and waits for the next Break. The Baud
Reload High and Low registers are not updated by hardware if this autobaud error occurs. The OE bit is also set if a data overrun error occurs.
LIN System Clock Requirements
The LIN master provides the timing reference for the LIN network and is required to have
a clock source with a tolerance of ±0.5%. A slave with autobaud capability is required to
have a baud clock matching the master oscillator within ±14%. The slave nodes autobaud
to lock onto the master timing reference with an accuracy of ±2%. If a Slave does not contain autobaud capability it must include a baud clock which deviates from the masters by
no more than ±1.5%. These accuracy requirements must include affects such as voltage
and temperature drift during operation.
Before sending/receiving messages, the Baud Reload High/Low registers must be initialized. Unlike standard UART modes, the Baud Reload High/Low registers must be loaded
with the baud interval rather than 1/16 of the baud interval.
In order to autobaud with the required accuracy, the LIN slave system clock must be at
least 100 times the baud rate.
LIN Mode Initialization and Operation
The LIN protocol mode is selected by setting either the LMST (LIN Master) or LSLV (LIN
Slave), and optionally (for LIN slave) the ABEN (Autobaud Enable) bits in the LIN Control
Register. To access the LIN Control Register, the MSEL (Mode Select) field of the LINUART Mode Select/Status register must be = 010B. The LIN-UART Control0 register
must be initialized with TEN = 1, REN = 1, all other bits = 0.
In addition to the LMST, LSLV and ABEN bits in the LIN Control Register, a LinState[1:0] field exists that defines the current state of the LIN logic. This field is initially
set by software. In the LIN Slave mode, the LinState field is updated by hardware as the
Slave moves through the Wait For Break, AutoBaud, and Active states.
The Noise Filter may also need to be enabled and configured when interfacing to a LIN
bus.
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LIN MASTER Mode Operation
LIN MASTER mode is selected by setting LMST = 1, LSLV = 0, ABEN = 0, LinState[1:0]
= 11B. If the LIN bus protocol indicates the bus is required go into the LIN sleep state, the
LinState[1:0] bits must be set = 00B by software.
The Break is the first part of the message frame transmitted by the master, consisting of at
least 13 bit periods of logical zero on the LIN bus. During initialization of the LIN master,
the duration (in bit times) of the Break is written to the TxBreakLength field of the LIN
Control Register. The transmission of the Break is performed by setting the SBRK bit in the
Control 0 Register. The LIN-UART starts the Break once the SBRK bit is set and any character transmission currently underway has completed. The SBRK bit is deasserted by hardware once the break is completed.
The Synch character is transmitted by writing a 55H to the Transmit Data Register (TDRE
must = 1 before writing). The Synch character is not transmitted by the hardware until
after the Break is complete.
The Identifier character is transmitted by writing the appropriate value to the Transmit
Data Register (TDRE must = 1 before writing).
If the master is sending the response portion of the message, these data and checksum
characters are written to the Transmit Data Register when the TDRE bit asserts. If the transmit data register is written after TDRE asserts, but before TXE asserts, the hardware inserts
one or two stop bits between each character as determined by the Stop bit in the Control0
register. Additional idle time occurs between characters if TXE asserts before the next
character is written.
If the selected slave is sending the response portion of the frame to the master, each
receive byte will be signalled by the receive data interrupt (RDA bit will be set in the
Status0 register).
If the selected slave is sending the response to a different slave, the master can ignore the
response characters by deasserting the REN bit in the Control0 register until the frame time
slot has completed.
LIN Sleep Mode
While the LIN bus is in the sleep state, the CPU can be in either low power STOP mode, in
HALT mode, or in normal operational state. Any device on the LIN bus may issue a Wakeup message if it requires the master to initiate a LIN message frame. Following the Wakeup message, the master wakes up and initiates a new message. A Wake-up message is
accomplished by pulling the bus low for at least 250 µs but less than 5 ms. Transmitting a
00h character is one way to transmit the wake-up message.
If the CPU is in STOP mode, the LIN-UART is not active and the Wake-up message must
be detected by a GPIO edge detect Stop-Mode Recovery. The duration of the Stop-Mode
Recovery sequence may preclude making an accurate measurement of the Wake-up message duration.
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If the CPU is in HALT or operational mode, the LIN-UART (if enabled) times the duration
of the Wake-up and provides an interrupt following the end of the break sequence if the
duration is ≥ 3 bit times. The total duration of the Wake-up message in bit times may be
obtained by reading the RxBreakLength field in the Mode Status register. After a Wakeup message has been detected, the LIN-UART can be placed (by software) into either LIN
Master or LIN Slave Wait for Break states as appropriate. If the break duration exceeds 15
bit times, the RxBreakLength field contains the value Fh. If the LIN-UART is disabled,
the Wake-up message can be detected via a port pin interrupt and timed by software. If the
device is in STOP mode, the high to low transition on the port pin will bring the device out
of STOP mode.
The LIN Sleep state is selected by software setting LinState[1:0] = 00. The decision to
move from an active state to sleep state is based on the LIN messages as interpreted by
software.
LIN Slave Operation
LIN Slave mode is selected by setting LMST = 0, LSLV = 1, ABEN = 1 or 0 and LinState[1:0] = 01b (Wait for Break State). The LIN slave detects the start of a new message by the Break which appears to the Slave as a break of at least 11 bit times in duration.
The LIN-UART detects the Break and generates an interrupt to the CPU. The duration of
the Break is observable in the RxBreakLength field of the Mode Status register. A Break
of less than 11 bit times in duration does not generate a break interrupt when the LINUART is in Wait for Break state. If the Break duration exceeds 15 bit times, the RxBreakLength field contains the value Fh.
Following the Break the LIN-UART hardware automatically transitions to the Autobaud
state, where it autobauds by timing the duration of the first 8 bit times of the Synch character as defined in the standard. At the end of the autobaud period, the duration measured by
the BRG counter (auto baud period divided by 8) is automatically transferred to the Baud
Reload High and Low registers if the ABEN bit of the LIN control register is set. If the
BRG Counter overflows before reaching the start of bit 7 in the autobaud sequence the
Autobaud Overrun Error interrupt occurs, the OE bit in the Status0 register is set and the
Baud Reload registers are not updated. To autobaud within 2% of the master’s baud rate,
the slave system clock must be a minimum of 100 times the baud rate. To avoid an autobaud overrun error, the system clock must not be greater than 219 times the baud rate (16
bit counter following 3-bit prescaler when counting the 8 bit times of the Autobaud
sequence).
Following the Synch character, the LIN-UART hardware transitions to the Active state
where the Identifier character is received and the characters of the Response section of the
message are sent or received. The Slave remains in the Active state until a Break is
received or software forces a state change. Once in Active State (autobaud has completed),
a Break of 10 or more bit times is recognized and will cause a transition to the Autobaud
state.
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If the Identifier character indicates that this slave device is not participating in the message, software can set the LinState[1:0] = 01b (Wait for Break State) to ignore the rest
of the message. No further receive interrupts will occur until the next Break.
LIN-UART Interrupts
The LIN-UART features separate interrupts for the transmitter and receiver. In addition,
when the LIN-UART primary functionality is disabled, the Baud Rate Generator can also
function as a basic timer with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for transmission. The TDRE interrupt occurs when the transmitter is initially enabled and after the
Transmit shift register has shifted the first bit of a character out. At this point, the Transmit
Data Register may be written with the next character to send. This provides 7 bit periods
of latency to load the Transmit Data Register before the Transmit shift register completes
shifting the current character. Writing to the LIN-UART Transmit Data Register clears the
TDRE bit to 0.
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
A data byte has been received and is available in the LIN-UART Receive Data Register. This interrupt can be disabled independent of the other receiver interrupt sources
via the RDAIRQ bit (this feature is useful in devices which support DMA). The received
data interrupt occurs once the receive character has been placed in the Receive Data
Register. Software must respond to this received data available condition before the
next character is completely received to avoid an overrun error.
Note: In MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on
the multiprocessor configuration and the most recent address byte
•
•
•
•
A break is received
A receive data overrun or LIN slave autobaud overrun error is detected.
A data framing error is detected
A parity error is detected (physical layer error in LIN mode)
LIN-UART Overrun Errors
When an overrun error condition occurs the LIN-UART prevents overwriting of the valid
data currently in the Receive Data Register. The Break Detect and Overrun status bits are
not displayed until after the valid data has been read.
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After the valid data has been read, the OE bit of the Status 0 register is updated to indicate
the overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate
that the Receive Data Register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and must be ignored. The BRKD bit indicates
if the overrun was caused by a break condition on the line. After reading the status byte
indicating an overrun error, the Receive Data Register must be read again to clear the error
bits in the LIN-UART Status 0 register.
In LIN mode, an Overrun Error is signaled for receive data overruns as described above
and in the LIN Slave if the BRG Counter overflows during the autobaud sequence (the
ATB bit will also be set in this case). There is no data associated with the autobaud overflow interrupt, however the Receive Data Register must be read to clear the OE bit. In this
case software must write a 10B to the LinState field, forcing the LIN slave back to a
Wait for Break state.
LIN-UART Data- and Error-Handling Procedure
Figure 16 illustrates the recommended procedure for use in LIN-UART receiver interrupt
service routines.
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Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read data that clears
the RDA bit and
resets the error bits
Read data
Discard data
Figure 16. LIN-UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts
If the BRGCTL bit of the Multiprocessor Control Register (LIN-UART Control 1 Register
with MSEL = 000b) register is set, and the REN bit of the Control 0 Register is 0, the LINUART Receiver interrupt asserts when the LIN-UART Baud Rate Generator reloads. This
action allows the Baud Rate Generator to function as an additional counter if the LINUART receiver functionality is not employed.
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The transmitter can be enabled in this mode.
LIN-UART Baud Rate Generator
The LIN-UART Baud Rate Generator creates a lower frequency baud rate clock for data
transmission. The input to the Baud Rate Generator is the system clock. The LIN-UART
Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value
(BRG[15:0]) that sets the data transmission rate (baud rate) of the LIN-UART. The LINUART data rate is calculated using the following equation for normal UART operation:
UART Data Rate (bits/s) =
System Clock Frequency (Hz)
16 x UART Baud Rate Divisor Value
The LIN-UART data rate is calculated using the following equation for LIN mode UART
operation:
UART Data Rate (bits/s) =
System Clock Frequency (Hz)
UART Baud Rate Divisor Value
When the LIN-UART is disabled, the Baud Rate Generator can function as a basic 16-bit
timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with
interrupt on time-out, complete the following procedure:
1. Disable the LIN-UART receiver by clearing the REN bit in the LIN-UART Control 0
Register to 0 (TEN bit may be asserted, transmit activity may occur).
2. Load the appropriate 16-bit count value into the LIN-UART Baud Rate High and Low
Byte registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTL bit in the LIN-UART Control 1 Register to 1.
Noise Filter
A noise filter circuit is included which filters noise on a digital input signal (such as UART
Receive Data) before the data is sampled by the block. This is likely to be a requirement
for protocols with a noisy environment.
The noise filter contains the following features:
•
•
PS024604-1005
Synchronizes the receive input data to the System Clock
Noise Filter Enable (NFEN) input selects whether the noise filter is bypassed (NFEN =
0) or included (NFEN = 1) in the receive data path.
PRELIMINARY
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Z8 Encore!® Motor Control Flash MCUs
Product Specification
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•
Noise Filter Control (NFCTL[2:0]) input selects the width of the up/down saturating
counter digital filter. The available widths range from 4 bits to 11 bits.
•
•
The digital filter output features hysteresis
Provides an active low Saturated State output (FiltSatB) which is used as an indication of the presence of noise.
Architecture
Figure 17 illustrates how the noise filter is integrated with the LIN-UART for use on a
LIN network.
System
Clock
RxD
RxD
FiltSatB
NFEN, NFCTL
Noise
Filter
LIN-UART
LIN
Transceiver
GPIO
TxD
TxD
LIN Bus
RxD
TxD
Figure 17. Noise Filter System Block Diagram
Operation
The figure below illustrates the operation of the noise filter both with and without noise.
The noise filter in this example is a 2-bit up/down counter which saturates at 00b and
11b. A 2-bit counter is shown for convenience, the operation of wider counters is similar.
The output of the filter switches from 1 to 0 when the counter counts down from 01b to
00b and switches from 0 to 1 when the counter counts up from 10b to 11b. The noise
filter delays the receive data by three System Clock cycles.
The FiltSatB signal is checked when the filtered RxD is sampled in the center of the bit
time. The presence of noise (FiltSatB = 1 at center of bit time) does not mean the sampled data is incorrect, just that the filter is not in its "saturated" state of all 1’s or all 0’s. If
FiltSatB = 1 when RxD is sampled during a receive character, the NE bit in the ModeStatus[4:0] field is set. By observing this bit, an indication of the level of noise in the network can be obtained.
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Baud Period
System
Clock
Input
RxD (ideal)
Noise Filter
Up/Dn Counter
Data Bit = 1
Data Bit = 0
3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Noise Filter
Output RxD
Clean RxD
Example
Nominal filter delay
Input
RxD (noisy)
Data Bit = 0
Noise Filter
Up/Dn Counter
3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Data Bit = 1
0 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Noise RxD
Example
Noise Filter
Output RxD
FiltSatB
Output
UART
Sample Point
Figure 18. Noise Filter Operation
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LIN-UART Control Register Definitions
The LIN-UART control registers support the LIN-UART, the associated Infrared Encoder/
Decoder and the noise filter. For more information on the infrared operation, refer to the
Infrared Encoder/Decoder chapter on page 145.
LIN-UART Transmit Data Register
Data bytes written to the LIN-UART Transmit Data Register, shown in Table 66, are
shifted out on the TxD pin. The Write-only LIN-UART Transmit Data Register shares a
Register File address with the read-only LIN-UART Receive Data Register.
Table 66. LIN-UART Transmit Data Register (U0TXD)
BITS
7
6
5
4
3
FIELD
TXD
RESET
X
R/W
W
ADDR
F40H
2
1
0
TXD—Transmit Data
LIN-UART transmitter data byte to be shifted out through the TXD pin.
LIN-UART Receive Data Register
Data bytes received through the RxD pin are stored in the LIN-UART Receive Data Register, shown in Table 67. The read-only LIN-UART Receive Data Register shares a Register File address with the Write-only LIN-UART Transmit Data Register.
Table 67. LIN-UART Receive Data Register (U0RXD)
BITS
7
6
5
4
3
FIELD
RXD
RESET
X
R/W
R
ADDR
F40H
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RXD—Receive Data
LIN-UART receiver data byte from the RXD pin
LIN-UART Status 0 Register
The LIN-UART Status 0 Register identifies the current LIN-UART operating configuration and status. Table 68 describes the Status 0 Register for standard UART mode. Table
69, which follows on page 132, describes the Status0 Register for LIN mode. A more
detailed discussion of each bit follows each table.
Table 68. LIN-UART Status 0 Register - standard UART mode (U0STAT0)
BITS
7
6
5
4
3
2
1
0
FIELD
RDA
PE
OE
FE
BRKD
TDRE
TXE
CTS
RESET
0
0
0
0
0
1
1
X
R/W
R
R
R
R
R
R
R
R
F41H
ADDR
Receive Data Available (RDA). This bit indicates that the LIN-UART Receive Data Reg-
ister has received data. Reading the LIN-UART Receive Data Register clears this bit.
Parity Error (PE). This bit indicates that a parity error has occurred. Reading the Receive
Data Register clears this bit.
Overrun Error (OE). This bit indicates that an overrun error has occurred. An overrun
occurs when new data is received and the Receive Data Register has not been read. Reading the Receive Data Register clears this bit.
Framing Error (FE). This bit indicates that a framing error (no STOP bit following data
reception) was detected. Reading the Receive Data Register clears this bit.
Break Detect (BRKD). This bit indicates that a break occurred. If the data bits, parity/
multiprocessor bit, and STOP bit(s) are all zeros then this bit is set to 1. Reading the
Receive Data Register clears this bit.
Transmitter Data Register Empty (TDRE). This bit indicates that the Transmit Data
Register is empty and ready for additional data. Writing to the Transmit Data Register
resets this bit.
Transmitter Empty (TXE). This bit indicates that the transmit shift register is empty and
character transmission is finished.
Clear To Send Signal (CTS). When this bit is read it returns the level of the CTS signal.
If LBEN = 1, the CTS input signal is replaced by the internal Receive Data Available sig-
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Z8 Encore!® Motor Control Flash MCUs
Product Specification
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nal to provide flow control in loopback mode. CTS only affects transmission if the CTSE
bit = 1.
Table 69. LIN-UART Status 0 Register - LIN mode (U0STAT0)
BITS
7
6
5
4
3
2
1
0
FIELD
RDA
PLE
ABOE
FE
BRKD
TDRE
TXE
ATB
RESET
0
0
0
0
0
1
1
0
R/W
R
R
R
R
R
R
R
R
F41H
ADDR
Receive Data Available (RDA). This bit indicates that the Receive Data Register has
received data. Reading the Receive Data Register clears this bit.
Physical Layer Error (PLE). This bit indicates that transmit and receive data do not
match when a LIN slave or master is transmitting. This could be caused by a fault in the
physical layer or multiple devices driving the bus simultaneously. Reading the Status 0
Register or the Receive Data Register clears this bit.
Receive Data and Autobaud Overrun Error (OE). This bit is set just as in normal UART
operation if a receive data overrun error occurs. This bit is also set during LIN Slave autobaud if the BRG counter overflows before the end of the autobaud sequence, indicating
the receive activity was not an autobaud character or the master baud rate is too slow. The
ATB status bit will also be set in this case. This bit is cleared by reading the Receive Data
Register.
Framing Error (FE). This bit indicates that a framing error (no STOP bit following data
reception) was detected. Reading the Receive Data Register clears this bit.
Break Detect (BRKD). This bit is set in LIN mode if (a) in LinSleep state and a break of at
least 4 bit times occurred (Wake-up event) or (b) in Slave Wait Break state and a break of
at least 11 bit times occurred (Break event) or (c) in Slave Active state and a break of at
least 10 bit times occurs. Reading the Status 0 Register or the Receive Data Register clears
this bit.
Transmitter Data Register Empty (TDRE). This bit indicates that the Transmit Data
Register is empty and ready for additional data. Writing to the Transmit Data Register
resets this bit.
Transmitter Empty (TXE). This bit indicates that the transmit shift register is empty and
character transmission is finished.
LIN Slave Autobaud Complete (ATB). This bit is set in LIN SLAVE mode when an autobaud character is received. If the ABIEN bit is set in the LIN Control Register, then a
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133
receive interrupt is generated when this bit is set. Reading the Status 0 Register clears this
bit. This bit will be 0 in LIN MASTER mode.
LIN-UART Mode Select and Status Register
The LIN-UART Mode Select and Status Register, shown in Table 70, contains mode select
and status bits. A more detailed discussion of each bit follows the table.
Table 70. LIN-UART Mode Select and Status Register (U0MDSTAT)
7
BITS
6
5
4
3
MSEL
FIELD
2
1
0
Mode Status
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
R
F44H
ADDR
MSEL—Mode Select.
This R/W field determines which control register is accessed when performing a write or
read to the Uart Control 1 Register address. This field also determines which status is
returned in the ModeStatus field when reading this register.
000 = Multiprocessor and normal UART control/status
001 = Noise Filter control/status
010 = LIN Protocol control/status
011–110: reserved
111 = LIN-UART Hardware Revision (allows hardware revision to be read in the Mode
Status field)
Mode Status. This read-only field returns status corresponding to the mode selected by
MSEL as follows
000 : Multiprocessor and normal UART mode status = {NE, 0, 0, NEWFRM, MPRX}
001 : Noise Filter status = {NE, 0,0,0,0}
010 : LIN mode status = {NE, RxBreakLength[3:0]}
011–110 : reserved = {0, 0, 0, 0, 0}
111 : LIN-UART hardware revision
MULTIPROCESSOR Mode Status field (MSEL = 000B)
NE—Noise Event. This bit is asserted if digital noise is detected on the receive data line
while the data is sampled (center of bit time). If this bit is set, it does not mean that the
receive data is corrupted (though it may be in extreme cases), just that one or more of the
noise filter data samples near the center of the bit time did not match the average data
value.
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LIN-UART Mode Select and Status Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
134
NEWFRM—Status bit denoting the start of a new frame. Reading the LIN-UART Receive
Data register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
MPRX—Multiprocessor Receive
Returns the value of the last multiprocessor bit received. Reading from the LIN-UART
Receive Data register resets this bit to 0.
Digital Noise Filter Mode Status Field (MSEL = 001B)
NE—Noise Event. This bit is asserted if digital noise is detected on the receive data line
while the data is sampled (center of bit time). If this bit is set, it does not mean that the
receive data is corrupted (though it may be in extreme cases), just that one or more of the
noise filter data samples near the center of the bit time did not match the average data
value.
LIN Mode Status Field (MSEL = 010B)
NE—Noise Event. This bit is asserted if some noise level is detected on the receive data
line while the data is sampled (center of bit time). If this bit is set, it does not indicate that
the receive data is corrupt (though it may be in extreme cases), just that one or more of the
16x data samples near the center of the bit time did not match the average data value.
RxBreakLength—LIN mode received break length. This field may be read following a
break (LIN WAKE-UP or BREAK) so software can determine the measured duration of
the break. If the break exceeds 15 bit times the value saturates at 1111B.
Hardware Revision Mode Status Field (MSEL = 111B)
This field indicates the hardware revision of the LIN-UART block.
00_xxx LIN UART hardware rev
01_xxx reserved
10_xxx reserved
11_xxx reserved
LIN-UART Control 0 Register
The LIN-UART Control 0 Register, shown in Table 71, configures the basic properties of
the LIN-UART’s transmit and receive operations. A more detailed discussion of each bit
follows the table.
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Table 71. LIN-UART Control 0 Register (U0CTL0)
BITS
7
6
5
4
3
2
1
0
FIELD
TEN
REN
CTSE
PEN
PSEL
SBRK
STOP
LBEN
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
F42H
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is Low and the CTSE bit is 1, the transmitter is
enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The LIN-UART recognizes the CTS signal as an enable control for the transmitter.
PEN—Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit.
0 = Parity is disabled. This bit is overridden by the MPEN bit.
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit.
PSEL—Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
SBRK—Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit. In
standard UART mode, the duration of the break is determined by how long software
leaves this bit asserted. Also the duration of any required Stop bits following the break
must be timed by software before writing a new byte to be transmitted to the transmit data
register. In LIN mode, the master sends a Break character by asserting SBRK. The duration
of the break is timed by hardware, and the SBRK bit is deasserted by hardware when the
Break is completed. The duration of the Break is determined by the TxBreakLength field
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Product Specification
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of the LIN Control register. One or two stop bits are automatically provided by the hardware in LIN mode as defined by the STOP bit.
0 = No break is sent.
1 = The output of the transmitter is 0.
STOP—Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver within the IrDA module.
LIN-UART Control 1 Registers
Multiple registers, shown in Tables 72 through 74) are accessible by a single bus address.
The register selected is determined by the Mode Select (MSEL) field. These registers provide additional control over LIN-UART operation.
Multiprocessor Control Register
When MSEL = 000b, the Multiprocessor Control Register, shown in Table 72, provides
control for UART multiprocessor mode, IRDA mode, baud rate timer mode as well as other
features that may apply to multiple modes. A more detailed discussion of each bit follows
the table.
Table 72. MultiProcessor Control Register (U0CTL1 with MSEL = 000b)
BITS
7
6
5
4
3
2
1
0
FIELD
MPMD[1]
MPEN
MPMD[0]
MPBT
DEPOL
BRGCTL
RDAIRQ
IREN
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
F43H with MSEL = 000b
MPMD[1:0]—Multiprocessor Mode
If MULTIPROCESSOR (9-bit) mode is enabled,
00 = The LIN-UART generates an interrupt request on all received bytes (data and
address).
01 = The LIN-UART generates an interrupt request only on received address bytes.
10 = The LIN-UART generates an interrupt request when a received address byte matches
the value stored in the Address Compare Register and on all successive data bytes until an
address mismatch occurs.
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11 = The LIN-UART generates an interrupt request on all received data bytes for which
the most recent address byte matched the value in the Address Compare Register.
MPEN—MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-bit) mode.
0 = Disable Multiprocessor (9-bit) mode.
1 = Enable Multiprocessor (9-bit) mode.
MPBT—Multiprocessor Bit Transmit
This bit is applicable only when Multiprocessor (9-bit) mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
DEPOL—Driver Enable Polarity
0 = DE signal is Active High.
1 = DE signal is Active Low.
BRGCTL—Baud Rate Generator Control
This bit causes different LIN-UART behavior depending on whether the LIN-UART
receiver is enabled (REN = 1 in the LIN-UART Control 0 Register).
When the LIN-UART receiver is not enabled, this bit determines whether the Baud Rate
Generator issues interrupts.
0 = BRG is disabled. Reads from the Baud Rate High and Low Byte registers return the
BRG Reload Value
1 = BRG is enabled and counting. The Baud Rate Generator generates a receive interrupt
when it counts down to 0. Reads from the Baud Rate High and Low Byte registers return
the current BRG count value.
When the LIN-UART receiver is enabled, this bit allows reads from the Baud Rate Registers to return the BRG count value instead of the Reload Value.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count
value. Unlike the Timers, there is no mechanism to latch the High Byte when the Low
Byte is read.
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the Interrupt Controller.
1 = Received data does not generate an interrupt request to the Interrupt Controller. Only
receiver errors generate an interrupt request.
IREN—Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. LIN-UART operates normally.
1 = Infrared Encoder/Decoder is enabled. The LIN-UART transmits and receives data
through the Infrared Encoder/Decoder.
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LIN-UART Control 1 Registers
Z8 Encore!® Motor Control Flash MCUs
Product Specification
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Noise Filter Control Register
When MSEL = 001b, the Noise Filter Control Register, shown in Table , provides control
for the digital noise filter. A more detailed discussion of each bit follows the table.
Table 73. Noise Filter Control Register (U0CTL1 with MSEL = 001b)
BITS
7
6
5
4
3
FIELD
NFEN
RESET
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
2
1
0
0
0
0
R
R
R
NFCTL
Reserved
F43H with MSEL = 001b
ADDR
NFEN—Noise Filter Enable
0 = Noise filter is disabled.
1 = Noise filter is enabled. Receive data is preprocessed by the noise filter.
NFCTL—Noise Filter Control
This field controls the delay and noise rejection characteristics of the noise filter. The
wider the counter the more delay that is introduced by the filter and the wider the noise
event that is filtered.
000 = 4-bit up/down counter
001 = 5-bit up/down counter
010 = 6-bit up/down counter
011 = 7-bit up/down counter
100 = 8-bit up/down counter
101 = 9-bit up/down counter
110 = 10-bit up/down counter
111 = 11-bit up/down counter
LIN Control Register
When MSEL = 010b, the LIN Control Register provides control for the LIN mode of operation. A more detailed discussion of each bit follows the table.
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139
Table 74. LIN Control Register (U0CTL1 with MSEL = 010b)
BITS
7
6
5
4
FIELD
LMST
LSLV
ABEN
ABIEN
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
3
2
LinState[1:0]
1
0
TxBreakLength
F43H with MSEL = 010b
LMST—LIN Master Mode
0 = LIN Master Mode not selected
1 = LIN Master Mode selected (if MPEN, PEN, LSLV = 0)
LSLV—LIN Slave Mode
0 = LIN Slave Mode not selected
1 = LIN Slave Mode selected (if MPEN, PEN, LMST = 0)
ABEN—Autobaud Enable
0 = Autobaud not enabled
1 = Autobaud enabled if in LIN Slave mode.
ABIEN—Autobaud Interrupt Enable
0 = Interrupt following Autobaud does not occur
1 = Interrupt WILL follow Autobaud if in LIN Slave mode and ABEN = 1. When the Autobaud character is received, a receive interrupt is generated and the ATB bit is set in the
Status0 register. There is no receive data associated with this interrupt. The Baud Reload
registers will be updated by hardware with the new bit period value.
LinState[1:0]—LIN State Machine
The LinState is controlled by both hardware and software. Software can force a state
change at any time if necessary. In normal operation, software moves the state in and out
of Sleep state. For a LIN Slave, software changes the state from Sleep to Wait for Break
after which hardware cycles through the Wait for Break, Autobaud and Active states. Software changes the state from one of the active states to Sleep state if the LIN bus goes into
Sleep mode. For a LIN Master, software changes the state from Sleep to Active where it
remains until software sets it back to the Sleep state. After configuration software does not
alter the LinState field during operation.
00 = Sleep State (either LMST or LSLV may be set)
01 = Wait for Break state (only valid for LSLV = 1)
10 = Autobaud state (only valid for LSLV = 1)
11 = Active state (either LMST or LSLV may be set)
TxBreakLength —Used in LIN mode by the master to control the duration of the transmitted Break.
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00 = 13 bit times
01 = 14 bit times
10 = 15 bit times
11 = 16 bit times
LIN-UART Address Compare Register
The LIN-UART Address Compare Register stores the multinode network address of the
LIN-UART. When the MPMD[1] bit of the LIN-UART Control Register 0 is set, all incoming address bytes are compared to the value stored in this Address Compare Register.
Receive interrupts and RDA assertions only occur in the event of a match. See Table 75.
Table 75. LIN-UART Address Compare Register (U0ADDR)
BITS
7
6
5
4
3
FIELD
COMP_ADDR
RESET
00H
R/W
R/W
ADDR
F45H
2
1
0
COMP_ADDR—Compare Address
This 8-bit value is compared to the incoming address bytes.
LIN-UART Baud Rate High and Low Byte Registers
The LIN-UART Baud Rate High and Low Byte registers, shown in Tables 76 and 77)
combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud rate) of the LIN-UART.
Table 76. LIN-UART Baud Rate High Byte Register (U0BRH)
BITS
7
6
5
4
3
FIELD
BRH
RESET
FFH
R/W
R/W
ADDR
F46H
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PRELIMINARY
2
1
0
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Table 77. LIN-UART Baud Rate Low Byte Register (U0BRL)
7
BITS
6
5
4
3
FIELD
BRL
RESET
FFH
R/W
R/W
ADDR
F47H
2
1
0
The LIN-UART data rate is calculated using the following equation for standard UART
modes. For LIN protocol, the Baud Rate registers must be programmed with the baud
period rather than 1/16 baud period.
Note: The UART must be disabled when updating the Baud Rate registers because the high and
low registers must be written independently.
The LIN-UART data rate is calculated using the following equation for standard UART
operation:
UART Data Rate (bits per second) =
System Clock Frequency (Hz)
16 x UART Baud Rate Divisor Value
The LIN-UART data rate is calculated using the following equation for LIN mode UART
operation:
UART Data Rate (bits per second) =
System Clock Frequency (Hz)
UART Baud Rate Divisor Value
For a given LIN-UART data rate, the integer baud rate divisor value is calculated using the
following equation for standard UART operation:
System Clock Frequency (Hz)
UART Baud Rate Divisor Value (BRG) = Round  -------------------------------------------------------------------------------
 16 x UART Data Rate (bits/s) 
For a given LIN-UART data rate, the integer baud rate divisor value is calculated using the
following equation for LIN mode UART operation:
System Clock Frequency (Hz)
UART Baud Rate Divisor Value (BRG) = Round  -------------------------------------------------------------------------------
 UART Data Rate (bits/s) 
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Z8 Encore!® Motor Control Flash MCUs
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The baud rate error relative to the appropriate baud rate is calculated using the following
equation:
Actual Data Rate – Desired Data Rate
UART Baud Rate Error (%) = 100 ×  ----------------------------------------------------------------------------------------------------


Desired Data Rate
For reliable communication, the LIN-UART baud rate error must never exceed 5 percent.
Tables 78 through 82 provide error data for popular baud rates and commonly-used crystal
oscillator frequencies for normal UART modes of operation.
Table 78. LIN-UART Baud Rates, 20.0 MHz System Clock
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
1250.0
1
1250.0
0.00
9.60
130
9.62
0.16
625.0
2
625.0
0.00
4.80
260
4.81
0.16
250.0
5
250.0
0.00
2.40
521
2.399
–0.03
115.2
11
113.64
–1.19
1.20
1042
1.199
–0.03
57.6
22
56.82
–1.36
0.60
2083
0.60
0.02
38.4
33
37.88
–1.36
0.30
4167
0.299
–0.01
19.2
65
19.23
0.16
Actual Rate Error(
(kHz)
%)
Actual Rate Error(
(kHz)
%)
Table 79. LIN-UART Baud Rates, 10.0 MHz System Clock
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
1250.0
N/A
N/A
N/A
9.60
65
9.62
0.16
625.0
1
625.0
0.00
4.80
130
4.81
0.16
250.0
3
208.33
–16.67
2.40
260
2.40
–0.03
115.2
5
125.0
8.51
1.20
521
1.20
–0.03
57.6
11
56.8
–1.36
0.60
1042
0.60
–0.03
38.4
16
39.1
1.73
0.30
2083
0.30
0.2
19.2
33
18.9
0.16
LIN-UART
Actual Rate Error(
(kHz)
%)
PRELIMINARY
Actual Rate Error(
(kHz)
%)
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
143
Table 80. LIN-UART Baud Rates, 5.5296 MHz System Clock
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
1250.0
N/A
N/A
N/A
9.60
36
9.60
0.00
625.0
N/A
N/A
N/A
4.80
72
4.80
0.00
250.0
1
345.6
38.24
2.40
144
2.40
0.00
115.2
3
115.2
0.00
1.20
288
1.20
0.00
57.6
6
57.6
0.00
0.60
576
0.60
0.00
38.4
9
38.4
0.00
0.30
1152
0.30
0.00
19.2
18
19.2
0.00
Actual Rate Error(
(kHz)
%)
Actual Rate Error(
(kHz)
%)
Table 81. LIN-UART Baud Rates, 3.579545 MHz System Clock
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
N/A
9.60
23
9.73
1.32
N/A
N/A
4.80
47
4.76
–0.83
1
223.72
–10.51
2.40
93
2.41
0.23
115.2
2
111.9
–2.90
1.20
186
1.20
0.23
57.6
4
55.9
–2.90
0.60
373
0.60
–0.04
38.4
6
37.3
–2.90
0.30
746
0.30
–0.04
19.2
12
18.6
–2.90
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
1250.0
N/A
N/A
625.0
N/A
250.0
Actual Rate Error(
(kHz)
%)
Actual Rate Error(
(kHz)
%)
Table 82. LIN-UART Baud Rates, 1.8432 MHz System Clock
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
1250.0
N/A
N/A
625.0
N/A
250.0
115.2
PS024604-1005
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
N/A
9.60
12
9.60
0.00
N/A
N/A
4.80
24
4.80
0.00
N/A
N/A
N/A
2.40
48
2.40
0.00
1
115.2
0.00
1.20
96
1.20
0.00
Actual Rate Error(
(kHz)
%)
PRELIMINARY
Actual Rate Error(
(kHz)
%)
LIN-UART Baud Rate High and Low Byte
Z8 Encore!® Motor Control Flash MCUs
Product Specification
144
Table 82. LIN-UART Baud Rates, 1.8432 MHz System Clock (Continued)
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
57.6
2
57.6
38.4
3
19.2
6
LIN-UART
Applicable
Rate (kHz)
BRG
Divisor
(Decimal)
0.00
0.60
192
0.60
0.00
38.4
0.00
0.30
384
0.30
0.00
19.2
0.00
Actual Rate Error(
(kHz)
%)
PRELIMINARY
Actual Rate Error(
(kHz)
%)
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
145
Infrared Encoder/Decoder
The Z8FMC16100 Series Flash MCU contains two fully-functional, high-performance
UART to Infrared Encoder/Decoders (endecs). Each infrared endec is integrated with an
on-chip UART to allow easy communication between the Z8FMC16100 Series Flash
MCU and IrDA Physical Layer Specification, Version 1.3-compliant infrared transceivers.
Infrared communication provides secure, reliable, low-cost, point-to-point communication
between PCs, PDAs, cell phones, printers and other infrared enabled devices.
Architecture
Figure 19 illustrates the architecture of the infrared endec.
System
Clock
RxD
TxD
UART
Baud Rate
Clock
RxD
Infrared
Encoder/Decoder
(endec)
TxD
ZiLOG
ZHX1810
RxD
TxD
Infrared
Transceiver
Interrupt
I/O
Signal Address
Data
Figure 19. Infrared Data Communication System Block Diagram
Operation
When the infrared endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the infrared transceiver using the TXD pin. Likewise, data received from the infrared transceiver is
passed to the infrared endec using the RXD pin, decoded by the infrared endec, and passed
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Architecture
Z8 Encore!® Motor Control Flash MCUs
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to the UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed.
The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud
rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet
IrDA specifications. The UART must be enabled to use the infrared endec. The infrared
endec data rate is calculated using the following equation:
Infrared Data Rate (bits/s) =
System Clock Frequency (Hz)
16 x UART Baud Rate Divisor Value
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The
UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the
modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared
data bit is 16-clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains
Low for the full 16-clock period. If the data to be transmitted is 0, a 3-clock high pulse is
output following a 7-clock low period. After the 3-clock high pulse, a 6-clock low pulse is
output to complete the full 16-clock data period. Figure 20 illustrates IrDA data transmission. When the infrared endec is enabled, the UART’s TXD signal is internal to the
Z8FMC16100 Series Flash MCU while the IR_TXD signal is output through the TXD pin.
16-Clock
Period
Baud Rate
Clock
UART’s
TxD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
3-Clock
Pulse
IR_TxD
7-Clock
Delay
Figure 20. Infrared Data Transmission
Infrared Encoder/Decoder
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
147
Receiving IrDA Data
Data received from the infrared transceiver via the IR_RXD signal through the RXD pin is
decoded by the infrared endec and passed to the UART. The UART’s baud rate clock is
used by the infrared endec to generate the demodulated signal (RXD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 21 illustrates data reception. When the infrared endec is enabled, the UART’s RXD signal is internal to the
Z8FMC16100 Series Flash MCU while the IR_RXD signal is received through the RXD
pin.
16-Clock
Period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RxD
Min. 1.6 s
Pulse
UART’s
RxD
8-Clock
Delay
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
16-Clock
Period
16-Clock
Period
16-Clock
Period
Data Bit 2 = 1
Data Bit 3 = 1
16-Clock
Period
Figure 21. Infrared Data Reception
Caution: The system clock frequency must be at least 1.0 MHz to ensure proper reception of the
1.6 µs minimum-width pulses allowed by the IrDA standard.
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
The window remains open until the count again reaches 8 (or in other words 24 baud clock
periods since the previous pulse was detected) giving the endec a sampling window of
minus four baud rate clocks to plus eight baud rate clocks around the expected time of an
PS024604-1005
PRELIMINARY
Receiving IrDA Data
Z8 Encore!® Motor Control Flash MCUs
Product Specification
148
incoming pulse. If an incoming pulse is detected inside this window this process is
repeated. If the incoming data is a logical 1 (no pulse), the endec returns to the initial state
and waits for the next falling edge. As each falling edge is detected, the endec clock
counter is reset, resynchronizing the endec to the incoming signal. This allows the endec
to tolerate jitter and baud rate errors in the incoming data stream. Resynchronizing the
endec does not alter the operation of the UART, which ultimately receives the data. The
UART is only synchronized to the incoming data stream when a Start bit is received.
Infrared Encoder/Decoder Control Register Definitions
All infrared endec configuration and status information is set by the UART control registers as defined in LIN-UART Control Register Definitions section on page 130.
Caution: To prevent spurious signals during IrDA data transmission, set the IREN bit in the UARTx Control 1 Register to 1 to enable the Infrared Encoder/Decoder before enabling the
GPIO Port alternate function for the corresponding pin.
Infrared Encoder/Decoder
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
149
Serial Peripheral Interface
The Serial Peripheral Interface (SPI) is a synchronous interface allowing several SPI-type
devices, such as EEPROMs, to be interconnected. SPI features include:
•
•
•
•
•
Full-duplex, synchronous, character-oriented communication
Four-wire interface
Data transfer rates up to a maximum of one-half the system clock frequency
Error detection
Dedicated Baud Rate Generator
Architecture
The SPI can be configured as either a master (in single or multimaster systems) or a slave
as illustrated in Figures 22 through 24.
SPI Master
To Slave s SS Pin
From Slave
To Slave
To Slave
SS
MISO
8-Bit Shift Register
Bit 0
Bit 7
MOSI
SCK
Baud Rate
Generator
Figure 22. SPI Configured as a Master in a Single Master, Single Slave System
PS024604-1005
PRELIMINARY
Architecture
Z8 Encore!® Motor Control Flash MCUs
Product Specification
150
VCC
SPI Master
SS
To Slave #2 s SS Pin
GPIO
To Slave #1 s SS Pin
GPIO
MISO
From Slave
8-Bit Shift Register
Bit 0
Bit 7
MOSI
To Slave
SCK
To Slave
Baud Rate
Generator
Figure 23. SPI Configured as a Master in a Single Master, Multiple Slave System
SPI Slave
From Master
To Master
From Master
From Master
SS
MISO
8-Bit Shift Register
Bit 7
Bit 0
MOSI
SCK
Figure 24. SPI Configured as a Slave
Serial Peripheral Interface
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
151
Operation
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (serial clock, transmit, receive, and slave select). The SPI block consists of a
transmit/receive shift register, a Baud Rate (clock) Generator, and a control unit.
During an SPI transfer, data is sent and received simultaneously by both the master and the
slave SPI devices. Separate signals are required for data and the serial clock. When an SPI
transfer occurs, a multibit (typically 8-bit) character is shifted out one data pin and an
multibit character is simultaneously shifted in on a second data pin. An 8-bit shift register
in the master and another 8-bit shift register in the slave are connected as a circular buffer.
The SPI shift register is single-buffered in the transmit and receive directions. New data to
be transmitted cannot be written into the shift register until the previous transmission is
complete and receive data (if valid) has been read.
SPI Signals
The four basic SPI signals are:
•
•
•
•
Master-In, Slave-Out (MISO)
Master-Out, Slave-In (MOSI)
Serial Clock (SCK)
Slave Select (SS)
The following paragraphs discuss these SPI signals. Each signal is described in both
MASTER and SLAVE modes.
Master-In, Slave-Out
The Master-In, Slave-Out (MISO) pin is configured as an input in a master device and as
an output in a slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. The MISO pin of a slave device is placed in a high-impedance
state if the slave is not selected. When the SPI is not enabled, this signal is in a highimpedance state.
Master-Out, Slave-In
The Master-Out, Slave-In (MOSI) pin is configured as an output in a master device and as
an input in a slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
PS024604-1005
PRELIMINARY
Operation
Z8 Encore!® Motor Control Flash MCUs
Product Specification
152
Serial Clock
The Serial Clock (SCK) synchronizes data movement both in and out of the device
through its MOSI and MISO pins. In MASTER mode, the SPI’s Baud Rate Generator creates the serial clock. The master drives the serial clock through its own serial clock (SCK)
pin to the slave’s SCK pin. When the SPI is configured as a slave, the SCK pin is an input
and the clock signal from the master synchronizes the data transfer between the master and
slave devices. These slave devices ignore the SCK signal unless the SS pin is asserted.
When configured as a slave, the SPI block requires a minimum SCK period of greater than
or equal to 8 times the system (XIN) clock period.
The master and slave are each capable of exchanging a character of data during a sequence
of NUMBITS clock cycles (refer to the NUMBITS field in the SPIMODE Register). In both
master and slave SPI devices, data is shifted on one edge of the SCK and is sampled on the
opposite edge, where data is stable. Edge polarity is determined by the SPI phase and
polarity control.
Slave Select
The active Low Slave Select (SS) input signal selects a slave SPI device. SS must be Low
prior to all data communication to and from the slave device. SS must remain Low for the
full duration of each character transferred. The SS signal may stay Low during the transfer
of multiple characters, or may deassert between each character.
When the SPI is configured as the only master in an SPI system, the SS pin can be set as
either an input or an output. For communication between the Z8 Encore!® 8K Series
device’s SPI master and external slave devices, the SS signal, as an output, can assert the
SS input pin on one of the slave devices. Other GPIO output pins can also be employed to
select external SPI slave devices.
When the SPI is configured as one master in a multimaster SPI system, the SS pin should
be set as an input. The SS input signal on the master must be High. If the SS signal goes
Low (indicating that another master is driving the SPI bus), a collision error flag is set in
the SPI Status Register.
SPI Clock Phase and Polarity Control
The SPI supports four combinations of serial clock phase and polarity using two bits in the
SPI Control Register. The clock polarity bit, CLKPOL, selects an active High or active
Low clock and has no effect on the transfer format. Table 83 lists the SPI Clock Phase and
Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamentally different transfer formats. For proper data transmission, clock phase and polarity
must be identical for the SPI master and the SPI slave. The master always places data on
the MOSI line a half-cycle before the receive clock edge (SCK signal) for the slave to
latch the data.
Serial Peripheral Interface
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
153
Table 83. SPI Clock Phase and Clock Polarity Operation
PHASE
CLKPOL
SCK Transmit
Edge
SCK Receive
Edge
SCK Idle
State
0
0
Falling
Rising
Low
0
1
Rising
Falling
High
1
0
Rising
Falling
Low
1
1
Falling
Rising
High
Transfer Format Phase Equals Zero
Figure 25 illustrates the timing diagram for an SPI transfer in which PHASE is cleared to 0.
The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to
1. The diagram can be interpreted as either a master or slave timing diagram because the
SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly connected between the master and the slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MISO
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Sample Time
SS
Figure 25. SPI Timing When Phase is 0
PS024604-1005
PRELIMINARY
SPI Clock Phase and Polarity Control
Z8 Encore!® Motor Control Flash MCUs
Product Specification
154
Transfer Format Phase Equals One
Figure 26 illustrates the timing diagram for an SPI transfer in which PHASE is 1. Two
waveforms are depicted for SCK, one for CLKPOL reset to 0, and another for CLKPOL set
to 1.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MISO
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Sample Time
SS
Figure 26. SPI Timing When Phase is 1
Multimaster Operation
In a multimaster SPI system, all SCK pins are tied together, all MOSI pins are tied
together, and all MISO pins are tied together. All SPI pins must then be configured in
OPEN-DRAIN mode to prevent bus contention. At any time, only one SPI device is configured as the master and all other SPI devices on the bus are configured as slaves. The
master enables a single slave by asserting the SS pin on that slave only. Then, the single
master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the slaves
(including those which are not enabled). The enabled slave drives data out its MISO pin to
the MISO master pin.
For a master device operating in a multimaster system, if the SS pin is configured as an
input and is driven Low by another master, the COL bit is set to 1 in the SPI Status Register. The COL bit indicates the occurrence of a multimaster collision (mode fault error condition).
Serial Peripheral Interface
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
155
Slave Operation
The SPI block is configured for SLAVE mode operation by setting the SPIEN bit to 1 and
the MMEN bit to 0 in the SPICTL Register and setting the SSIO bit to 0 in the SPIMODE
Register. The IRQE, PHASE, CLKPOL, and WOR bits in the SPICTL Register and the NUMBITS field in the SPIMODE Register must be set to be consistent with the other SPI
devices. The STR bit in the SPICTL Register can be used, if appropriate, to force a startup interrupt. The BIRQ bit in the SPICTL Register and the SSV bit in the SPIMODE Register are not used in SLAVE mode. The SPI baud rate generator is not used in SLAVE
mode; therefore, the SPIBRH and SPIBRL registers do not require initialization.
If the slave contains data to send to the master, the data should be written to the SPIDAT
Register before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT Register is not written prior to the slave transaction, the MISO pin outputs the value
that is currently in the SPIDAT Register.
Due to the delay resulting from synchronization of the SPI input signals to the internal system clock, the maximum SPICLK baud rate that can be supported in SLAVE mode is the
system clock frequency (XIN) divided by 8. This rate is controlled by the SPI master.
Error Detection
The SPI contains error detection logic that supports SPI communication protocols and recognizes when communication errors have occurred. The SPI Status Register indicates
when a data transmission error has been detected.
Overrun
An overrun error (write collision) indicates that a Write to the SPI Data Register was
attempted while a data transfer is in progress (in either MASTER or SLAVE modes). An
overrun sets the OVR bit in the SPI Status Register to 1. Writing a 1 to OVR clears this
error flag. The SPI Data Register is not altered when a Write occurs while a data transfer is
in progress.
Mode Fault
A mode fault indicates when more than one master is trying to communicate at the same
time (a multimaster collision). The mode fault is detected when the enabled master’s SS
pin is asserted. A mode fault sets the COL bit in the SPI Status Register to 1. Writing a 1 to
COL clears this error flag.
Slave Mode Abort
In SLAVE mode, if the SS pin deasserts before all bits in a character have been transferred, the transaction aborts. When this condition occurs, the ABT bit is set in the
SPISTAT Register as well as the IRQ bit (which indicates that the transaction is complete).
PS024604-1005
PRELIMINARY
Slave Operation
Z8 Encore!® Motor Control Flash MCUs
Product Specification
156
The next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous transaction suspended. Writing a 1 to ABT clears this error flag.
SPI Interrupts
When SPI interrupts are enabled, the SPI generates an interrupt after character transmission/reception is completed in both MASTER and SLAVE modes. A character can be
defined to be 1–8 bits by the NUMBITS field in the SPI Mode Register. In SLAVE mode, it
is not necessary for SS to deassert between characters to generate an interrupt. The SPI in
SLAVE mode can also generate an interrupt if the SS signal deasserts prior to transfer of
all the bits in a character (see description of slave abort error above). Writing a 1 to the
IRQ bit in the SPI Status Register clears the pending SPI interrupt request. The IRQ bit
must be cleared to 0 by the interrupt service routine to generate future interrupts. To start
the transfer process, an SPI interrupt can be forced by software to write a 1 to the STR bit
in the SPICTL Register.
If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator timeout. This timer function must be enabled by setting the BIRQ bit in the SPICTL Register.
This Baud Rate Generator time-out does not set the IRQ bit in the SPISTAT Register, just
the SPI interrupt bit in the interrupt controller.
SPI Baud Rate Generator
In SPI MASTER mode, the Baud Rate Generator creates a lower-frequency serial clock
(SCK) for data transmission synchronization between the master and the external slave.
The input to the Baud Rate Generator is from the system clock. The SPI Baud Rate High
and Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI
Baud Rate Generator. The SPI baud rate is calculated using the following equation:
SPI Baud Rate (bits/s) =
System Clock Frequency (Hz)
2 x BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000h for a clock divisor value
of (2 x 65536 = 131072).
When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with an interrupt upon time-out. To configure the Baud Rate Generator as a timer with an
interrupt upon time-out, complete the following procedure:
1. Disable the SPI by clearing the SPIEN bit in the SPI Control Register to 0.
2. Load the appropriate 16-bit count value into the SPI Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and the associated interrupt by setting
the BIRQ bit in the SPI Control Register to 1.
Serial Peripheral Interface
PRELIMINARY
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Z8FMC16100 Series Flash MCU
Product Specification
157
SPI Data Register
The SPI Data Register stores both the outgoing (transmit) data and the incoming (receive)
data. Reads from the SPI Data Register always return the current contents of the 8-bit shift
register. Data is shifted out starting with bit 7. The last bit received resides in bit position 0.
With the SPI configured as a master, writing a data byte to this register initiates data transmission. With the SPI configured as a slave, writing a data byte to this register loads the
shift register in preparation for the next data transfer with the external master. In either
MASTER or SLAVE mode, if a transmission is already in progress, Writes to this register
are ignored and the overrun error flag, OVR, is set in the SPI Status Register.
When character length is less than 8 bits (as set by the NUMBITS field in the SPI Mode Register), the transmit character must be left-justified in the SPI Data Register. A received character of less than 8 bits is right-justified (the final bit received is in bit position 0). For
example, if the SPI is configured for 4-bit characters, the transmit characters must be written
to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0]. See Table 84.
Table 84. SPI Data Register (SPIDATA)
BITS
7
6
5
4
3
FIELD
DATA
RESET
X
R/W
R/W
ADDR
F60H
2
1
0
DATA—Data
Transmit and/or receive data.
PS024604-1005
PRELIMINARY
SPI Data Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
158
SPI Control Register
The SPI Control Register configures the SPI for transmit and receive operations.
Table 85. SPI Control Register (SPICTL)
BITS
7
6
5
4
3
2
1
0
FIELD
IRQE
STR
BIRQ
PHASE
CLKPOL
WOR
MMEN
SPIEN
RESET
00H
R/W
R/W
ADDR
F61H
IRQE—Interrupt Request Enable
0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.
1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.
STR—Start an SPI Interrupt Request
0 = No effect.
1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status register to 1. Setting this bit
forces the SPI to send an interrupt request to the Interrupt Control. This bit can be used by
software for a function similar to transmit buffer empty in a UART. Writing a 1 to the
IRQ bit in the SPI Status register clears this bit to 0.
BIRQ—BRG Timer Interrupt Request
If the SPI is enabled, this bit has no effect. If the SPI is disabled:
0 = The Baud Rate Generator timer function is disabled.
1 = The Baud Rate Generator timer function and time-out interrupt are enabled.
PHASE—Phase Select
Sets the phase relationship of the data to the clock. Refer to the SPI Clock Phase and
Polarity Control section for more information on operation of the PHASE bit.
CLKPOL—Clock Polarity
0 = SCK idles Low (0).
1 = SCK idle High (1).
WOR—Wire-OR (Open-Drain) Mode Enabled
0 = SPI signal pins not configured for open-drain.
1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function.
This setting is typically used for multi-master and/or multi-slave configurations.
MMEN—SPI MASTER Mode Enable
0 = SPI configured in SLAVE mode.
1 = SPI configured in MASTER mode.
Serial Peripheral Interface
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SPIEN—SPI Enable
0 = SPI disabled.
1 = SPI enabled.
SPI Status Register
The SPI Status Register indicates the current state of the SPI. All bits revert to their reset
state if the SPIEN bit in the SPICTL Register = 0.
Table 86. SPI Status Register (SPISTAT)
BITS
7
6
5
4
FIELD
IRQ
OVR
COL
ABT
RESET
0
0
0
0
R/W
3
2
Reserved
0
0
R/W*
1
0
TXST
SLAS
0
1
R
F62H
ADDR
R/W* = Read access. Write a 1 to clear the bit to 0.
IRQ—Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL register is set, or upon completion
of an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud
Rate Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
OVR—Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
COL—Collision
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
ABT—SLAVE mode transaction abort
This bit is set if the SPI is configured in SLAVE mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE register. The IRQ bit also sets, indicating the transaction has completed.
0 = A SLAVE mode transaction abort has not occurred.
1 = A SLAVE mode transaction abort has been detected.
Reserved—Must be 0.
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SPI Status Register
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TXST—Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
SLAS—Slave Select
If SPI enabled as a Slave,
0 = SS input pin is asserted (Low)
1 = SS input is not asserted (High).
If SPI enabled as a Master, this bit is not applicable.
SPI Mode Register
The SPI Mode Register configures the character bit width and the direction and value of
the SS pin.
Table 87. SPI Mode Register (SPIMODE)
BITS
FIELD
7
6
Reserved
5
DIAG
4
3
2
NUMBITS[2:0]
1
0
SSIO
SSV
00H
RESET
R
R/W
R/W
F63H
ADDR
Reserved—Must be 0.
DIAG - Diagnostic Mode Control bit
This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be
read using the SPIBRH and SPIBRL register locations.
0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers
1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading SPIBRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High and
Low byte values are not buffered.
Caution:
Exercise caution if reading the values while the BRG is counting.
NUMBITS[2:0]—Number of Data Bits Per Character to Transfer
This field contains the number of bits to shift for each character transfer. Refer to the SPI
Data Register description for information on valid bit positions when the character length
is less than 8-bits.
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000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bits
110 = 6 bits
111 = 7 bits
SSIO—Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (MASTER mode only).
SSV—Slave Select Value
If SSIO = 1 and SPI configured as a Master:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or SPI configured as a Slave
SPI Diagnostic State Register
The SPI Diagnostic State Register provides observability of internal state. It is a read-only
register used for SPI diagnostics. More detail about each bit follows the table.
Table 88. SPI Diagnostic State Register (SPIDST)
BITS
7
6
FIELD
SCKEN
TCKEN
5
4
3
2
1
0
SPISTATE
RESET
00H
R/W
R
ADDR
F64H
SCKEN - Shift Clock Enable
0 = The internal Shift Clock Enable signal is deasserted
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next system clock)
TCKEN - Transmit Clock Enable
0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial
data out is updated on the next system clock (MOSI or MISO).
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SPISTATE - SPI State Machine
Defines the current state of the internal SPI State Machine.
SPI Baud Rate High and Low Byte Registers
The SPI Baud Rate High and Low Byte registers combine to form a 16-bit reload value,
BRG[15:0], for the SPI Baud Rate Generator. The SPI baud rate is calculated using the
following equation:
SPI Baud Rate (bits/s) =
System Clock Frequency (Hz)
2 x BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000h for a clock divisor value
of (2 X 65536 = 131072).
Table 89. SPI Baud Rate High Byte Register (SPIBRH)
BITS
7
6
5
4
3
FIELD
BRH
RESET
FFH
R/W
R/W
ADDR
F66H
2
1
0
BRH = SPI Baud Rate High Byte
Most significant byte, BRG[15:8], of the SPI Baud Rate Generator’s reload value.
Table 90. SPI Baud Rate Low Byte Register (SPIBRL)
BITS
7
6
5
4
3
FIELD
BRL
RESET
FFH
R/W
R/W
ADDR
F67H
2
1
0
BRL = SPI Baud Rate Low Byte
Least significant byte, BRG[7:0], of the SPI Baud Rate Generator’s reload value.
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I2C Master/Slave Controller
The I2C Master/Slave Controller ensures that the Z8FMC16100 Series Flash MCU
devices are bus-compatible with the I2C protocol. The I2C bus consists of the serial data
signal (SDA) and a serial clock signal (SCL) bidirectional lines. Features of the I2C controller include:
•
•
•
•
•
•
•
Operates in MASTER/SLAVE or SLAVE ONLY modes
•
•
Unrestricted number of data bytes per transfer
Supports arbitration in a multimaster environment (MASTER/SLAVE mode)
Supports data rates up to 400 Kbps
7- or 10-bit slave address recognition (interrupt only on address match)
Optional general call address recognition
Optional digital filter on receive SDA, SCL lines
Optional interactive receive mode allows software interpretation of each received address and/or data byte before acknowledging
Baud Rate Generator can be used as a general-purpose timer with an interrupt if the I2C
controller is disabled.
Architecture
Figure 27 illustrates the architecture of the I2C controller.
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SDA
Shift
SCL
SHIFT
I2CDATA
Baud Rate Generator
Load
I2CBRH
I2CBRL
I2CISTAT
Tx/Rx State Machine
I2CCTL
I2CMODE
I2CSLVAD
I2C Interrupt
I2CSTATE
Register Bus
Figure 27. I2C Controller Block Diagram
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I2C Master/Slave Controller Registers
Table 91 summarizes the I2C master/slave controller’s software-accessible registers.
Table 91. I2C Master/Slave Controller Registers
Name
Abbreviation
Description
I2C Data
I2CDATA
Transmit/receive data register.
I2
C Interrupt Status I2CISTAT
I2C Control
I2CCTL
Interrupt status register.
Control register—basic control functions.
I2C Baud Rate High I2CBRH
High byte of baud rate generator initialization
value.
I2C Baud Rate Low I2CBRL
Low byte of baud rate generator initialization
value.
I2C State
I2CSTATE
State register.
I2C Mode
I2CMODE
Selects MASTER or SLAVE modes, 7- or 10-bit
addressing; configure address recognition, define
slave address bits [9:8].
I2C Slave Address
I2CSLVAD
Defines slave address bits [7:0].
Comparison with the Master Mode Only I2C Controller
Porting code written for the MASTER ONLY I2C controller found on other Z8 Encore!®
parts to the I2C Master/Slave Controller is straightforward. The I2CDATA, I2CCTL,
I2CBRH and I2CBRL Register definitions have not changed. The following bullets highlight the differences between these two designs.
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•
The Status (I2CSTATE) Register from the MASTER ONLY I2C controller is split into
the Interrupt Status (I2CISTAT) Register and the State (I2CSTATE) Register because
more interrupt sources are available. The ACK, 10B, TAS (now called AS), and DSS
(now called DS) bits, formerly part of the Status Register, are now part of the State Register.
•
The I2CSTATE Register was called the Diagnostic State (I2CDST) Register in the
MASTER-mode-only version. The I2CDST Register provided diagnostic information.
The I2CSTATE Register contains status and state information that may be useful to
software in an operational mode.
•
The I2CMODE Register was called the Diagnostic Control (I2CDIAG) Register in the
MASTER-mode-only version. The I2CMODE Register provides control for the
SLAVE modes of operation, as well as the most significant two bits of the 10-bit slave
address.
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•
The I2CSLVAD Register is added to provide programming capabilities for the slave
address.
•
The ACKV bit in the I2CSTATE Register enables the master to check the Acknowledge from the slave before sending the next byte.
•
Support for multimaster environments—if arbitration is lost when operating as a master, the ARBLST bit in the I2CISTAT Register is set and the mode automatically
switches to SLAVE mode.
Operation
The I2C Master/Slave Controller operates in MASTER/SLAVE mode, SLAVE ONLY
mode, or with master arbitration. In MASTER/SLAVE mode, it can be used as the only
master on the bus or as one of several masters on the bus, with arbitration. In a multimaster
environment, the controller switches from MASTER to SLAVE mode upon losing arbitration.
Though slave operation is fully supported in MASTER/SLAVE mode, if a device is
intended to operate only as a slave, then SLAVE ONLY mode can be selected. In SLAVE
ONLY mode, the device will not initiate a transaction, even if the software inadvertently
sets the START bit.
SDA and SCL Signals
The I2C circuit sends all addresses, data, and Acknowledge signals over the SDA line,
most-significant bit first. SCL is the clock for the I2C bus. When the SDA and SCL pin
alternate functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.
The master is responsible for driving the SCL clock signal. During the Low period of the
clock, a slave can hold the SCL signal Low to suspend the transaction if it is not ready to
proceed. The master releases the clock at the end of the Low period and notices that the
clock remains Low instead of returning to a High level. When the slave releases the clock,
the I2C master continues the transaction. All data is transferred in bytes; there is no limit to
the amount of data transferred in one operation. When transmitting address, data, or an
Acknowledge, the SDA signal changes in the middle of the Low period of SCL. When
receiving address, Data or an Acknowledge, the SDA signal is sampled in the middle of
the High period of SCL.
A low-pass digital filter can be applied to the SDA and SCL receive signals by setting the
Filter Enable (FILTEN) bit in the I2C Control Register. When the filter is enabled, any
glitch that is less than a system clock period in width will be rejected. This filter should be
enabled when running in I2C FAST mode (400 kbps), and can also be used at lower data
rates.
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I2C Interrupts
The I2C controller contains multiple interrupt sources that are combined into one interrupt
request signal to the interrupt controller. If the I2C controller is enabled, the source of the
interrupt is determined by which bits are set in the I2CISTAT Register. If the I2C controller is disabled, the BRG controller can be used to generate general-purpose timer interrupts.
Each interrupt source, other than the baud rate generator interrupt, features an associated
bit in the I2CISTAT Register that clears automatically when software reads the register or
performs another task, such as reading/writing the data register.
Transmit Interrupts
Transmit interrupts (TDRE bit = 1 in I2CISTAT) occur under the following conditions, both
of which must be true.
•
•
The transmit data register is empty and the TXI bit = 1 in the I2C Control Register
The I2C controller is enabled, with one of the following:
– The first bit of a 10-bit address is shifted out
– The first bit of the final byte of an address is shifted out and the RD bit is deasserted
– The first bit of a data byte is shifted out
Writing to the I2C Data Register always clears the TRDE bit to 0.
Receive Interrupts
Receive interrupts (RDRF bit = 1 in I2CISTAT) occur when a byte of data has been
received by the I2C controller. The RDRF bit is cleared by reading from the I2C Data Register. If the RDRF interrupt is not serviced prior to the completion of the next Receive
byte, the I2C controller holds SCL Low during the final data bit of the next byte until
RDRF is cleared, to prevent receive overruns. A receive interrupt does not occur when a
slave receives an address byte or for data bytes following a slave address that did not
match. An exception is if the Interactive Receive Mode (IRM) bit is set in the I2CMODE
Register, in which case Receive interrupts occur for all Receive address and data bytes in
SLAVE mode.
Slave Address Match Interrupts
Slave address match interrupts (SAM bit = 1 in I2CISTAT) occur when the I2C controller is
in SLAVE mode and an address is received that matches the unique slave address. The
General Call Address (0000_0000) and STARTBYTE (0000_0001) are recognized if the
GCE bit = 1 in the I2CMODE Register. The software checks the RD bit in the I2CISTAT
Register to determine if the transaction is a Read or Write transaction. The General Call
Address and STARTBYTE address are also distinguished by the RD bit. The General Call
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Address (GCA) bit of the I2CISTAT Register indicates whether the address match occurred
on the unique slave address or the General Call/STARTBYTE address. The SAM bit clears
automatically when the I2CISTAT Register is read.
If configured via the MODE[1:0] field of the I2C Mode Register for 7-bit slave addressing, the most significant 7 bits of the first byte of the transaction are compared against the
SLA[6:0] bits of the Slave Address Register. If configured for 10-bit slave addressing,
the first byte of the transaction is compared against {11110,SLA[9:8],R/W} and the second byte is compared against SLA[7:0].
Arbitration Lost Interrupts
Arbitration Lost interrupts (ARBLST bit = 1 in I2CISTAT) occur when the I2C controller is
in MASTER mode and loses arbitration (outputs a 1 on SDA and receives a 0 on SDA).
The I2C controller switches to SLAVE mode when this instance occurs. This bit clears
automatically when the I2CISTAT Register is read.
Stop/Restart Interrupts
A Stop/Restart event interrupt (SPRS bit = 1 in I2CISTAT) occurs when the I2C controller
is in SLAVE mode and a STOP or RESTART condition is received, indicating the end of the
transaction. The RSTR bit in the I2C State Register indicates whether the bit was set due to
a STOP or RESTART condition. When a restart occurs, a new transaction by the same master is expected to follow. This bit is cleared automatically when the I2CISTAT Register is
read. The STOP/RESTART interrupt only occurs on a selected (address match) slave.
Not Acknowledge Interrupts
Not Acknowledge interrupts (NCKI bit = 1 in I2CISTAT) occur in MASTER mode when a
Not Acknowledge is received or sent by the I2C controller and the START or STOP bit is
not set in the I2C Control Register. In MASTER mode, the Not Acknowledge interrupt
clears by setting the START or STOP bit. When this interrupt occurs in MASTER mode,
the I2C controller waits until it is cleared before performing any action. In SLAVE mode,
the Not Acknowledge interrupt occurs when a Not Acknowledge is received in response to
data sent. The NCKI bit clears in SLAVE mode when software reads the I2CISTAT Register.
General Purpose Timer Interrupt from Baud Rate Generator
If the I2C controller is disabled (IEN bit in the I2CCTL Register = 0) and the BIRQ bit in
the I2CCTL Register = 1, an interrupt is generated when the baud rate generator (BRG)
counts down to 1. The baud rate generator reloads and continues counting, providing a
periodic interrupt. None of the bits in the I2CISTAT Register are set, allowing the BRG in
the I2C controller to be used as a general-purpose timer when the I2C controller is disabled.
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Start and Stop Conditions
The master generates the START and STOP conditions to start or end a transaction. To
start a transaction, the I2C controller generates a START condition by pulling the SDA signal Low while SCL is High. To complete a transaction, the I2C controller generates a
STOP condition by creating a Low-to-High transition of the SDA signal while the SCL
signal is High. These START and STOP events occur when the START and STOP bits in
the I2C Control Register are written by software to begin or end a transaction. Any byte
transfer currently under way, including the Acknowledge phase, finishes before the
START or STOP condition occurs.
Software Control of I2C Transactions
The I2C controller is configured via the I2C Control and I2C Mode registers. The
MODE[1:0] field of the I2C Mode Register allows the configuration of the I2C controller
for MASTER/SLAVE or SLAVE ONLY mode, and configures the slave for 7- or 10-bit
addressing recognition.
MASTER/SLAVE mode can be used for:
•
•
•
MASTER ONLY operation in a single master/one or more slave I2C system
MASTER/SLAVE in a multimaster/multislave I2C system
SLAVE ONLY operation in an I2C system
In SLAVE ONLY mode, the START bit of the I2C Control Register is ignored (software
cannot initiate a master transaction by accident), and operation to SLAVE ONLY mode is
restricted, thereby preventing accidental operation in MASTER mode.
The software can control I2C transactions by enabling the I2C controller interrupt in the
interrupt controller or by polling the I2C Status Register.
To use interrupts, the I2C interrupt must be enabled in the interrupt controller and followed
by executing an EI instruction. The TXI bit in the I2C Control Register must be set to
enable transmit interrupts. An I2C interrupt service routine then checks the I2C Status
Register to determine the cause of the interrupt.
To control transactions by polling, the TDRE, RDRF, SAM, ARBLST, SPRS, and NCKI interrupt bits in the I2C Status Register should be polled. The TDRE bit asserts regardless of the
state of the TXI bit.
Master Transactions
The following sections describe master Read and Write transactions to both 7- and 10-bit
slaves.
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Master Arbitration
If a master loses arbitration during the address byte, it releases the SDA line, switches to
SLAVE mode and monitors the address to determine if it is selected as a slave. If a master
loses arbitration during the transmission of a data byte, it releases the SDA line and waits
for the next STOP or START condition.
The master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the
bus in the same bit-time. This loss occurs if more than one master is simultaneously
accessing the bus. Loss of arbitration can occur during the address phase (two or more
masters accessing different slaves) or during the data phase, when the masters are attempting to write different data to the same slave.
When a master loses arbitration, the software is informed by means of the Arbitration Lost
interrupt. The software can repeat the same transaction at a later time.
A special case can occur when a slave transaction starts just before the software attempts
to start a new master transaction by setting the START bit. In this case, the state machine
enters its slave states before the START bit is set, and as a result, the I2C controller will not
arbitrate. If a slave address match occurs and the I2C controller receives/transmits data, the
START bit is cleared and an Arbitration Lost interrupt is asserted. The software can minimize the chance of this instance occurring by checking the BUSY bit in the I2CSTATE
Register before initiating a master transaction. If a slave address match does not occur, the
Arbitration Lost interrupt will not occur, and the START bit will not be cleared. The I2C
controller will initiate the master transaction after the I2C bus is no longer busy.
Master Address-Only Transactions
It is sometimes preferable to perform an address-only transaction to determine if a particular slave device is able to respond. This transaction can be performed by monitoring the
ACKV bit in the I2CSTATE Register after the address has been written to the I2CDATA
Register and the START bit has been set. After the ACKV bit is set, the ACK bit in the
I2CSTATE Register determines if the slave is able to communicate. The STOP bit must be
set in the I2CCTL Register to terminate the transaction without transferring data. For a 10bit slave address, if the first address byte is acknowledged, the second address byte should
also be sent to determine if the preferred slave is responding.
Another approach is to set both the STOP and START bits (for sending a 7-bit address).
After both bits have cleared (7-bit address has been sent and transaction is complete), the
ACK bit can be read to determine if the slave has acknowledged. For a 10-bit slave, set the
STOP bit after the second TDRE interrupt (which indicates that the second address byte is
being sent).
Master Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate the data that is transferred from the master to the slave, and the unshaded regions indicate the data that is transferred from the slave to the master. The transaction field labels are defined as follows:
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S
Start
W
Write
A
Acknowledge
A
Not Acknowledge
P
Stop
Master Write Transaction with a 7-Bit Address
Figure 28 illustrates the data transfer format from a master to a 7-bit addressed slave
S
Slave
Address
W=0
A
Data
A
Data
A
Data
A/A
P/S
Figure 28. Data Transfer Format—Master Write Transaction with a 7-Bit Address
The procedure for a master transmit operation to a 7-bit addressed slave is as follows:
1. The software initializes the MODE field in the I2C Mode Register for MASTER/
SLAVE mode with either a 7- or 10-bit slave address. The MODE field selects the
address width for this mode when addressed as a slave (but not for the remote slave).
The software asserts the IEN bit in the I2C Control Register.
2. The software asserts the TXI bit of the I2C Control Register to enable transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty.
4. The software responds to the TDRE bit by writing a 7-bit slave address plus the Write
bit (which is cleared to 0) to the I2C Data Register.
5. The software sets the START bit of the I2C Control Register.
6. The I2C controller sends a START condition to the I2C slave.
7. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Register.
8. After one bit of the address has been shifted out by the SDA signal, the transmit interrupt asserts.
9. The software responds by writing the transmit data into the I2C Data Register.
10. The I2C controller shifts the remainder of the address and the Write bit out via the
SDA signal.
11. The I2C slave sends an Acknowledge (by pulling the SDA signal Low) during the next
high period of SCL. The I2C controller sets the ACK bit in the I2C Status Register.
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If the slave does not acknowledge the address byte, the I2C controller sets the NCKI
bit in the I2C Status Register, sets the ACKV bit, and clears the ACK bit in the I2C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXI bit. The I2C controller flushes the Transmit Data Register,
sends a STOP condition on the bus, and clears the STOP and NCKI bits. The transaction
is complete, and the following steps can be ignored.
12. The I2C controller loads the contents of the I2C Shift Register with the contents of the
I2C Data Register.
13. The I2C controller shifts the data out via the SDA signal. After the first bit is sent, the
transmit interrupt asserts.
14. If more bytes remain to be sent, return to Step 9.
15. When there is no more data to be sent, the software responds by setting the STOP bit of
the I2C Control Register (or the START bit to initiate a new transaction).
16. If no additional transaction is queued by the master, the software can clear the TXI bit
of the I2C Control Register.
17. The I2C controller completes transmission of the data on the SDA signal.
18. The I2C controller sends a STOP condition to the I2C bus.
Note: If the slave terminates the transaction early by responding with a Not Acknowledge during
the transfer, the I2C controller asserts the NCKI interrupt and halts. The software must terminate the transaction by setting either the STOP bit (end transaction) or the START bit
(end this transaction, start a new one). In this case, it is not necessary for software to set
the FLUSH bit of the I2CCTL Register to flush the data that was previously written but not
transmitted. The I2C controller hardware automatically flushes transmit data in this not
acknowledge case.
Master Write Transaction with a 10-Bit Address
Figure 29 illustrates the data transfer format from a master to a 10-bit addressed slave.
S
Slave Address
1st Byte
W=0
A
Slave Address
2nd Byte
A
Data
A
Data
A/A
F/S
Figure 29. Data Transfer Format—Master Write Transaction with a 10-Bit Address
The first seven bits transmitted in the first byte are 11110XX. The two XX bits are the two
most significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
Read/Write control bit (which is cleared to 0). The transmit operation is performed in the
same manner as 7-bit addressing.
The procedure for a master transmit operation to a 10-bit addressed slave is as follows:
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1. The software initializes the MODE field in the I2C Mode Register for MASTER/
SLAVE mode with 7- or 10-bit addressing (the I2C bus protocol allows the mixing of
slave address types). The MODE field selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IEN bit in
the I2C Control Register.
2. The software asserts the TXI bit of the I2C Control Register to enable transmit interrupts.
3. The I2C interrupt asserts because the I2C Data Register is empty.
4. The software responds to the TDRE interrupt by writing the first slave address byte
(11110xx0). The least-significant bit must be 0 for the write operation.
5. The software asserts the START bit of the I2C Control Register.
6. The I2C controller sends a START condition to the I2C slave.
7. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Register.
8. After one bit of the address is shifted out by the SDA signal, the transmit interrupt
asserts.
9. The software responds by writing the second byte of address into the contents of the
I2C Data Register.
10. The I2C controller shifts the remainder of the first byte of the address and the Write bit
out via the SDA signal.
11. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next
high period of SCL. The I2C controller sets the ACK bit in the I2C Status Register.
If the slave does not acknowledge the first address byte, the I2C controller sets the
NCKI bit in the I2C Status Register, sets the ACKV bit, and clears the ACK bit in the I2C
State Register. The software responds to the Not Acknowledge interrupt by setting the
STOP bit and clearing the TXI bit. The I2C controller flushes the second address byte
from the data register, sends a STOP condition on the bus, and clears the STOP and
NCKI bits. The transaction is complete, and the following steps can be ignored.
12. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Register (2nd address byte).
13. The I2C controller shifts the second address byte out via the SDA signal. After the
first bit has been sent, the transmit interrupt asserts.
14. The software responds by writing the data to be written out to the I2C Control Register.
15. The I2C controller shifts out the remainder of the second byte of the slave address (or
ensuing data bytes, if looping) via the SDA signal.
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16. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next
high period of SCL. The I2C controller sets the ACK bit in the I2C Status Register.
If the slave does not acknowledge, refer to the second paragraph of Step 11.
17. The I2C controller shifts the data out by the SDA signal. After the first bit is sent, the
transmit interrupt asserts.
18. If more bytes remain to be sent, return to Step 14.
19. The software responds by asserting the STOP bit of the I2C Control Register.
20. The I2C controller completes transmission of the data on the SDA signal.
21. The I2C controller sends a STOP condition to the I2C bus.
Note: If the slave responds with a Not Acknowledge during the transfer, the I2C controller
asserts the NCKI bit, sets the ACKV bit, clears the ACK bit in the I2C State Register, and
halts. The software terminates the transaction by setting either the STOP bit (end transaction) or the START bit (end this transaction, start a new one). The Transmit Data Register
is flushed automatically.
Master Read Transaction with a 7-Bit Address
Figure 30 illustrates the data transfer format for a read operation to a 7-bit addressed slave.
S
Slave Address
R=1
A
Data
A
Data
A
P/S
Figure 30. Data Transfer Format—Master Read Transaction with a 7-Bit Address
The procedure for a master Read operation to a 7-bit addressed slave is as follows:
1. The software initializes the MODE field in the I2C Mode Register for MASTER/
SLAVE mode with 7- or 10-bit addressing (the I2C bus protocol allows the mixing of
slave address types). The MODE field selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IEN bit in
the I2C Control Register.
2. The software writes the I2C Data Register with a 7-bit slave address, plus the Read bit
(which is set to 1).
3. The software asserts the START bit of the I2C Control Register.
4. If this operation is a single-byte transfer, the software asserts the NAK bit of the I2C
Control Register so that after the first byte of data has been read by the I2C controller,
a Not Acknowledge instruction is sent to the I2C slave.
5. The I2C controller sends a START condition.
6. The I2C controller sends the address and Read bit out via the SDA signal.
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7. The I2C slave acknowledges the address by pulling the SDA signal Low during the
next high period of SCL.
If the slave does not acknowledge the address byte, the I2C controller sets the NCKI
bit in the I2C Status Register, sets the ACKV bit, and clears the ACK bit in the I2C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXI bit. The I2C controller flushes the Transmit Data Register,
sends a STOP condition on the bus, and clears the STOP and NCKI bits. The transaction
is complete, and the following steps can be ignored.
8. The I2C controller shifts in the first byte of data from the I2C slave on the SDA signal.
9. The I2C controller asserts the receive interrupt.
10. The software responds by reading the I2C Data Register. If the next data byte is to be
the final byte, the software must set the NAK bit of the I2C Control Register.
11. The I2C controller sends a Not Acknowledge to the I2C slave if the next byte is the
final byte; otherwise, it sends an Acknowledge.
12. If there are more bytes to transfer, the I2C controller returns to Step 7.
13. A NAK interrupt (NCKI bit in I2CISTAT) is generated by the I2C controller.
14. The software responds by setting the STOP bit of the I2C Control Register.
15. A STOP condition is sent to the I2C slave.
Master Read Transaction with a 10-Bit Address
Figure 31 illustrates the read transaction format for a 10-bit addressed slave.
S
Slave Address W=0 A Slave Address A S Slave Address R=1
1st Byte
2nd Byte
1st Byte
A
Data
A
Data
A P
Figure 31. Data Transfer Format—Master Read Transaction with a 10-Bit Address
The first seven bits transmitted in the first byte are 11110XX. The two XX bits are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
The data transfer procedure for a Read operation to a 10-bit addressed slave is as follows:
1. The software initializes the MODE field in the I2C Mode Register for MASTER/
SLAVE mode with 7- or 10-bit addressing (the I2C bus protocol allows the mixing of
slave address types). The MODE field selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IEN bit in
the I2C Control Register.
2. The software writes 11110b, followed by the two most-significant address bits and a
0 (write) to the I2C Data Register.
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3. The software asserts the START bit of the I2C Control Register.
4. The I2C controller sends a START condition.
5. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Register.
6. After the first bit has been shifted out, a transmit interrupt is asserted.
7. The software responds by writing the least significant eight bits of address to the I2C
Data Register.
8. The I2C controller completes shifting of the first address byte.
9. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next
high period of SCL.
If the slave does not acknowledge the address byte, the I2C controller sets the NCKI
bit in the I2C Status Register, sets the ACKV bit and clears the ACK bit in the I2C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXI bit. The I2C controller flushes the Transmit Data Register,
sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete, and the following steps can be ignored.
10. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Register (the lower byte of the 10-bit address).
11. The I2C controller shifts out the next eight bits of the address. After the first bit shifts,
the I2C controller generates a transmit interrupt.
12. The software responds by setting the START bit of the I2C Control Register to generate
a repeated START condition.
13. The software writes 11110b, followed by the 2-bit slave address and a 1 (Read) to the
I2C Data Register.
14. If the user chooses to read only one byte, the software responds by setting the NAK bit
of the I2C Control Register.
15. After the I2C controller shifts out the address bits listed in Step 9 (the second address
transfer), the I2C slave sends an Acknowledge by pulling the SDA signal Low during
the next High period of SCL.
If the slave does not acknowledge the address byte, the I2C controller sets the NCKI
bit in the I2C Status Register, sets the ACKV bit, and clears the ACK bit in the I2C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXI bit. The I2C controller flushes the Transmit Data Register,
sends the STOP condition on the bus, and clears the STOP and NCKI bits. The transaction is complete, and the following steps can be ignored.
16. The I2C controller sends a repeated START condition.
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17. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Register (the third address transfer).
18. The I2C controller sends 11110b, followed by the two most-significant bits of the
slave read address and a 1 (Read).
19. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next
High period of SCL.
20. The I2C controller shifts in a byte of data from the slave.
21. The I2C controller asserts the Receive interrupt.
22. The software responds by reading the I2C Data Register. If the next data byte is to be
the final byte, the software must set the NAK bit of the I2C Control Register.
23. The I2C controller sends an Acknowledge or Not Acknowledge to the I2C slave, based
on the value of the NAK bit.
24. If there are more bytes to transfer, the I2C controller returns to Step 18.
25. The I2C controller generates a NAK interrupt (the NCKI bit in the I2CISTAT Register).
26. The software responds by setting the STOP bit of the I2C Control Register.
27. A STOP condition is sent to the I2C slave.
Slave Transactions
The following sections describe Read and Write transactions to the I2C controller configured for 7- and 10-bit slave modes.
Slave Address Recognition
The following slave address recognition options are supported.
Slave 7-Bit Address Recognition Mode. If IRM = 0 during the address phase and the
controller is configured for MASTER/SLAVE or SLAVE 7-bit address mode, the hardware detects a match to the 7-bit slave address defined in the I2CSLVAD Register and
generates the slave address match interrupt (the SAM bit = 1 in the I2CISTAT Register).
The I2C controller automatically responds during the Acknowledge phase with the value
in the NAK bit of the I2CCTL Register.
Slave 10-Bit Address Recognition Mode. If IRM = 0 during the address phase and the
controller is configured for MASTER/SLAVE or SLAVE 10-bit address mode, the hardware detects a match to the 10-bit slave address defined in the I2CMODE and I2CSLVAD
registers and generates the slave address match interrupt (the SAM bit = 1 in the I2CISTAT
Register). The I2C controller automatically responds during the Acknowledge phase with
the value in the NAK bit of the I2CCTL Register.
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General Call and Start Byte Address Recognition. If GCE = 1 and IRM = 0 during the
address phase, and the controller is configured for MASTER/SLAVE or SLAVE in either
7- or 10-bit address modes, the hardware detects a match to the General Call Address or
the START byte and generates the slave address match interrupt. A General Call Address
is a 7-bit address of all 0’s with the R/W bit = 0. A START byte is a 7-bit address of all 0’s
with the R/W bit = 1. The SAM and GCA bits are set in the I2CISTAT Register. The RD bit in
the I2CISTAT Register distinguishes a General Call Address from a START byte which is
cleared to 0 for a General Call Address). For a General Call Address, the I2C controller
automatically responds during the address acknowledge phase with the value in the NAK
bit of the I2CCTL Register. If the software is set to process the data bytes associated with
the GCA bit, the IRM bit can optionally be set following the SAM interrupt to allow the software to examine each received data byte before deciding to set or clear the NAK bit.
A START byte will not be acknowledged—a requirement of the I2C specification.
Software Address Recognition. To disable hardware address recognition, the IRM bit
must be set to 1 prior to the reception of the address byte(s). When IRM = 1, each received
byte generates a receive interrupt (RDRF = 1 in the I2CISTAT Register). The software must
examine each byte and determine whether to set or clear the NAK bit. The slave holds SCL
Low during the Acknowledge phase until the software responds by writing to the I2CCTL
Register. The value written to the NAK bit is used by the controller to drive the I2C bus,
then releasing the SCL. The SAM and GCA bits are not set when IRM = 1 during the address
phase, but the RD bit is updated based on the first address byte.
Slave Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate data transferred from
the master to the slave, and the unshaded regions indicate the data transferred from the
slave to the master. The transaction field labels are defined as follows:
S
Start
W
Write
A
Acknowledge
A
Not Acknowledge
P
Stop
Slave Receive Transaction with 7-Bit Address
The data transfer format for writing data from a master to a slave in 7-bit address mode is
shown in Figure 32. The procedure that follows describes the I2C Master/Slave Controller
operating as a slave in 7-bit addressing mode and receiving data from the bus master.
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S
Slave Address
W=0
A
Data
A
Data
A
Data
A/A
P/S
Figure 32. Data Transfer Format—Slave Receive Transaction with 7-Bit Address
1. The software configures the controller for operation as a slave in 7-bit addressing
mode, as follows.
a. Initialize the MODE field in the I2C Mode Register for either SLAVE ONLY mode
or MASTER/SLAVE mode with 7-bit addressing.
b. Optionally set the GCE bit.
c. Initialize the SLA[6:0] bits in the I2C Slave Address Register.
d. Set IEN = 1 in the I2C Control Register. Set NAK = 0 in the I2C Control Register.
2. The bus master initiates a transfer, sending the address byte. In SLAVE mode, the I2C
controller recognizes its own address and detects that the R/W bit = 0 (written from
the master to the slave). The I2C controller acknowledges, indicating it is available to
accept the transaction. The SAM bit in the I2CISTAT Register is set to 1, causing an
interrupt. The RD bit in the I2CISTAT Register is cleared to 0, indicating a Write to the
slave. The I2C controller holds the SCL signal Low, waiting for the software to load
the first data byte.
3. The software responds to the interrupt by reading the I2CISTAT Register (which
clears the SAM bit). After seeing the SAM bit to 1, the software checks the RD bit.
Because RD = 0, no immediate action is required until the first byte of data is received.
If software is only able to accept a single byte it sets the NAK bit in the I2CCTL Register at this time.
4. The master detects the Acknowledge and sends the byte of data.
5. The I2C controller receives the data byte and responds with Acknowledge or Not
Acknowledge depending on the state of the NAK bit in the I2CCTL Register. The I2C
controller generates the receive data interrupt by setting the RDRF bit in the I2CISTAT
Register.
6. The software responds by reading the I2CISTAT Register, finding the RDRF bit = 1
and reading the I2CDATA Register clearing the RDRF bit. If software can accept only
one more data byte it sets the NAK bit in the I2CCTL Register.
7. The master and slave loops through steps 4 to 6 until the master detects a Not
Acknowledge instruction or runs out of data to send.
8. The master sends the STOP or RESTART signal on the bus. Either of these signals can
cause the I2C controller to assert a STOP interrupt (the STOP bit = 1 in the I2CISTAT
Register). Because the slave received data from the master, the software takes no
action in response to the STOP interrupt other than reading the I2CISTAT Register to
clear the STOP bit in the I2CISTAT Register.
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Slave Receive Transaction with 10-Bit Address
The data transfer format for writing data from a master to a slave with 10-bit addressing is
shown in Figure 33. The procedure that follows describes the I2C Master/Slave Controller
operating as a slave in 10-bit addressing mode and receiving data from the bus master.
s
S
Slave Address
1st Byte
W=0
A
Slave Address
2nd Byte
A
Data
A
Data
A/A
P/S
Figure 33. Data Transfer Format—Slave Receive Transaction with 10-Bit Address
1. The software configures the controller for operation as a slave in 10-bit addressing
mode, as follows.
a. Initialize the MODE field in the I2CMODE Register for either SLAVE ONLY
mode or MASTER/SLAVE mode with 10-bit addressing.
b. Optionally set the GCE bit.
c. Initialize the SLA[7:0] bits in the I2CSLVAD Register and the SLA[9:8] bits in
the I2CMODE Register.
d. Set IEN = 1 in the I2CCTL Register. Set NAK = 0 in the I2C Control Register.
2. The master initiates a transfer, sending the first address byte. The I2C controller recognizes the start of a 10-bit address with a match to SLA[9:8] and detects the R/W bit =
0 (a Write from the master to the slave). The I2C controller acknowledges, indicating
it is available to accept the transaction.
3. The master sends the second address byte. The SLAVE mode I2C controller detects an
address match between the second address byte and SLA[7:0]. The SAM bit in the
I2CISTAT Register is set to 1, thereby causing an interrupt. The RD bit is cleared to 0,
indicating a Write to the slave. The I2C controller acknowledges, indicating it is available to accept the data.
4. The software responds to the interrupt by reading the I2CISTAT Register, which clears
the SAM bit. Because RD = 0, no immediate action is taken by the software until the
first byte of data is received. If the software is only able to accept a single byte, it sets
the NAK bit in the I2CCTL Register.
5. The master detects the Acknowledge and sends the first byte of data.
6. The I2C controller receives the first byte and responds with Acknowledge or Not
Acknowledge, depending on the state of the NAK bit in the I2CCTL Register. The I2C
controller generates the receive data interrupt by setting the RDRF bit in the I2CISTAT
Register.
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7. The software responds by reading the I2CISTAT Register, finding the RDRF bit = 1,
and then reading the I2CDATA Register, which clears the RDRF bit. If the software can
accept only one more data byte, it sets the NAK bit in the I2CCTL Register.
8. The master and slave loops through steps 5 to 7 until the master detects a Not
Acknowledge instruction or runs out of data to send.
9. The master sends the STOP or RESTART signal on the bus. Either of these signals can
cause the I2C controller to assert the STOP interrupt (the STOP bit = 1 in the
I2CISTAT Register). Because the slave received data from the master, the software
takes no action in response to the STOP interrupt other than reading the I2CISTAT
Register to clear the STOP bit.
Slave Transmit Transaction with 7-bit Address
The data transfer format for a master reading data from a slave in 7-bit address mode is
shown in Figure 37. The procedure that follows describes the I2C Master/Slave Controller
operating as a slave in 7-bit addressing mode and transmitting data to the bus master.
S
Slave Address
R=1
A
Data
A
Data
A
P/S
Figure 34. Data Transfer Format—Slave Transmit Transaction with 7-bit Address
1. The software configures the controller for operation as a slave in 7-bit addressing
mode, as follows.
a. Initialize the MODE field in the I2C Mode Register for either SLAVE ONLY mode
or MASTER/SLAVE mode with 7-bit addressing.
b. Optionally set the GCE bit.
c. Initialize the SLA[6:0] bits in the I2C Slave Address Register.
d. Set IEN = 1 in the I2C Control Register. Set NAK = 0 in the I2C Control Register.
2. The master initiates a transfer, sending the address byte. The SLAVE mode I2C controller finds an address match and detects that the R/W bit = 1 (read by the master
from the slave). The I2C controller acknowledges, indicating that it is ready to accept
the transaction. The SAM bit in the I2CISTAT Register is set to 1, causing an interrupt.
The RD bit is set to 1, indicating a Read from the slave.
3. The software responds to the interrupt by reading the I2CISTAT Register, thereby
clearing the SAM bit. Because RD = 1, the software responds by loading the first data
byte into the I2CDATA Register. The software sets the TXI bit in the I2CCTL Register
to enable transmit interrupts. When the master initiates the data transfer, the I2C controller holds SCL Low until the software has written the first data byte to the
I2CDATA Register.
4. SCL is released and the first data byte is shifted out.
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5. After the first bit of the first data byte has been transferred, the I2C controller sets the
TDRE bit, which asserts the transmit data interrupt.
6. The software responds to the transmit data interrupt (TDRE = 1) by loading the next
data byte into the I2CDATA Register, which clears TDRE.
7. After the data byte has been received by the master, the master transmits an Acknowledge instruction (or Not Acknowledge instruction if this byte is the final data byte).
8. The bus cycles through steps 5 to 7 until the final byte has been transferred. If the software has not yet loaded the next data byte when the master brings SCL Low to transfer the most significant data bit, the slave I2C controller holds SCL Low until the data
register has been written. When a Not Acknowledge instruction is received by the
slave, the I2C controller sets the NCKI bit in the I2CISTAT Register, causing the Not
Acknowledge interrupt to be generated.
9. The software responds to the Not Acknowledge interrupt by clearing the TXI bit in the
I2CCTL Register and by asserting the FLUSH bit of the I2CCTL Register to empty the
data register.
10. When the master has completed the final acknowledge cycle, it asserts a STOP or
RESTART condition on the bus.
11. The slave I2C controller asserts the STOP/RESTART interrupt (set SPRS bit in
I2CISTAT Register).
12. The software responds to the STOP/RESTART interrupt by reading the I2CISTAT Register, which clears the SPRS bit.
Slave Transmit Transaction with 10-Bit Address
The data transfer format for a master reading data from a slave with 10-bit addressing is
shown in Figure 35. The following procedure describes the I2C Master/Slave Controller
operating as a slave in 10-bit addressing mode, transmitting data to the bus master.
S Slave Address W = 0 A Slave Address A
1st Byte
2nd Byte
S Slave Address R = 1 A
1st Byte
Data
A
Data
A
P
Figure 35. Data Transfer Format—Slave Transmit Transaction with 10-Bit Address
1. The software configures the controller for operation as a slave in 10-bit addressing
mode.
a. Initialize the MODE field in the I2C Mode Register for either SLAVE ONLY mode
or MASTER/SLAVE mode with 10-bit addressing.
b. Optionally set the GCE bit.
c. Initialize the SLA[7:0] bits in the I2CSLVAD Register and SLA[9:8] in the
I2CMODE Register.
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d. Set IEN = 1, NAK = 0 in the I2C Control Register.
2. The master initiates a transfer, sending the first address byte. The SLAVE mode I2C
controller recognizes the start of a 10-bit address with a match to SLA[9:8] and
detects the R/W bit = 0 (a Write from the master to the slave). The I2C controller
acknowledges, indicating it is available to accept the transaction.
3. The master sends the second address byte. The SLAVE mode I2C controller compares
the second address byte with the value in SLA[7:0]. If there is a match, the SAM bit in
the I2CISTAT Register is set = 1, causing a slave address match interrupt. The RD bit
is set = 0, indicating a write to the slave. If a match occurs, the I2C controller acknowledges on the I2C bus, indicating it is available to accept the data.
4. The software responds to the slave address match interrupt by reading the I2CISTAT
Register, which clears the SAM bit. Because the RD bit = 0, no further action is
required.
5. The master sees the Acknowledge and sends a RESTART instruction, followed by the
first address byte with the R/W set to 1. The SLAVE mode I2C controller recognizes
the RESTART instruction followed by the first address byte with a match to
SLA[9:8], and detects the R/W = 1 (the master reads from the slave). The slave I2C
controller sets the SAM bit in the I2CISTAT Register, which causes the slave address
match interrupt. The RD bit is set = 1. The SLAVE mode I2C controller acknowledges
on the bus.
6. The software responds to the interrupt by reading the I2CISTAT Register, clearing the
SAM bit. The software loads the initial data byte into the I2CDATA Register and sets
the TXI bit in the I2CCTL Register.
7. The master starts the data transfer by asserting SCL Low. After the I2C controller has
data available to transmit, the SCL is released, and the master proceeds to shift the
first data byte.
8. After the first bit of the first data byte has been transferred, the I2C controller sets the
TDRE bit which asserts the transmit data interrupt.
9. The software responds to the transmit data interrupt by loading the next data byte into
the I2CDATA Register.
10. The I2C master shifts in the remainder of the data byte. The master transmits the
Acknowledge (or Not Acknowledge, if this byte is the final data byte).
11. The bus cycles through steps 7 to 10 until the final byte has been transferred. If the
software has not yet loaded the next data byte when the master brings SCL Low to
transfer the most significant data bit, the slave I2C controller holds SCL Low until the
data register is written.
When a Not Acknowledge is received by the slave, the I2C controller sets the NCKI bit
in the I2CISTAT Register, causing the NAK interrupt to be generated.
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12. The software responds to the NAK interrupt by clearing the TXI bit in the I2CCTL
Register and by asserting the FLUSH bit of the I2CCTL Register.
13. When the master has completed the Acknowledge cycle of the last transfer, it asserts a
STOP or RESTART condition on the bus.
14. The slave I2C controller asserts the STOP/RESTART interrupt (sets the SPRS bit in the
I2CISTAT Register).
15. The software responds to the STOP interrupt by reading the I2CISTAT Register and
clearing the SPRS bit.
I2C Data Register
The I2C Data Register, shown in Table 92, contains the data that is to be loaded into the
Shift Register to transmit onto the I2C bus. This register also contains data that is loaded
from the Shift Register after it is received from the I2C bus. The I2C Shift Register is not
accessible in the Register File address space, but is used only to buffer incoming and outgoing data.
Writes by the software to the I2CDATA Register are blocked if a slave Write transaction is
underway (the I2C controller is in SLAVE mode, and data is being received).
Table 92. I2C Data Register (I2CDATA)
BITS
7
6
5
4
3
FIELD
DATA
RESET
0
R/W
R/W
ADDR
F50H
2
1
0
I2C Interrupt Status Register
The read-only I2C Interrupt Status Register, shown in Table 93, indicates the cause of any
current I2C interrupt and provides status of the I2C controller. When an interrupt occurs,
one or more of the TDRE, RDRF, SAM, ARBLST, SPRS or NCKI bits is set. The GCA and
RD bits do not generate an interrupt but rather provide status associated with the
SAM bit interrupt.
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Table 93. I2C Interrupt Status Register (I2CISTAT)
BITS
7
6
5
4
3
2
1
0
FIELD
TDRE
RDRF
SAM
GCA
RD
ARBLST
SPRS
NCKI
RESET
1
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
ADDR
F51H
TDRE—Transmit Data Register Empty
When the I2C Controller is enabled, this bit is 1 when the I2C Data register is empty.
When set, this bit causes the I2C Controller to generate an interrupt, except when the I2C
Controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit clears by writing to the I2CDATA register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I2C Controller is enabled and the I2C Controller has received a
byte of data. When asserted, this bit causes the I2C Controller to generate an interrupt.
This bit clears by reading the I2CDATA register.
SAM—Slave Address Match
This bit is set = 1 if the I2C Controller is enabled in Slave mode and an address is received
which matches the unique Slave address or General Call Address (if enabled by the GCE
bit in the I2C Mode register). In 10-bit addressing mode, this bit is not set until a match is
achieved on both address bytes. When this bit is set, the RD and GCA bits are also valid.
This bit clears by reading the I2CISTAT register.
GCA—General Call Address
This bit is set in Slave mode when the General Call Address or START byte is recognized
(in either 7 or 10 bit Slave mode). The GCE bit in the I2C Mode register must be set to
enable recognition of the General Call Address and START byte. This bit clears when IEN
= 0 and is updated following the first address byte of each Slave mode transaction. A General Call Address is distinguished from a START byte by the value of the RD bit (RD = 0
for General Call Address, 1 for START byte).
RD—Read
This bit indicates the direction of transfer of the data. It is set when the Master is reading
data from the Slave. This bit matches the least-significant bit of the address byte after the
START condition occurs (for both Master and Slave modes). This bit clears when IEN = 0
and is updated following the first address byte of each transaction.
ARBLST—Arbitration Lost
This bit is set when the I2C Controller is enabled in Master mode and loses arbitration
(outputs a 1 on SDA and receives a 0 on SDA). The ARBLST bit clears when the
I2CISTAT register is read.
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I2C Interrupt Status Register
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SPRS—Stop/Restart Condition Interrupt
This bit is set when the I2C Controller is enabled in Slave mode and detects a STOP or
RESTART condition during a transaction directed to this slave. This bit clears when the
I2CISTAT register is read. Read the RSTR bit of the I2CSTATE register to determine
whether the interrupt was caused by a STOP or RESTART condition.
NCKI—NAK Interrupt
In Master mode, this bit is set when a Not Acknowledge condition is received or sent and
neither the START nor the STOP bit is active. In Master mode, this bit can only be cleared
by setting the START or STOP bits.
In Slave mode, this bit is set when a Not Acknowledge condition is received (Master reading data from Slave), indicating the Master is finished reading. A STOP or RESTART condition follows. In Slave mode this bit clears when the I2CISTAT register is read.
I2C Control Register
The I2C Control Register, shown in Table 94, enables and configures I2C operation.
Table 94. I2C Control Register (I2CCTL)
BITS
7
6
5
4
3
2
1
0
FIELD
IEN
START
STOP
BIRQ
TXI
NAK
FLUSH
FILTEN
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W1
R/W1
R/W
R/W
R/W1
R/W
R/W
F52H
ADDR
NOTE: R/W1 - bit may be set (write 1) but not cleared.
IEN—I2C Enable
This bit enables the I2C Controller.
START—Send Start Condition
When set, this bit causes the I2C Controller (when configured as the Master) to send the
Start condition. Once asserted, it is cleared by the I2C Controller after it sends the Start
condition or by deasserting the IEN bit. If this bit is 1, it cannot be cleared by writing to
the bit. After this bit is set, the START condition is sent if there is data in the I2CDATA or
I2CSHIFT register. If there is no data in one of these registers, the I2C Controller waits
until data is loaded. If this bit is set while the I2C Controller is shifting out data, it generates a RESTART condition after the byte shifts and the acknowledge phase completes. If
the STOP bit is also set, it also waits until the STOP condition is sent before the START
condition.
If START is set while a slave mode transaction is underway to this device, the START bit
will be cleared and ARBLST bit in the Interrupt Status register will be set.
I2C Master/Slave Controller
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STOP—Send Stop Condition
When set, this bit causes the I2C Controller (when configured as the Master) to send the
STOP condition after the byte in the I2C Shift register has completed transmission or after
a byte has been received in a receive operation. When set, this bit is reset by the I2C Controller after a STOP condition has been sent or by deasserting the IEN bit. If this bit is 1, it
cannot be cleared to 0 by writing to the register.
If STOP is set while a slave mode transaction is underway, the STOP bit will be cleared by
hardware.
BIRQ—Baud Rate Generator Interrupt Request
This bit is ignored when the I2C Controller is enabled. If this bit is set = 1 when the I2C
Controller is disabled (IEN = 0) the baud rate generator is used as an additional timer causing an interrupt to occur every time the baud rate generator counts down to one. The baud
rate generator runs continuously in this mode, generating periodic interrupts.
TXI—Enable TDRE interrupts
This bit enables interrupts when the I2C Data register is empty.
NAK—Send NAK
Setting this bit sends a Not Acknowledge condition after the next byte of data has been
received. It is automatically deasserted after the Not Acknowledge is sent or the IEN bit is
cleared. If this bit is 1, it cannot be cleared to 0 by writing to the register.
FLUSH—Flush Data
Setting this bit clears the I2C Data register and sets the TDRE bit to 1. This bit allows flushing of the I2C Data register when an NAK condition is received after the next data byte
has been written to the I2C Data register. Reading this bit always returns 0.
FILTEN—I2C Signal Filter Enable
Setting this bit enables low-pass digital filters on the SDA and SCL input signals. This
function provides the spike suppression filter required in I2C Fast Mode. These filters
reject any input pulse with periods less than a full system clock cycle. The filters introduce
a 3-system clock cycle latency on the inputs.
I2C Baud Rate High and Low Byte Registers
The I2C Baud Rate High and Low Byte registers, shown in Tables 95 and 96, combine to
form a 16-bit reload value, BRG[15:0], for the I2C Baud Rate Generator. The I2C baud rate
is calculated using the following equation.
Note: If BRG = 0000h, use 10000h in the equation):
I2C Baud Rate (bits/s)
PS024604-1005
=
System Clock Frequency (Hz)
4 x BRG[15:0]
PRELIMINARY
I2C Baud Rate High and Low Byte Registers
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.
Table 95. I2C Baud Rate High Byte Register (I2CBRH)
BITS
7
6
5
4
3
FIELD
BRH
RESET
FFH
R/W
R/W
ADDR
F53H
2
1
0
BRH = I2C Baud Rate High Byte
Most significant byte, BRG[15:8], of the I2C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I2C Mode Register is set to 1, a read of the I2CBRH register returns
the current value of the I2C Baud Rate Counter[15:8].
Table 96. I2C Baud Rate Low Byte Register (I2CBRL)
BITS
7
6
5
4
3
FIELD
BRL
RESET
FFH
R/W
R/W
ADDR
F54H
2
1
0
BRL = I2C Baud Rate Low Byte
Least significant byte, BRG[7:0], of the I2C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I2C Mode Register is set to 1, a read of the I2CBRL register returns
the current value of the I2C Baud Rate Counter[7:0]
I2C State Register
The read-only I2C State Register provides information about the state of the I2C bus and
the I2C bus controller.
When the DIAG bit of the I2C Mode Register is cleared, this register provides information
on the internal state of the I2C controller and I2C bus, as shown in Table 97. A more
detailed discussion of each bit follows this table.
When the DIAG bit of the I2C Mode Register is set, this register returns the value of the
I2C controller state machine, as shown in Table 98, which follows on page 190.
I2C Master/Slave Controller
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Table 97. I2C State Register (I2CSTATE) - Description when DIAG = 0
BITS
7
6
5
4
3
2
1
0
FIELD
ACKV
ACK
AS
DS
10B
RSTR
SCLOUT
BUSY
RESET
0
0
0
0
0
0
X
X
R/W
R
R
R
R
R
R
R
R
ADDR
F55H
ACKV—ACK Valid
This bit is set if sending data (Master or Slave) and the ACK bit in this register is valid for
the byte just transmitted. This bit can be monitored if it is appropriate for software to verify the ACK value before writing the next byte to be sent. To operate in this mode, the data
register must not be written when TDRE asserts; instead, software waits for ACKV to assert.
This bit clears when transmission of the next byte begins or the transaction is ended by a
STOP or RESTART condition.
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
This bit is set for an Acknowledge and cleared for a Not Acknowledge condition.
AS—Address State
This bit is active High while the address is being transferred on the I2C bus.
DS—Data State
This bit is active high while the data is being transferred on the I2C bus.
10B—This bit indicates whether a 10 or 7-bit address is being transmitted when operating
as a Master. After the START bit is set, if the five most-significant bits of the address are
11110B, this bit is set. When set, it is reset once the address has been sent.
RSTR—RESTART
This bit is updated each time a STOP or RESTART interrupt occurs (SPRS bit set in
I2CISTAT register).
0 = Stop condition
1 = Restart condition
SCLOUT—Serial Clock Output
Current value of Serial Clock being output onto the bus. The actual values of the SCL and
SDA signals on the I2C bus can be observed via the GPIO Input register.
BUSY—I2C Bus Busy
0 = No activity on the I2C Bus.
1 = A transaction is underway on the I2C bus.
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I2C State Register
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Table 98. I2C State Register (I2CSTATE) - Description when DIAG = 1
BITS
7
6
5
4
3
I2CSTATE_H
FIELD
2
1
0
I2CSTATE_L
RESET
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
F55H
ADDR
I2CSTATE_H—I2C State
This field defines the current state of the I2C Controller. It is the most significant nibble of
the internal state machine. Table 99 defines the states for this field.
I2CSTATE_L—Least significant nibble of the I2C state machine. This field defines the
substates for the states defined by I2CSTATE_H. Table 100 defines the values for this
field.
Table 99. I2CSTATE_H
State
Encoding
State Name
State Description
0000
Idle
I2C bus is idle or I2C controller is disabled.
0001
Slave Start
I2C controller has received a START condition.
0010
Slave Bystander
Address did not match; ignore remainder of transaction.
0011
Slave Wait
Waiting for STOP or RESTART condition after sending a Not
Acknowledge instruction.
0100
Master Stop2
Master completing STOP condition (SCL = 1, SDA = 1).
0101
Master Start/Restart
MASTER mode sending START condition (SCL = 1, SDA = 0).
0110
Master Stop1
Master initiating STOP condition (SCL = 1, SDA = 0).
0111
Master Wait
Master received a Not Acknowledge instruction, waiting for
software to assert STOP or START control bits.
1000
Slave Transmit Data
9 substates, one for each data bit and one for the Acknowledge.
1001
Slave Receive Data
9 substates, one for each data bit and one for the Acknowledge.
1010
Slave Receive Addr1
Slave receiving first address byte (7- and 10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
1011
Slave Receive Addr2
Slave Receiving second address byte (10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
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Table 99. I2CSTATE_H (Continued)
State
Encoding
State Name
State Description
1100
Master Transmit Data
9 substates, one for each data bit and one for the Acknowledge.
1101
Master Receive Data
9 substates, one for each data bit and one for the Acknowledge.
1110
Master Transmit Addr1 Master sending first address byte (7- and 10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
1111
Master Transmit Addr2 Master sending second address byte (10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
Table 100. I2CSTATE_L
State
Substate
I2CSTATE_H I2CSTATE_L
Substate Name
State Description
0000–0100
0000
—
There are no substates for these I2CSTATE_H
values.
0110–0111
0000
—
There are no substates for these I2CSTATE_H
values.
0101
0000
Master Start
Initiating a new transaction
0001
Master Restart
Master is ending one transaction and starting a
new one without letting the bus go idle.
0111
send/receive bit 7
Sending/Receiving most significant bit
0110
send/receive bit 6
0101
send/receive bit 5
0100
send/receive bit 4
0011
send/receive bit 3
0010
send/receive bit 2
0001
send/receive bit 1
0000
send/receive bit 0
Sending/Receiving least significant bit
1000
send/receive
Acknowledge
Sending/Receiving Acknowledge
1000–1111
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I2C Mode Register
The I2C Mode Register, Table 101, provides control over master versus slave operating
mode, slave address and diagnostic modes.
Table 101. I2C Mode Register (I2CMODE)
BITS
7
FIELD
Reserved
RESET
R/W
6
5
4
3
2
1
0
MODE[1:0]
IRM
GCE
SLA[9:8]
DIAG
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
F56H
ADDR
MODE—Selects the I2C Controller operational mode
00 = Master/Slave capable (supports multi-Master arbitration) with 7-bit Slave address
01 = Master/Slave capable (supports multi-Master arbitration) with 10-bit Slave address
10 = Slave Only capable with 7-bit address
11 = Slave Only capable with 10-bit address
IRM—Interactive Receive Mode
Valid in Slave mode when software needs to interpret each received byte before acknowledging. This bit is useful for processing the data bytes following a General Call Address or
if software wants to disable hardware address recognition.
0 = Acknowledge occurs automatically and is determined by the value of the NAK bit of
the I2CCTL register.
1 = A receive interrupt is generated for each byte received (address or data). The SCL is
held Low during the acknowledge cycle until software writes to the I2CCTL register. The
value written to the NAK bit of the I2CCTL register is output on SDA. This value allows
software to Acknowledge or Not Acknowledge after interpreting the associated address/
data byte.
GCE—General Call Address Enable
Enables reception of messages beginning with the General Call Address or START byte.
0 = Do not accept a message with the General Call Address or START byte.
1 = Do accept a message with the General Call Address or START byte. When an address
match occurs, the GCA and RD bits in the I2C Status register indicates whether the
address matched the General Call Address/START byte or not. Following the General Call
Address byte, software may set the IRM bit that allows software to examine the following
data byte(s) before acknowledging.
SLA[9:8]— Slave Address Bits 9 and 8.
Initialize with the appropriate Slave address value when using 10-bit Slave addressing.
These bits are ignored when using 7-bit Slave addressing.
DIAG—Diagnostic Mode
Selects read back value of the Baud Rate Reload and State registers.
I2C Master/Slave Controller
PRELIMINARY
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0 = Reading the Baud Rate registers returns the Baud Rate register values. Reading the
State register returns I2C Controller state information
1 = Reading the Baud Rate registers returns the current value of the baud rate counter.
Reading the State register returns additional state information.
I2C Slave Address Register
The I2C Slave Address Register, shown in Table 102, provides control over the lower
order address bits used in 7 and 10 bit slave address recognition.
Table 102. I2C Slave Address Register (I2CSLVAD)
BITS
7
6
5
4
3
FIELD
SLA[7:0]
RESET
00H
R/W
R/W
ADDR
F57H
2
1
0
SLA[7:0] - Slave Address Bits 7-0. Initialize with the appropriate Slave address value.
When using 7 bit Slave addressing, SLA[9:7] are ignored.
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PRELIMINARY
I2C Slave Address Register
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194
I2C Master/Slave Controller
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Comparator and Operational Amplifier
The Z8FMC16100 Series Flash MCU devices feature a general-purpose comparator and
an operational amplifier. The comparator is a moderate speed (200 ns propagation delay)
device that is designed for a maximum input offset of 5 mV. The comparator can be used to
compare two analog input signals. General-purpose input pins (CINP and CINN) provide
the comparator inputs. The output is available as an interrupt source.
The operational amplifier is a two-input, one-output operational amplifier with a typical
open loop gain of 10,000 (80 dB). One general-purpose input pin, OPINP, provides a noninverting amplifier input, while another general-purpose input pin, OPINN, provides the
inverting amplifier input. The output is available at the output pin, OPOUT.
The key operating characteristics of the operational amplifier are:
•
•
•
•
•
•
Frequency compensated for unity gain stability
Input common-mode range from GND (0.0 V) to VDD – 1 V
Input offset voltage less than 15 mV
Output voltage swing from GND + 0.1 V to VDD – 0.1 V
Input bias current less than 1 nA
Operating the operational amplifier open loop (no feedback) effectively provides another on-chip comparator, if appropriate
Comparator Operation
The comparator output reflects the relationship between the noninverting input and the
inverting (reference) input. If the voltage on the noninverting input is higher than the voltage on the inverting input, the comparator output is at a high state. If the voltage on the
noninverting input is lower than the voltage on the inverting input, the comparator output
is at a low state.
To operate, the comparator must be enabled by setting the CMPEN bit in the Comparator
and Op Amp Register to 1. In addition the CINP and CINN comparator input alternate
functions must be enabled on their respective general-purpose I/O pins. Refer to the GPIO
Alternate Functions section on page 36 for more information.
The comparator does not automatically power-down. To reduce operating current when
not in use, the comparator may be disabled by clearing the CMPEN bit to 0.
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Comparator Operation
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Operational Amplifier Operation
To operate, the operational amplifier must be enabled by setting the OPEN bit in the Comparator and Op Amp Register to 1. In addition, the OPINP, OPINN, and OPOUT alternate
functions must be enabled on their respective general-purpose I/O pins. Refer to the GPIO
Alternate Functions section on page 36 for more information.
The logical value of the operational amplifier output (OPOUT) can be read from the Port 3
data input register if both the operational amplifier and input pin Schmitt trigger are
enabled. Refer to the GPIO Alternate Functions section on page 36 for more information.
The operational amplifier can also generate an interrupt via the GPIO Port B3 input interrupt, if enabled.
The output of the operational amplifier is also connected to an analog input (ANA3) of the
Analog-to-Digital Converter (ADC) multiplexer.
The operational amplifier does not automatically power-down. To reduce operating current when not in use, the operational amplifier may be disabled by clearing the OPEN bit in
the Comparator and Op Amp Register to 0.
When the operational amplifier is disabled, the output is high impedance.
Interrupts
The comparator will generate an interrupt on any change in the logic output value (from 0
to 1 and from 1 to 0). Refer to the Interrupt Controller chapter on page 51 for information
about enabling and prioritization of the comparator interrupt.
Comparator and Operational Amplifier
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Comparator and Op Amp Control Register
The Comparator and Op Amp Control (CMPOPC) Register, shown in Table 103, enables
the comparator and operational amplifier and provides access to the comparator output.
Table 103. Comparator and Op Amp Control Register (CMPOPC)
BITS
7
6
5
4
3
2
1
0
FIELD
OPEN
Reserved
CPSEL
CMPIRQ
CMPIV
CMPOUT
CMPEN
RESET
0
00
0
0
0
X
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
F90H
ADDR
Bit
Position
Value
(H)
[7]
OPEN
0
Operational Amplifier Disable
Operational amplifier is disabled.
1
Operational amplifier is enabled.
[6:5]
Reserved
[3]
CPSEL
[3]
CMPIRQ
[2]
CMPIV
[1]
CMPOUT
[0]
CMPEN
Description
Must be 0.
0
Comparator Input Select
Comparator input is PA1
1
Comparator input is PB4
0
Comparator Interrupt Edge Select
Interrupt Request on Comparator Rising Edge
1
Interrupt Request on Comparator Falling Edge
0
PWM Fault Comparator Polarity
PWM Fault is active when cp+ > cp-
1
PWM Fault is active when cp- > cp+
0
Comparator Output Value
Comparator output is logical 0.
1
Comparator output is logical 1.
0
Comparator Enable
Comparator is disabled.
1
Comparator is enabled.
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Comparator and Operational Amplifier
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Analog-to-Digital Converter
The Z8FMC16100 Series Flash MCU includes an eight-channel analog-to-digital converter (ADC). The ADC converts an analog input signal to a 10-bit binary number. The
features of the successive-approximation ADC include:
•
•
•
•
•
•
•
•
Eight analog input sources multiplexed with general-purpose I/O ports
Fast conversion time, less than 5 µs
Programmable timing controls
Interrupt upon conversion complete
Internal voltage reference generator
Internal reference voltage available externally
Ability to supply external reference voltage
Timer count capture on every ADC conversion
Architecture
The ADC architecture, as shown in Figure 36, consists of an 8-input multiplexer, sampleand-hold amplifier, and 10-bit successive-approximation analog-to-digital converter. The
ADC digitizes the signal on a selected channel and stores the digitized data in the ADC
data registers. In environments with high electrical noise, an external RC filter must be
added at the input pins to reduce high-frequency noise.
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Architecture
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REFEN
Internal Voltage
Reference Generator
VR2
VREF
RBUF
Analog-to-Digital
Converter
Data
Output
10
ANA0
ANA1
Reference Input
ANA2
ANA3
BUSY
Analog Input
Sample-and-Hold
Amplifier
ANA4
ANA5
ANA6
ANA7
ADCLK
ADCEN
ANAIN[2:0]
START
SAMPLE/HOLD
Figure 36. Analog-to-Digital Converter Block Diagram
Operation
The ADC converts the analog input, ANAX, to a 10-bit digital representation. The equation for calculating the digital value is represented by:
ADC Output = 1024 x (ANAx ÷ VREF)
Assuming zero gain and offset errors, any voltage outside the ADC input limits of AVSS
and VREF returns all 0s or 1s, respectively.
A new conversion can be initiated by either software write to the ADC Control Register’s
START bit or by PWM trigger. Refer to the Synchronization of PWM and Analog-to-Digi-
tal Converter section on page 73 for information about the PWM trigger.
Analog-to-Digital Converter
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To avoid disrupting a conversion already in progress, the START bit can be read to indicate
ADC operation status (busy or available).
Caution: Starting a new conversion while another conversion is in progress will stop the conversion in progress and the new conversion will not complete.
ADC Timing
Each ADC measurement consists of 3 phases:
1. Input sampling (programmable, minimum of 1.0 µs)
2. Sample-and-hold amplifier settling (programmable, minimum of 0.5 µs)
3. Conversion is 13 ADCLK cycles.
Figure 37 illustrates the control and flow of an ADC conversion.
Conversion period
START bit
Cleared by BUSY
Set by user
1.0 s sample period
SAMPLE/HOLD
Internal signal
Programmable
settling period
BUSY
Internal signal
13-clock
Conversion period
Figure 37. ADC Timing Diagram
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1
2
3
4
5
6
7
8
9
10
Store in Register
Convertbit 0
Convertbit 1
Convertbit 2
Convertbit 3
Convertbit 4
Convertbit 5
Convertbit 6
Convertbit 7
Convertbit 8
Convert msb
Figure 38 illustrates the timing of an ADC convert period.
11
12
13
14
15
16
17
ADC Clock
13-Clock
Convert Period
BUSY
Figure 38. ADC Convert Timing
ADC Interrupt
The ADC can generate an interrupt request when a conversion has been completed. An
interrupt request that is pending when the ADC is disabled is not automatically cleared.
ADC Timer 0 Capture
The Timer 0 count is captured for every ADC conversion. The capture of the Timer 0
count occurs after the programmed sample time is complete for every conversion and
stored in the ADC Timer Capture Register (ADCTCAP).
Reference Buffer
The reference buffer, RBUF, supplies the reference voltage for the ADC. When enabled,
the internal voltage reference generator supplies the ADC and the voltage is available on
the VREF pin. When RBUF is disabled, the ADC must have the reference voltage supplied
externally through the VREF pin. RBUF is controlled by the REFEN bit in the ADC Control
Register.
Internal Voltage Reference Generator
The Internal Voltage Reference Generator provides the voltage, VR2, for the RBUF. VR2
is 2 volts.
Analog-to-Digital Converter
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203
Calibration and Compensation
A user can perform calibration and store the values into Flash, or the user code can perform a manual offset calibration. There is no provision for manual gain calibration.
ADC Control Register 0
The ADC Control Register 0 initiates the A/D conversion and provides ADC status information. See Table 104.
Table 104. ADC Control Register 0 (ADCCT0)
BITS
7
6
5
4
3
FIELD
START
Reserved
REFEN
ADCEN
Reserved
RESET
0
0
0
0
0
0
0
0
R/W1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
1
0
ANAIN[2:0]
F70H
ADDR
Bit
Position
Value
(H)
[7]
START
0
Description
ADC Start / Busy
Writing to 0 has no effect.
Reading a 0 indicates the ADC is available to begin a conversion.
1
Writing to 1 starts a conversion.
Reading a 1 indicates a conversion is currently in progress.
[6]
0
Reserved—Must Be 0.
[5]
REFEN
0
Reference Enable
Internal reference voltage is disabled allowing an external reference voltage to be
used by the ADC.
1
[4]
ADCEN
[3]
Reserved
Internal reference voltage for the ADC is enabled. The internal reference voltage
can be measured on the VREF pin.
0
ADC Enable
ADC is disabled for low power operation.
1
ADC is enabled for normal use.
Reserved—Must Be 0.
0
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Calibration and Compensation
Z8 Encore!® Motor Control Flash MCUs
Product Specification
204
[2:0]
ANAIN
000
Analog Input Select
ANA0 input is selected for analog to digital conversion.
001
ANA1 input is selected for analog to digital conversion.
010
ANA2 input is selected for analog to digital conversion.
011
ANA3 input is selected for analog to digital conversion.
100
ANA4 input is selected for analog to digital conversion.
101
ANA5 input is selected for analog to digital conversion.
110
ANA6 input is selected for analog to digital conversion.
111
ANA7 input is selected for analog to digital conversion.
ADC Raw Data High Byte Register
The ADC Data Raw High Byte Register, shown in Table 105, contains the upper eight bits
of raw data from the ADC output. Access to the ADC Raw Data High Byte register is
Read-Only. This register is used for test only.
Table 105. ADC Raw Data High Byte Register (ADCRD_H)
BITS
7
6
5
4
3
FIELD
ADCRDH
RESET
X
R/W
R
2
1
0
F71H
ADDR
Bit
Position
Value
(H)
Description
[7:0]
00H–FFH ADC Raw Data High Byte
The data in this register is the raw data coming from the SAR Block. It will change
as the conversion is in progress. This register is used for testing only.
ADC Data High Byte Register
The ADC Data High Byte Register, shown in Table 106, contains the upper eight bits of
the ADC output. Access to the ADC Data High Byte Register is Read-Only. Reading the
ADC Data High Byte Register latches data in the ADC Low Bits Register.
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Table 106. ADC Data High Byte Register (ADCD_H)
BITS
7
6
5
4
3
FIELD
ADCDH
RESET
X
R/W
R
2
1
0
F72H
ADDR
Bit
Position
Value
(H)
Description
[7:0]
00H–FFH ADC High Byte
The last conversion output is held in the data registers until the next ADC
conversion has completed.
ADC Data Low Bits Register
The ADC Data Low Bits Register, shown in Table 107, contain the lower bits of the ADC
output as well as an overflow status bit. Access to the ADC Data Low Bits Register is ReadOnly. Reading the ADC Data High Byte Register latches data in the ADC Low Bits Register.
Table 107. ADC Data Low Bits Register (ADCD_L)
BITS
7
6
5
4
3
2
FIELD
ADCDL
Reserved
RESET
X
X
R/W
R
R
Value
(H)
[7:6]
00–11b
[5:0]
Reserved
0
F73H
ADDR
Bit
Position
1
Description
ADC Low Bits
These bits are the 2 least significant bits of the 10-bit ADC output. These bits are
undefined after a Reset. The low bits are latched into this register whenever the
ADC Data High Byte register is read.
Reserved—Must Be 0.
0
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ADC Data Low Bits Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
206
Sample Settling Time Register
The Sample Settling Time Register, shown in Table 108, is used to program the length of
time from the SAMPLE/HOLD signal to the START signal, when the conversion can
begin. The number of clock cycles required for settling will vary from system to system
depending on the system clock period used. The system designer should program this register to contain the number of clocks required to meet a 0.5 µs minimum settling time.
Table 108. Sample and Settling Time (ADCSST)
BITS
7
6
FIELD
Reserved
RESET
0
R/W
R
5
4
3
2
1
0
1
1
SST
1
1
1
R/W
F74H
ADDR
Bit
Position
Value
(H)
Description
[7:5]
0H
Reserved - Must be 0.
[4:0]
SST
0H - FH
Sample settling time in number of system clock periods to meet 0.5 µS minimum.
Sample Time Register
The Sample Time Register, shown in Table 109, is used to program the length of active
time for the sample after a conversion has begun by setting the START bit in the ADC
Control Register or initiated by the PWM. The number of system clock cycles required for
sample time varies from system to system, depending on the clock period used. The system designer should program this register to contain the number of system clocks required
to meet a 1 µs minimum sample time.
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Table 109. Sample Hold Time (ADCST)
BITS
7
6
FIELD
Reserved
RESET
0
5
4
3
1
0
1
1
1
ST
1
1
1
R/W
R/W
2
R/W
F75H
ADDR
Bit
Position
Value
(H)
Description
[7:6]
0H
Reserved - Must be 0.
[5:0]
SHT
0H - FH
Sample Hold time in number of system clock periods to meet 1 µS minimum.
ADC Clock Prescale Register
The ADC Clock Prescale Register, shown in Table 110, is used to provide a divided system clock to the ADC. When this register is programmed with 0h, the System Clock is
used for the ADC Clock.
Table 110. ADC Clock Prescale Register (ADCCP)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
DIV16
DIV8
DIV4
DIV2
RESET
0
0
0
0
0
R/W
R/W
ADDR
F76H
Bit
Position
Value
(H)
[0]
DIV2
0
DIV2
Clock is not divided
1
System Clock is divided by 2 for ADC Clock
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Description
PRELIMINARY
ADC Clock Prescale Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
208
[1]
DIV4
[2]
DIV8
[3]
DIV16
[7:4]
0
DIV4
Clock is not divided
1
System Clock is divided by 4 for ADC Clock
0
DIV8
Clock is not divided
1
System Clock is divided by 8 for ADC Clock
0
DIV16
Clock is not divided
1
System Clock is divided by 16 for ADC Clock
0H
Reserved - must be 0.
ADC Timer Capture High Byte Register
The high byte of the ADC Timer Capture Register, shown in Table 111, contains the upper
eight bits of the ADC Timer 0 count. Access to the ADC Timer Capture High Byte Register is Read-Only.
Table 111. ADC Timer Capture High Byte Register (ADCTCAP_H)
BITS
7
6
5
4
3
FIELD
ADCTCAPH
RESET
X
R/W
R
2
1
0
F08H
ADDR
Bit
Position
Value
(H)
Description
[7:0]
00H–FFH ADC Timer Capture Count High Byte
The timer count is held in the data registers until the next ADC conversion is
started.
ADC Timer Capture Low Byte Register
The low byte of the ADC Timer Capture Register, shown in Table 112, contains the lower
eight bits of the ADC Timer 0 count. Access to the ADC Timer Capture Low Byte Register is Read-Only.
Analog-to-Digital Converter
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209
Table 112. ADC Timer Capture Low Byte Register (ADCTCAP_L)
BITS
7
6
5
4
3
FIELD
ADCTCAPL
RESET
X
R/W
R
2
1
0
F09H
ADDR
Bit
Position
Value
(H)
[7:0]
00H–FFH ADC Timer Capture Count Low Byte
The timer count is held in the data registers until the next ADC conversion is
started.
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Description
PRELIMINARY
ADC Timer Capture Low Byte Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
210
Analog-to-Digital Converter
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Program Memory
The Z8FMC16100 Series Flash MCU products feature up to 16 KB (16,384 bytes) of nonvolatile Flash memory with read/write/erase capability. Flash memory can be programmed
and erased in-circuit by either user code or through the On-Chip Debugger.
The Flash memory array is arranged in 512-byte pages. The 512-byte page is the minimum Flash block size that can be erased. Flash memory is also divided into 8 sectors
which can be protected from programming and erase operations on a per sector basis.
Table 113 describes the Flash memory configuration for each device in the Z8FMC16100
Series Flash MCU. Table 114 lists the sector address ranges. Figure 39 illustrates the Flash
memory arrangement.
Table 113. Flash Memory Configurations
Part
Number
Flash Size
Number of
Pages
Program Memory
Addresses
Sector Size
Number of
Sectors
Pages per
Sector
Z8FMC16
16K (16,384)
32
0000h–3FFFh
2K (2048)
8
4
Z8FMC08
8K (8,192)
16
0000h–1FFFh
1K (1024)
8
2
Z8FMC04
4K (4,096)
8
0000h–0FFFh
512
8
1
Table 114. Flash Memory Sector Addresses
Flash Sector Address Ranges
PS024604-1005
Sector Number
Z8FMC16
Z8FMC08
Z8FMC04
0
0000h–07FFh
0000h–03FFh
0000h–01FFh
1
0800h–0FFFh
0400h–07FFh
0200h–03FFh
2
1000h–17FFh
0800h–0BFFh
0400h–05FFh
3
1800h–1FFFh
0C00h–0FFFh
0600h–07FFh
4
2000h–27FFh
1000h–13FFh
0800h–09FFh
5
2800h–2FFFh
1400h–17FFh
0A00h–0BFFh
6
3000h–37FFh
1800h–1BFFh
0C00h–0DFFh
7
3800h–3FFFh
1C00h–1FFFh
0E00h–0FFFh
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Product Specification
212
16KB Flash
Program Memory
3FFFh
3E00h
3DFFh
3C00h
3BFFh
3A00h
32 Pages
512 Bytes per Page
05FFh
0400h
03FFh
0200h
01FFh
0000h
Figure 39. Flash Memory Arrangement
Information Area
Table 115 describes the Z8FMC16100 Series Flash MCU’s information area. This 512byte information area is accessed by setting bit 7 of the Page Select Register to 1. When
access is enabled, the information area is mapped into Program Memory and overlays the
512 bytes at addresses FE00h to FFFFh. When information area access is enabled, LDC
instructions return data from the information area. CPU instruction fetches always arrive
from Program Memory regardless of the information area access bit. Access to the information area is Read-Only.
Program Memory
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Table 115. Z8FMC16100 Series Flash MCU Information Area Map
Program Memory
Address (Hex)
Function
FE00h–FE3Fh
Reserved.
FE40h–FE53h
Part Number:20-character ASCII alphanumeric
code, left-justified and filled with zeroes.
FE54h–FFFFh
Reserved.
Operation
The Flash Controller provides the proper signals and timing for the Byte Programming,
Page Erase, and Mass Erase operations in Flash memory. The Flash Controller contains a
protection mechanism, via the Flash Control Register (FCTL), to prevent accidental programming or erasure. The following subsections provide details about the Lock, Unlock,
Sector Protect, Byte Programming, Page Erase, and Mass Erase operations.
Timing Using the Flash Frequency Registers
Before performing a program or erase operation on Flash memory, the user must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency registers
allow programming and erasure of Flash with system clock frequencies ranging from
32 KHz through 20 MHz (the valid range is limited to device operating frequencies).
The Flash Frequency High and Low Byte registers combine to form a 16-bit value,
FFREQ, to control the timing of Flash program and erase operations. The 16-bit Flash Frequency value must contain the system clock frequency in kilohertz. This value is calculated using the following equation:
FFREQ[15:0] =
System Clock Frequency (Hz)
1000
Caution: Flash programming and erasure are not supported for system clock frequencies below
32 KHz, above 20 MHz, or outside of the device’s operating frequency range. The Flash
Frequency High and Low Byte registers must be loaded with the correct value to ensure
proper Flash programming and erase operations.
Flash Read Protection
The user code contained within Flash memory can be protected from external access. Programming the Flash Read Protect option bit prevents the reading of user code by the On-
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Operation
Z8 Encore!® Motor Control Flash MCUs
Product Specification
214
Chip Debugger or by using the Flash Controller Bypass mode. Refer to the Option Bits
chapter on page 223 and the On-Chip Debugger chapter on page 241 for more information.
Flash Write/Erase Protection
The Z8FMC16100 Series Flash MCU device provides several levels of protection against
accidental program and erasure of the contents of Flash memory. This protection is provided by the Flash Controller unlock mechanism, the Flash Sector Protect Register, and
the Flash Write Protect option bit.
Flash Controller Unlock Mechanism
At Reset, the Flash Controller locks to prevent accidental program or erasure of Flash
memory. To program or erase Flash memory, the Flash Controller must be unlocked. After
unlocking the Flash Controller, the Flash can be programmed or erased. Any value written
by user code to the Flash Control Register or Page Select Register out of sequence will
lock the Flash Controller.
The proper steps to unlock the Flash Controller from user code are:
1. Write 00h to the Flash Control Register to reset the Flash Controller.
2. Write the page to be programmed or erased to the Page Select Register.
3. Write the first unlock command 73h to the Flash Control Register.
4. Write the second unlock command 8Ch to the Flash Control Register.
5. Rewrite the page written in Step 2 to the Page Select Register.
Flash Sector Protection
The Flash Sector Protect Register can be configured to prevent sectors from being programmed or erased. After a sector is protected, it cannot be unprotected by user code. The
Flash Sector Protect Register is cleared after reset and any previously written protection
values are lost. User code must write this register in their initialization routine if they want
to enable sector protection.
The Flash Sector Protect Register shares its Register File address with the Page Select
Register. The Flash Sector Protect Register is accessed by writing the Flash Control Register with 5EH. After the Flash Sector Protect Register is selected, it can be accessed at the
Page Select Register address. When user code writes the Flash Sector Protect Register,
bits can only be set to 1. Therefore, sectors can be protected, but not unprotected, via register Write operations. The Flash Sector Protect Register is deselected by writing any
value to the Flash Control Register.
The steps to setup the Flash Sector Protect Register from user code are:
1. Write 00h to the Flash Control Register to reset the Flash Controller.
Program Memory
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2. Write 5Eh to the Flash Control Register to select the Flash Sector Protect Register.
3. Read and/or write the Flash Sector Protect Register, which now resides at Register
File address FF9h.
4. Write 00h to the Flash Control Register to return the Flash Controller to its reset state.
Flash Write Protection Option Bit
The Flash Write Protect option bit can be enabled to block all program and erase operations from user code. Refer to the Option Bits chapter on page 223 for more information.
Byte Programming
When the Flash Controller is unlocked, Writes to Program Memory from user code will
program a byte into the Flash if the address is located in the unlocked page. An erased
Flash byte contains all ones (FFh). The programming operation can only be used to
change bits from one to zero. To change a Flash bit (or multiple bits) from zero to one
requires a Page Erase or Mass Erase operation.
Byte programming can be performed using the eZ8 CPU’s LDC or LDCI instructions.
Refer to the eZ8 CPU User Manual (UM0128) for a description of the LDC and LDCI
instructions.
While the Flash Controller programs Flash memory, the eZ8 CPU idles, but the system
clock and on-chip peripherals continue to operate. Interrupts that occur when a programming operation is in progress are serviced after the programming operation is complete. To
exit programming mode and lock the Flash Controller, write 00h to the Flash Control
Register.
User code cannot program Flash Memory on a page that lies in a protected sector. When
user code writes memory locations, only addresses located in the unlocked page are programmed. Memory Writes outside of the unlocked page are ignored.
Caution: Each memory location must not be programmed more than twice before an erase is required.
The proper steps to program Flash memory from user code are:
1. Write 00h to the Flash Control Register to reset the Flash Controller.
2. Write the page of memory to be programmed to the Page Select Register.
3. Write the first unlock command 73h to the Flash Control Register.
4. Write the second unlock command 8Ch to the Flash Control Register.
5. rewrite the page written in Step 2 to the Page Select Register.
6. Write Program Memory using LDC or LDCI instructions to program Flash.
7. Repeat Step 6 to program additional memory locations on the same page.
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Byte Programming
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216
8. Write 00h to the Flash Control Register to lock the Flash Controller.
Page Erase
Flash memory can be erased one page (512 bytes) at a time. Page-erasing Flash memory
sets all bytes in that page to the value FFh. The Page Select Register identifies the page to
be erased. While the Flash Controller executes the Page Erase operation, the eZ8 CPU
idles, but the system clock and on-chip peripherals continue to operate. The eZ8 CPU
resumes operation after the Page Erase operation completes. Interrupts that occur when
the Page Erase operation is in progress are serviced after the Page Erase operation is complete. When the Page Erase operation is complete, the Flash Controller returns to its
locked state. Only pages located in unprotected sectors can be erased.
The proper steps to perform a Page Erase operation are:
1. Write 00h to the Flash Control Register to reset the Flash Controller.
2. Write the page to be erased to the Page Select Register.
3. Write the first unlock command, 73h, to the Flash Control Register.
4. Write the second unlock command 8Ch to the Flash Control Register.
5. Rewrite the page written in Step 2 to the Page Select Register.
6. Write the Page Erase command, 95h, to the Flash Control Register.
Mass Erase
Flash memory cannot be mass-erased by user code.
Flash Controller Bypass
The Flash Controller can be bypassed and the control signals for Flash memory brought
out to the GPIO pins. Bypassing the Flash Controller allows faster programming algorithms by controlling the Flash programming signals directly.
Flash Controller Bypass is recommended for gang-programming applications and largevolume customers who do not require in-circuit programming of Flash memory.
Refer to the ZiLOG Application Note titled Third-Party Flash Programming Support for
the Z8 Encore!® MCU (AN0117) for more information about bypassing the Flash controller. This document is available for download at www.zilog.com.
Flash Controller Behavior in Debug Mode
The following changes in behavior of the Flash Controller occur when the Flash Controller is accessed using the On-Chip Debugger:
Program Memory
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•
•
•
•
•
The Flash Write Protect option bit is ignored
•
•
•
The Page Select Register can be written when the Flash Controller is unlocked
The Flash Sector Protect Register is ignored for programming and erase operations
Programming operations are not limited to the page selected in the Page Select Register
Bits in the Flash Sector Protect Register can be written to one or zero
The second write of the Page Select Register to unlock the Flash Controller is not necessary
The Mass Erase command is enabled through the Flash Control Register
The page erase and programming operations are disabled if the Memory Read Protect
option is enabled
Flash Control Register
The Flash Control Register, shown in Table 116, unlocks the Flash Controller for programming and erase operations, or to select the Flash Sector Protect Register.
The Write-Only Flash Control Register shares its Register File address with the ReadOnly Flash Status Register.
Table 116. Flash Control Register (FCTL)
BITS
7
6
5
4
3
FIELD
FCMD
RESET
00H
R/W
W
ADDR
FF8H
Bit
Position
[7:0]
FCMD
Value
73H
8CH
95H
63H
5EH
PS024604-1005
2
1
0
Description
Flash Command:
First unlock command.
Second unlock command.
Page erase command.
Mass erase command.
Flash Sector Protect register select.
All other commands, or any command out of sequence, locks the Flash
Controller.
PRELIMINARY
Flash Control Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
218
Flash Status Register
The Flash Status Register, shown in Table 117, indicates the current state of the Flash Controller. This register can be read at any time. The read-only Flash Status Register shares its
Register File address with the write-only Flash Control Register.
Table 117. Flash Status Register (FSTAT)
BITS
7
6
5
4
3
2
FIELD
Reserved
FSTAT
RESET
00B
00_0000B
R/W
R
R
Value
[7:6]
Reserved
[5:0]
FSTAT
0
FF8H
ADDR
Bit
Position
1
Description
Must be 00.
00_0000
00_0001
00_0010
00_0011
00_0100
00_1xxx
01_0xxx
10_0xxx
Flash Controller Status
Flash Controller locked.
First unlock command received.
Second unlock command received.
Flash Controller unlocked.
Flash Sector Protect register selected.
Program operation in progress.
Page erase operation in progress.
Mass erase operation in progress.
Flash Page Select Register
The Flash Page Select (FPS) Register, shown in Table 118, selects one of the 32 available
Flash memory pages to be erased or programmed. Each Flash Page contains 512 bytes of
Flash memory. During a Page Erase operation, all Flash memory locations with the 7 most
significant bits of the address assigned by the PAGE field are erased to FFh.
The Flash Page Select Register shares its Register File address with the Flash Sector Protect Register. The Flash Page Select Register cannot be accessed when the Flash Sector
Protect Register is enabled.
Program Memory
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219
Table 118. Flash Page Select Register (FPS)
BITS
7
6
5
4
FIELD
INFO_EN
PAGE
RESET
0
000_0000B
R/W
R/W
R/W
[7]
INFO_EN
2
1
0
FF9H
ADDR
Bit
Position
3
Value
Description
0
Information Area Enable
Information area is not selected.
1
Information Area is selected.
The Information area is mapped into the Program Memory address space at
addresses FE00H through FFFFH.
[6:0]
PAGE
Page Select
This 7-bit field selects the Flash memory page for Programming and Page Erase
operations. Program Memory Address[15:9] = PAGE[6:0].
Flash Sector Protect Register
The Flash Sector Protect Register, shown in Table 119, protects Flash memory sectors
from being programmed or erased from user code. The Flash Sector Protect Register
shares its Register File address with the Flash Page Select Register. The Flash Sector protect Register can be accessed only after writing the Flash Control Register with 5Eh.
User code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code).
Table 119. Flash Sector Protect Register (FPROT)
BITS
7
6
5
4
3
2
1
0
FIELD
SECT7
SECT6
SECT5
SECT4
SECT3
SECT2
SECT1
SECT0
RESET
0
0
0
0
0
0
0
0
R/W
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
ADDR
FF9H
R/W1 = Register is accessible for Read operations. Register can be written to 1 only (through user code).
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Flash Sector Protect Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
220
Bit
Position
Value
Description
[7:0]]
SECTn
0
Sector Protect
Sector n can be programmed or erased from user code.
1
Sector n is protected and cannot be programmed or erased from user code.
Flash Frequency High and Low Byte Registers
The Flash Frequency High and Low Byte registers, shown in Tables 120 and 121, combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit Flash Frequency registers must be written with the system clock
frequency in kilohertz for Program and Erase operations. Calculate the Flash Frequency
value using the following equation:
FFREQ[15:0] = {FFREQH[7:0],FFREQL[7:0]} =
System Clock Frequency
1000
Caution: Flash programming and erasure is not supported for system clock frequencies below
32 KHz, above 20 MHz, or outside of the valid operating frequency range for the device.
The Flash Frequency High and Low Byte registers must be loaded with the correct value
to ensure proper program and erase times.
Table 120. Flash Frequency High Byte Register (FFREQH)
BITS
7
6
5
4
3
FIELD
FFREQH
RESET
00H
R/W
R/W
ADDR
FFAH
Program Memory
PRELIMINARY
2
1
0
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221
.
Table 121. Flash Frequency Low Byte Register (FFREQL)
BITS
7
6
5
4
3
FIELD
FFREQL
RESET
00H
R/W
R/W
ADDR
FFBH
2
1
0
FFREQH and FFREQL—Flash Frequency High and Low Bytes
These 2 bytes, {FFREQH[7:0], FFREQL[7:0]}, contain the 16-bit Flash Frequency value.
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Z8 Encore!® Motor Control Flash MCUs
Product Specification
222
Program Memory
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223
Option Bits
Option bits allow user configuration of certain aspects of the Z8FMC16100 Series Flash
MCU operation. The feature configuration data is stored in program memory and read
during Reset. The features available for control using the option bits are:
•
•
•
•
•
•
•
•
•
•
Watch-Dog Timer time-out selection of interrupt or Reset
Watch-Dog Timer enabled at Reset
Code protection by preventing external read access of program memory
The ability to prevent accidental programming and erasure of program memory
Voltage Brown-Out can be disabled during STOP mode to reduce power consumption
External oscillator mode selection
Selectable PWM OFF state, output polarity, fault state, and Reset state
Disable PWM output pairs, enabling them as inputs
RESET/Fault0 pin function selection
Low power clock divide mode selection
Option Bit Types
Two types of option bits, user option bits and trim option bits, allow configuration of certain aspects of Z8FMC16100 Series Flash MCU operation. Each is described in this section.
User Option Bits
The user option bits are contained in the first two bytes of program memory. Because
these locations contain application-specific device configuration, it is possible for the user
to alter these bytes by programming Flash memory.
Note: The information contained in these bytes is lost when page 0 of program memory is
erased.
Trim Option Bits
The trim option bits are contained in the information page of Flash memory. These bits are
factory-programmed values required to optimize the operation of on-board analog circuitry, and cannot be altered by the user. Program memory can be erased without endangering these values.
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Caution: It is possible to alter the working values of these bits by accessing the Trim Bit Address
and Data registers, but these working values are lost after a Reset.
There are 32 trim addresses. To read or write these values, the user code must first write a
value between 00h and 1Fh into the Trim Bit Address Register. Writing the Trim Bit Data
Register changes the working value of the target trim data. Reading the Trim Bit Data
Register returns the working value of the target trim data.
User Option Bit Configuration By Reset
Each time the user option bits are programmed or erased, the device must be Reset for the
change to take place.
Option Bit Address Space
The first two bytes of program memory at addresses 0000h, shown in Table 122, and
0001h, shown in Table 123, are reserved for the user option bits.
Program Memory Address 0000H
Table 122. User Option Bits at Program Memory Address 0000H
BITS
FIELD
7
6
WDT_RES WDT_AO
5
4
3
2
1
0
OSC_SEL[1:0]
VBO_AO
RP
Reserved
FWP
RESET
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program Memory 0000H
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Position
Value
(H)
[7]
WDT_RES
0
Watch-Dog Timer Reset
Watch-Dog Timer time-out generates an interrupt request. Interrupts must be
globally enabled for the eZ8 CPU to acknowledge the interrupt request.
1
Watch-Dog Timer time-out causes a Reset.
0
Watch-Dog Timer Always On
Watch-Dog Timer is automatically enabled.
1
Watch-Dog Timer is enabled upon execution of the WDT instruction.
[6]
WDT_AO
Option Bits
Description
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Bit
Position
[5:4]
OSC_SEL
Value
(H)
00
01
10
11
[3]
VBO_AO
[2]
RP
External Oscillator Mode Selection:
Reserved.
Minimum power for use with very low frequency crystals (32KHz to 1.0MHz).
Medium power for use with medium frequency crystals or ceramic resonators
(0.5MHz to 10.0MHz).
Maximum power for use with high frequency crystals (8.0MHz to 20.0MHz).
0
Voltage Brown Out Always On
Voltage Brown-Out Protection is disabled in STOP mode to reduce total power
consumption.
1
Voltage Brown-Out Protection is always enabled.
0
Read Protect
External access to User program code is disabled.
1
User program code is accessible.
[1]
Reserved
[0]
FWP
Description
Must be 1.
This Option Bit is reserved for future use and must always be 1.
Flash Write Protect
Programming, Page Erase, and Mass Erase using User Code is disabled.
0
1
Programming, Page Erase, and Mass Erase are enabled for all of Flash Program
Memory.
Program Memory Address 0001H
These bits define the behavior of the Pulse-Width Modulator. The high and low default
off-state (the output polarity) is also defined here. The off-state is used by the PWM output
control and PWM Fault logic. PWM output pairs can be disabled and used as high-impedance input pins. The RESET/Fault0 pin function is also selectable.
Table 123. Options Bits at Program Memory Address 0001H
BITS
7
6
FIELD
FLTSEL
LPDEN
RESET
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
5
4
3
2
1
0
PWMHI
PWMLO
U
U
U
R/W
R/W
R/W
Reserved PWM2EN PWM1EN PWM0EN
Program Memory 0001H
Note: U = Unchanged by Reset. R/W = Read/Write.
PS024604-1005
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Program Memory Address 0001H
Z8 Encore!® Motor Control Flash MCUs
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Bit
Position
Value
(H)
[7]
FLTSEL
0
RESET/Fault0 Select
RESET/Fault0 pin is configured as Fault0 input.
1
RESET/Fault0 pin is configured as RESET input.
0
Low Power Divide Mode Enable. See Oscillator Control chapter on page 231.
Low Power Divide mode is enabled
1
Low Power Divide mode is disabled
[6]
LPDEN
[5]
Reserved
[4]
PWM2EN
[3]
PWM1EN
[2]
PWM0EN
[1]
PWMHI
[0]
PWMLO
Option Bits
Description
Must be 1.
This Option Bit is reserved for future use and must always be 1.
0
PWM Output Pair PWM2 Enable
PWM2 outputs are enabled and controlled by PWM logic.
1
PWM2 outputs are always high-impedance.
0
PWM Output Pair PWM1 Enable
PWM1 outputs are enabled and controlled by PWM logic.
1
PWM1 outputs are always high-impedance.
0
PWM Output Pair PWM0 Enable
PWM0 outputs are enabled and controlled by PWM logic.
1
PWM0 outputs are always high-impedance.
0
PWM High Side (PWM outputs 0H,1H, 2H) Default Off-State
PWM High-side inactive state is low, active state is High.
1
PWM High-side inactive state is high, active state is Low.
0
PWM Low Side (PWM outputs 0L,1L, 2L) Default Off-State
PWM Low-side inactive state is low, active state is high.
1
PWM Low-side inactive state is high, active state is low.
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Trim Bit Address Register
The Trim Bit Address Register, shown in Table 124, contains the target address for access
to the trim option bits.
Table 124. Trim Bit Address Register (TRMADR)
BITS
7
6
5
4
3
FIELD
TRMADR
RESET
00H
R/W
R/W
ADDR
FF6H
2
1
0
Bit Position Value (H) Description
[7:0}
TRMADR
00 - 1FH Trim Bit Address Register
Trim Bit Data Register
Trim Bit Data Register, shown in Table 125, contains the read or write data for access to
addresses in the Trim Bit Address Register.
Table 125. Trim Bit Data Register (TRMDR)
BITS
7
6
5
4
3
FIELD
TRMDR
RESET
00H
R/W
R/W
ADDR
FF7H
2
1
0
Bit Position Value (H) Description
[7:0}
TRMDR
00 - FFH Trim Bit Data Register
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Trim Bit Address 0001H
This register is loaded from the Flash Information Area following reset or STOP mode
recovery. Writing to this register allows user frequency adjustment of the IPO. Writing to
this register does not effect the Flash memory contents.
Table 126. IPO Trim Option Bits at 0001H (IPO_TRIM)
BITS
7
6
5
4
3
2
TEMP_TRIM
FIELD
1
0
IPO_TRIM[9:8]
RESET
U
R/W
R/W
ADDR
Information Page Memory 0021H
U = Unchanged by Reset. R/W = Read/Write.
Bit Position Value (H) Description
TEMP_TRIM 00 - 3FH Internal precision Oscillator trim bits for Temperature compensation.
[5:0]
IPO_TRIM
[9:8]
00 - 11H Internal Precision Oscillator Trim Byte
Used with IPO Trim1 options bits as bits [9:8]. Trimming for Internal Precision
Oscillator frequency adjustment.
Trim Bit Address 0002H
This register is loaded from the Flash Information Area following reset or STOP mode
recovery. Writing to this register allows user frequency adjustment of the IPO. Writing to
this register does not effect the Flash memory contents.
Table 127. IPO Trim1 Option Bits at 0002H (IPO_TRIM1)
BITS
7
6
5
4
3
FIELD
IPO_TRIM[7:0]
RESET
U
R/W
R/W
ADDR
Information Page Memory 0022H
2
1
0
U = Unchanged by Reset. R/W = Read/Write.
Option Bits
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Bit Position Value (H) Description
IPO_TRIM
[7:0]
00 - FFH Internal Precision Oscillator Trim Byte
Trimming byte for Internal Precision Oscillator frequency adjustment. Use with
IPO trim bits [9:8} in previous register
Trim Bit Address 0003H
Table 128. Trim Option Bits at 0004H (ADCCAL)
BITS
FIELD
7
6
5
4
3
Reserved
2
1
0
Vref_TRIM
RESET
U
R/W
R/W
ADDR
Information Page Memory 0023H
Note: U = Unchanged by Reset. R/W = Read/Write.
Vref_TRIM—Trim values for the Vref circuit used by the Analog to Digital Converter
Contains factory trimmed values for Vref (ADC Reference Voltage) These values are used
to set the Vref voltage to meet specified tolerance. The format is TBD.
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Trim Bit Address 0003H
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Product Specification
230
Option Bits
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Oscillator Control
The Z8FMC16100 Series Flash MCU uses three possible clocking schemes, each userselectable:
•
•
•
Trimmable Internal Precision Oscillator
On-chip oscillator using off-chip crystal/resonator or external clock driver
On-chip low precision Watch-Dog Timer oscillator
In addition, Z8FMC16100 Series Flash MCUs contain clock failure detection and recovery circuitry, allowing continued operation despite any potential failure of the primary
oscillator.
The on-chip system clock frequency can be reduced via a clock divider allowing reduced
dynamic power dissipation. Flash memory can be powered down during portions of the
clock period when running slower than 10 MHz.
Operation
This section explains the logic used to select the system clock, divide down the system
clock, and handle oscillator failures. A description of the specific operation of each oscillator is outlined elsewhere in this document. Refer to Watch-Dog Timer chapter on page
63, the On-Chip Oscillator chapter on page 237, and the Internal Precision Oscillator
chapter on page 239.
System Clock Selection
The oscillator control block selects from the available clocks. Table 129 details each clock
source and its usage.
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Operation
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Product Specification
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Table 129. Oscillator Configuration and Selection
Clock Source
Characteristics
Required Setup
Internal Precision
Oscillator
• 5.5296 MHz
• This is the reset default.
• High precision possible when trimmed
• No external components required
External Crystal/
Resonator/
External Clock
Drive
• 0 to 20MHz
• Very high accuracy (dependent on
crystal/resonator or external source)
• Requires external components
• Configure Option Bits for correct
external oscillator mode
• Unlock and write Oscillator Control
Register (OSCCTL) to enable external
oscillator
• Wait for required stabilization time
• Unlock and write Oscillator Control
Register (OSCCTL) to select external
oscillator
Internal Watchdog
Timer Oscillator
• 10KHz nominal
• Low accuracy
• No external components required
• Low power consumption
• Unlock and write Oscillator Control
Register (OSCCTL) to enable and select
Internal WDT oscillator
Unintentional accesses to the Oscillator Control Register (OSCCTL) can stop the chip by
switching to a nonfunctioning oscillator. Accidental alteration of the OSCCTL register is
prevented by a locking/unlocking scheme. To write the register, unlock it by making two
writes to the OSCCTL register with the values E7H followed by 18H. A third write to the
OSCCTL register then changes the value of the register and returns the register to a locked
state. Any other sequence of oscillator control register writes has no effect. The values
written to unlock the register must be ordered correctly, but need not be consecutive. It is
possible to access other registers within the locking/unlocking operation.
Clock Selection Following System Reset
The Internal Precision Oscillator is selected following a System Reset. Startup code after
the System Reset may change the system clock source by unlocking and configuring the
OSCCTL register. If the LPDEN bit in Program Memory Address 0001H is zero, Flash
Low Power mode is enabled during reset. When Flash Low Power mode is enabled during
reset, the FLPEN bit in the Oscillator Control Register (OSCCTL) will be set and the DIV
field of the OSCDIV register will be set to 08h.
Clock Failure Detection and Recovery for Primary Oscillator
The Z8FMC16100 Series Flash MCU generates a System Exception when a failure of the
primary oscillator occurs if the POFEN bit is set in the OSCCTL Register. To maintain system function in this situation, the clock failure recovery circuitry automatically forces the
Oscillator Control
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Product Specification
233
Watch-Dog Timer oscillator to drive the system clock. Although this oscillator runs at a
much lower frequency than the original system clock, the CPU continues to operate,
allowing execution of a clock failure vector and software routines that either remedy the
oscillator failure or issue a failure alert. This automatic switch-over is not available if the
Watch-Dog Timer is the primary oscillator.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1KHz ±+/-50%. For operating frequencies below 2KHz, do not enable the
clock failure circuitry (POFEN must be deasserted in the OSCCTL register).
Clock Failure Detection and Recovery for WDT Oscillator
In the event of a Watch-Dog Timer oscillator failure, a System Exception will be issued if
the WDFEN bit of the OSCCTL register is set. This event does not trigger an attendant clock
switch-over, but alerts the CPU of the failure. After a Watch-Dog Timer failure, it is no
longer possible to detect a primary oscillator failure.
The Watch-Dog Timer oscillator failure detection circuit counts system clocks while looking for a Watch-Dog Timer clock. The logic counts 8000 system clock cycles before determining that a failure occurred. The system clock rate determines the speed at which the
Watch-Dog Timer failure can be detected. A very slow system clock results in very slow
detection times. If the Watch-Dog Timer is the primary oscillator or if the Watch-Dog
Timer oscillator is disabled, deassert the WDFEN bit of the OSCCTL register.
Oscillator Control Register
The Oscillator Control Register (OSCCTL) enables/disables the various oscillator circuits,
enables/disables the failure detection/recovery circuitry, actively powers down the flash,
and selects the primary oscillator, which becomes the system clock.
The Oscillator Control Register must be unlocked before writing. Writing the two-step
sequence E7H followed by 18H to the Oscillator Control Register address unlocks it. The
register locks after completion of a register write to the OSCCTL.
Table 130. Oscillator Control Register (OSCCTL)
BITS
7
6
5
4
3
2
1
0
FIELD
INTEN
XTLEN
WDTEN
POFEN
WDFEN
FLPEN
SCKSEL
RESET
1
0
1
0
0
0*
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F86H
ADDR
* The reset value is 1 if the option bit LPDEN is 0.
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Z8 Encore!® Motor Control Flash MCUs
Product Specification
234
Bit
Position
Value
(H)
[7]
INTEN
0
Internal Precision Oscillator Enable
Internal precision oscillator is disabled.
1
Internal precision oscillator is enabled.
0
Crystal Oscillator Enable
Crystal oscillator is disabled.
1
Crystal oscillator is enabled.
0
Watch-Dog Timer Oscillator Enable
Watch-Dog Timer oscillator is disabled
1
Watch-Dog Timer oscillator is enabled
0
Primary Oscillator Failure Detection Enable
Failure detection and recovery of primary oscillator is disabled. This bit is cleared
automatically if a primary oscillator failure is detected.
1
Failure detection and recovery of primary oscillator is enabled
0
Watch-Dog Timer Oscillator Failure Detection Enable
Failure detection of Watch-Dog Timer oscillator is disabled.This bit is cleared
automatically if a Watch-Dog Timer oscillator failure is detected.
1
Failure detection of Watch-Dog Timer oscillator is enabled
0
Flash Low Power Mode Enable
Flash Low Power Mode is disabled.
[6]
XTLEN
[5]
WDTEN
[4]
POFEN
[3]
WDFEN
[2]
FLPEN
1
[1:0]
SCKSEL
Description
Flash Low Power Mode is enabled. The Flash will be powered down during idle
periods of the clock and powered up during Flash reads. This bit should only be
set if the frequency of the primary oscillator source is 8MHz or lower. The reset
value of this bit is controlled by the LPDEN option bit during reset.
00
01
10
11
System Clock Oscillator Select
Internal precision oscillator functions as system clock at 5.6 MHz
Crystal oscillator or external clock driver functions as system clock
Reserved
Watch-Dog Timer oscillator functions as system clock
Oscillator Divide Register
The Oscillator Divide Register (OSCDIV) provides the value that divides the system
clock. The Oscillator Divide Register must be unlocked before writing. Writing the twostep sequence E7h, followed by 18h, to the Oscillator Control Register address unlocks
the register. The register locks after completion of a register Write to the OSCDIV.
Oscillator Control
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Table 131. Oscillator Divide Register (OSCDIV)
BITS
7
6
5
4
3
FIELD
DIV
RESET
00H*
R/W
R/W
ADDR
F87H
2
1
0
* The reset value is 08H if the option bit LPDEN is 0.
Bit
Position
[7:0]
DIV
Value
(H)
00H to
FFH
PS024604-1005
Description
Oscillator Divide
00H - divider is disabled, all other entries are the divide value for scaling the
system clock.
PRELIMINARY
Oscillator Divide Register
Z8 Encore!® Motor Control Flash MCUs
Product Specification
236
Oscillator Control
PRELIMINARY
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237
On-Chip Oscillator
The products in the Z8FMC16100 Series Flash MCU features an on-chip oscillator for use
with external crystals with frequencies ranging from 32 KHz to 20 MHz. In addition, the
oscillator can support ceramic resonators with oscillation frequencies up to 20 MHz. This
oscillator generates the primary system clock for the internal eZ8 CPU and the majority of
the on-chip peripherals. Alternatively, the XIN input pin can also accept a CMOS-level
clock input signal (32 KHz–20 MHz). If an external clock generator is used, the XOUT pin
must remain unconnected.
When configured for use with crystal oscillators or external clock drivers, the frequency of
the signal on the XIN input pin determines the frequency of the system clock (that is, no
internal clock divider).
Crystal Oscillator Operation
Figure 40 illustrates a recommended configuration for connection with an external fundamental-mode, parallel-resonant crystal operating at 20 MHz. Recommended 20 MHz crystal specifications are provided in Table 132. The printed circuit board layout must add no
more than 4 pF of stray capacitance to either the XIN or XOUT pins. If oscillation does not
occur, reduce the values of capacitors C1 and C2 to decrease loading.
On-Chip Oscillator
XIN
XOUT
20 MHz Crystal
(Fundamental Mode)
C2 = 22 pF
C2 = 22 pF
Figure 40. Recommended 20MHz Crystal Oscillator Configuration
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Crystal Oscillator Operation
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Product Specification
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Table 132. Recommended Crystal Oscillator Specifications (20MHz Operation)
On-Chip Oscillator
Parameter
Value
Units
Frequency
20
MHz
Resonance
Parallel
Mode
Fundamental
Series Resistance (RS)
25
Ohm
Maximum
Load Capacitance (CL)
20
pF
Maximum
Shunt Capacitance (C0)
7
pF
Maximum
Drive Level
1
mW
Minimum
PRELIMINARY
Comments
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239
Internal Precision Oscillator
The Internal Precision Oscillator (IPO) is designed for use without external components.
The IPO comes factory trimmed a ±4% frequency accuracy over the operating temperature and supply voltage range of the device. IPO features include:
•
•
•
•
•
On-chip RC oscillator that does not require external components
Trimmed to ±4% accuracy
Target output frequency of 5.5296 MHz
Trimming possible through Flash option bits with user override
Can eliminate crystals or ceramic resonators in applications where high timing accuracy is not required.
Operation
The internal oscillator is an RC relaxation oscillator that has had its sensitivity to power
supply variation minimized. By using ratio tracking thresholds, the effect of power supply
voltage is cancelled out. The dominant source of oscillator error is the absolute variance of
chip-level fabricated components, such as capacitors. Two 8-bit trimming registers, incorporated into the design, allow compensation of absolute variation of oscillator frequency.
Once calibrated, the oscillator frequency is relatively stable and does not require subsequent calibration.
By default, the oscillator is configured through the Flash Option bits. However, the user
code can override these trim values as described in Trim Option Bits section on page 223.
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Operation
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Product Specification
240
Internal Precision Oscillator
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On-Chip Debugger
The Z8FMC16100 Series Flash MCU device includes an integrated On-Chip Debugger
(OCD) that provides advanced debugging features, including:
•
•
•
•
Reading and writing of the Register File
Reading and writing of program and data memory
Setting of break points
Execution of eZ8 CPU instructions
Architecture
The On-Chip Debugger consists of four primary functional blocks: Transmitter, Receiver,
Autobaud Generator, and Debug Controller. Figure 41 illustrates the architecture of the
On-Chip Debugger.
System
Clock
Autobaud
Detector/Generator
eZ8 CPU
Control
Transmitter
Debug Controller
Receiver
DBG Pin
Figure 41. On-Chip Debugger Block Diagram
OCD Interface
The On-Chip Debugger (OCD) uses the DBG pin for communication with an external
host. This one-pin interface is a bidirectional open-drain interface that transmits and
PS024604-1005
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Architecture
Z8 Encore!® Motor Control Flash MCUs
Product Specification
242
receives data. Data transmission is half-duplex, in that transmit and receive cannot occur
simultaneously. The serial data on the DBG pin is sent using the standard asynchronous
data format defined in RS-232. This pin interfaces the Z8FMC16100 Series Flash MCU
device to the serial port of a host PC using minimal external hardware. Two different
methods for connecting the DBG pin to an RS-232 interface are depicted in Figures 42
and 43 .
Caution: For operation of the Z8FMC16100 Series Flash MCU, all power pins (VDD and AVDD)
must be supplied with power, and all ground pins (VSS and AVSS) must be properly
grounded. The DBG pin should always be connected to VDD through an external pullup resistor.
VDD
RS-232
Transceiver
10K‰
Diode
RS232 TX
DBG pin
RS232 RX
Figure 42. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (1)
VDD
RS-232
Transceiver Open-Drain
Buffer
10K‰
RS232 TX
DBG pin
RS232 RX
Figure 43. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)
On-Chip Debugger
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243
Debug Mode
The operating characteristics of the Z8FMC16100 Series Flash MCU device in DEBUG
mode are:
•
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute specific instructions
•
•
The system clock operates unless in STOP mode
•
•
Automatically exits HALT mode
All enabled on-chip peripherals operate unless in STOP mode or otherwise defined by
the on-chip peripheral to disable in DEBUG mode
Constantly refreshes the Watch-Dog Timer, if enabled
Entering Debug Mode
The device enters DEBUG mode following any of the following operations:
•
•
•
•
•
Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface
eZ8 CPU execution of a BRK (break point) instruction (when enabled)
Match of PC to OCDCNTR register (when enabled)
OCDCNTR register decrements to 0000h (when enabled)
The DBG pin is Low when the device exits Reset
Exiting Debug Mode
The device exits DEBUG mode following any of the following operations:
•
•
•
•
•
Clearing the DBGMODE bit in the OCD Control Register to 0
Power-on reset
Voltage Brown Out reset
Asserting the RESET pin Low to initiate a Reset
Driving the DBG pin Low while the device is in STOP mode initiates a System Reset
OCD Data Format
The On-Chip Debugger (OCD) interface uses the asynchronous data format defined for
RS-232. Each character is transmitted as 1 start bit, 8 data bits (least-significant bit first),
and 1 stop bit. See Figure 44.
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Z8 Encore!® Motor Control Flash MCUs
Product Specification
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ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST = Start Bit
SP = Stop Bit
D0—D7 = Data Bits
Figure 44. OCD Data Format
OCD Auto-Baud Detector/Generator
To run over a range of baud rates (bits per second) with various system clock frequencies,
the On-Chip Debugger has an Auto-Baud Detector/Generator. After a reset, the OCD is
idle until it receives data. The OCD requires that the first character sent from the host is
the character 80h. The character 80h contains eight continuous bits Low (one Start bit
plus 7 data bits). The Auto-Baud Detector measures this period and sets the OCD Baud
Rate Generator accordingly.
The Auto-Baud Detector/Generator is clocked by the system clock. The minimum baud
rate is the system clock frequency divided by 512. The maximum recommended baud rate
is the system clock frequency divided by 8. Table 133 lists minimum and recommended
maximum baud rates for sample crystal frequencies.
Table 133. OCD Baud-Rate Limits
System Clock
Frequency
Maximum Asynchronous
Baud Rate (bits/s)
Minimum
Baud Rate (bits/s)
20.0 MHz
2.5 M
39.1 K
1.0 MHz
125 K
1960
32.768 KHz
4096
64
If the OCD receives a Serial Break (ten or more continuous bits Low) the Auto-Baud
Detector/Generator resets. The Auto-Baud Detector/Generator can then be reconfigured
by sending 80h. If the Auto-Baud Detector overflows while measuring the Auto-Baud
character, the Auto-Baud Detector will remain reset.
OCD Serial Errors
The On-Chip Debugger can detect any of the following error conditions on the DBG pin:
•
•
On-Chip Debugger
Serial Break (a minimum of ten continuous bits Low)
Framing Error (received STOP bit is Low)
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•
Transmit Collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a Serial Break 4096 system clock cycles long back to the host, and resets the
Auto-Baud Detector/Generator. A Framing Error or Transmit Collision can be caused by
the host sending a Serial Break to the OCD. Because of the open-drain nature of the interface, returning a Serial Break break back to the host only extends the length of the Serial
Break if the host releases the Serial Break early.
The host transmits a Serial Break on the DBG pin when first connecting to the
Z8FMC16100 Series Flash MCU device or when recovering from an error. A Serial Break
from the host resets the Auto-Baud Generator/Detector but does not reset the OCD Control Register. A Serial Break leaves the device in DEBUG mode if that is the current mode.
The OCD is held in Reset until the end of the Serial Break when the DBG pin returns
High. Because of the open-drain nature of the DBG pin, the host can send a Serial Break to
the OCD even if the OCD is transmitting a character.
Automatic Reset
The Z8FMC16100 Series Flash MCU devices have the capability to switch clock sources
during operation. If the Auto-Baud is set and the clock source is switched, the Auto-Baud
value becomes invalid. A new Auto-Baud value must be configured with the new clock
frequency.
The oscillator control logic has clock switch detection. If a clock switch is detected and
the Auto-Baud is set, the device will automatically send a Serial Break for 4096 clocks.
This will reset the Auto-Baud and indicate to the host that a new Auto-Baud character
should be sent.
Break Points
Execution break points are generated using the BRK instruction (Op Code 00h). When the
eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If break points are
enabled, the OCD idles the eZ8 CPU and enters DEBUG mode. If break points are not
enabled, the OCD ignores the BRK signal and the BRK instruction operates as a NOP
instruction.
If break points are enabled, the OCD can be configured to automatically enter DEBUG
mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK
instruction, then the CPU remains able to service DMA and interrupt requests.
The loop on BRK instruction can service interrupts in the background. For interrupts to be
serviced in the background, there cannot be any break points in the interrupt service routine. Otherwise, the CPU stops on the break point in the interrupt routine. For interrupts to
be serviced in the background, interrupts must also be enabled. Debugging software does
not automatically enable interrupts when using this feature. Interrupts are typically dis-
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abled during critical sections of code where interrupts do not occur (such as adjusting the
stack pointer or modifying shared data).
Host software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is
looping on a BRK instruction. When software wants to stop the CPU on the BRK instruction on which it is looping, software must not set the DBGMODE bit of the OCDCTL register. The CPU may have vectored to an interrupt service routine. Instead, software clears
the BRKLP bit. This allows the CPU to finish the interrupt service routine it may be in and
return to the BRK instruction. When the CPU returns to the BRK instruction on which it
was previously looping, it automatically sets the DBGMODE bit and enters DEBUG
mode.
The majority of the OCD commands remain disabled when the eZ8 CPU is looping on a
BRK instruction. The eZ8 CPU must be in DEBUG mode before these commands can be
issued.
Break Points in Flash Memory
The BRK instruction is Op Code 00h, which corresponds to the fully programmed state of
a byte in Flash memory. To implement a break point, write 00h to the appropriate address,
overwriting the current instruction. To remove a break point, erase the corresponding page
of Flash memory and reprogram with the original data.
OCDCNTR Register
The On-Chip Debugger contains a multipurpose 16-bit Counter Register. It can be used
for the following:
•
•
•
Count system clock cycles between break points
Generate a BRK when it counts down to 0
Generate a BRK when its value matches the Program Counter
When configured as a counter, the OCDCNTR register starts counting when the On-Chip
Debugger leaves DEBUG mode and stops counting when it enters DEBUG mode again or
when it reaches the maximum count of FFFFh. The OCDCNTR register automatically
resets itself to 0000h when the OCD exits DEBUG mode if it is configured to count clock
cycles between break points.
If the OCDCNTR Register is configured to generate a BRK when it counts down to zero,
it will not be reset when the CPU starts running. The counter will start counting down
toward zero once the On-Chip debugger leaves DEBUG mode. If the On-Chip Debugger
enters DEBUG mode before the OCDCNTR register counts down to zero, the OCDCNTR
will stop counting.
If the OCDCNTR register is configured to generate a BRK when the program counter
matches the OCDCNTR register, the OCDCNTR register will not be reset when the CPU
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resumes executing and it will not be decremented when the CPU is running. A BRK will
be generated when the program counter matches the value in the OCDCNTR register
before executing the instruction at the location of the program counter.
Caution: The OCDCNTR register is used by many of the OCD commands. It counts the number
of bytes for the register and memory read/write commands. It retains the residual value
when generating the CRC. If the OCDCNTR is used to generate a BRK, its value must
be written as a final step before leaving DEBUG mode.
Because this register is overwritten by various OCD commands, it must only be used to
generate temporary break points, such as stepping over CALL instructions or running to a
specific instruction and stopping.
When the OCDCNTR register is read, it returns the inverse of the data in this register. The
OCDCNTR register is only decremented when counting. The mode where it counts the
number of clock cycles in between execution is achieved by counting down from its maximum count. When the OCDCNTR register is read, the counter appears to have counted
up because its value is inverted. The value in this register is always inverted when it is
read. If this register is used as a hardware break point, the value read from this register will
be the inverse of the data actually in the register.
On-Chip Debugger Commands
The host communicates to the On-Chip Debugger by sending OCD commands using the
DBG interface. During normal operation, only a subset of the OCD commands are available. In Debug mode, all OCD commands become available unless the user code is protected by programming the Read Protect option bit (RP). The Read Protect option bit
prevents the code in memory from being read out of the Z8FMC16100 Series Flash MCU
device. When this option is enabled, several of the OCD commands are disabled. Table
134 contains a summary of the On-Chip Debugger commands. Each OCD command is
described in further detail in the bulleted list following Table 134. Table 134 indicates
those commands that operate when the device is not in DEBUG mode (normal operation)
and those commands that are disabled by programming the Read Protect option bit.
Table 134. On-Chip Debugger Commands
Command
Byte
Enabled When Not
In Debug Mode?
Disabled by Read Protect
Option Bit
Read Revision
00h
Yes
—
Write OCD Counter Register
01h
—
—
Read OCD Status Register
02h
Yes
—
Read OCD Counter Register
03h
—
—
Debug Command
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Table 134. On-Chip Debugger Commands (Continued)
Command
Byte
Enabled When Not
In Debug Mode?
Disabled by Read Protect
Option Bit
Write OCD Control Register
04h
Yes
—
Read OCD Control Register
05h
Yes
—
Write Program Counter
06h
—
Disabled
Read Program Counter
07h
—
Disabled
Write Register
08h
—
Writes to on-chip peripheral
registers are enabled. Writes to
the on-chip RAM are disabled.
Read Register
09h
—
Reads from on-chip peripheral
registers are enabled. Reads from
the on-chip RAM are disabled.
Write Program Memory
0Ah
—
Disabled
Read Program Memory
0Bh
—
Disabled
Write Data Memory
0Ch
—
Disabled
Read Data Memory
0Dh
—
Disabled
Read Program Memory CRC
0Eh
—
—
Reserved
0Fh
—
—
Step Instruction
10h
—
Disabled
Stuff Instruction
11H
—
Disabled
Execute Instruction
12H
—
Disabled
Read Baud Reload Register
1BH
—
—
Debug Command
Note: Unlisted command byte values are reserved.
In the following bulleted list of OCD Commands, data and commands sent from the host
to the On-Chip Debugger are identified by ’DBG ← Command/Data’. Data sent from the
On-Chip Debugger back to the host is identified by ’DBG → Data’
Read Revision. The Read Revision command returns the revision identifier. DBG ←
00h
DBG → REVID[15:8] (Major revision number)
DBG → REVID[7:0] (Minor revision number)
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Write OCD Counter Register. The Write OCD Counter Register command writes the
data that follows to the OCDCNTR register. If the device is not in DEBUG mode, the data
is discarded.
DBG ← 01h
DBG ← OCDCNTR[15:8]
DBG ← OCDCNTR[7:0]
Read OCD Status Register. The Read OCD Status Register command reads the OCD-
STAT register.
DBG ← 02h
DBG → OCDSTAT[7:0]
Read OCD Counter Register. The OCD Counter Register can be used to count system
clock cycles in between break points, generate a BRK when it counts down to 0, or generate a BRK when its value matches the Program Counter. Because this register is really a
down counter, the returned value is inverted when this register is read so the returned
result appears to be an up counter. If the device is not in DEBUG mode, this command
returns FFFFh.
DBG ← 03h
DBG → ~OCDCNTR[15:8]
DBG → ~OCDCNTR[7:0]
Write OCD Control Register. The Write OCD Control Register command writes the data
that follows to the OCDCTL register.
DBG ← 04h
DBG ← OCDCTL[7:0]
Read OCD Control Register. The Read OCD Control Register command reads the value
of the OCDCTL register.
DBG ← 05h
DBG → OCDCTL[7:0]
Write Program Counter. The Write Program Counter command writes the data that fol-
lows to the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode or if
the Read Protect option bit is enabled, the Program Counter (PC) values are discarded.
DBG ← 06h
DBG ← ProgramCounter[15:8]
DBG ← ProgramCounter[7:0]
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Read Program Counter. The Read Program Counter command reads the value in the eZ8
CPU’s Program Counter (PC). If the device is not in DEBUG mode or if the Read Protect
option bit is enabled, this command returns FFFFh.
DBG ← 07h
DBG → ProgramCounter[15:8]
DBG → ProgramCounter[7:0]
Write Register. The Write Register command writes data to the Register File. Data can be
written 1-256 bytes at a time (256 bytes can be written by setting size to zero). If the
device is not in DEBUG mode, the address and data values are discarded. If the Read Protect option bit is enabled, then only writes to the on-chip peripheral registers are allowed
and all other register write data values are discarded.
DBG
DBG
DBG
DBG
DBG
←
←
←
←
←
08h
{4’h0,Register Address[11:8]}
Register Address[7:0]
Size[7:0]
1-256 data bytes
Read Register. The Read Register command reads data from the Register File. Data can
be read 1-256 bytes at a time (256 bytes can be read by setting size to zero). If the device
is not in DEBUG mode or if the Read Protect option bit is enabled and on-chip RAM is
being read from, this command returns FFh for all the data values.
DBG
DBG
DBG
DBG
DBG
←
←
←
←
→
09h
{4’h0,Register Address[11:8]
Register Address[7:0]
Size[7:0]
1-256 data bytes
Write Program Memory. The Write Program Memory command writes data to Program
Memory. This command is equivalent to the LDC and LDCI instructions. Data can be
written 1–65536 bytes at a time (65536 bytes can be written by setting size to 0). The onchip Flash controller must be written to and unlocked for the programming operation to
occur. If the Flash controller is not unlocked, the data is discarded. If the device is not in
DEBUG mode or if the Read Protect option bit is enabled, the data is discarded.
DBG
DBG
DBG
DBG
DBG
DBG
On-Chip Debugger
←
←
←
←
←
←
0Ah
Program Memory Address[15:8]
Program Memory Address[7:0]
Size[15:8]
Size[7:0]
1-65536 data bytes
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Read Program Memory. The Read Program Memory command reads data from Program
Memory. This command is equivalent to the LDC and LDCI instructions. Data can be read
1–65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not
in DEBUG mode or if the Read Protect option bit is enabled, this command returns FFh
for the data.
DBG
DBG
DBG
DBG
DBG
DBG
←
←
←
←
←
→
0Bh
Program Memory Address[15:8]
Program Memory Address[7:0]
Size[15:8]
Size[7:0]
1-65536 data bytes
Write Data Memory. The Write Data Memory command writes data to Data Memory.
This command is equivalent to the LDE and LDEI instructions. Data can be written 1–
65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device is not
in DEBUG mode or if the Read Protect option bit is enabled, the data is discarded.
DBG
DBG
DBG
DBG
DBG
DBG
←
←
←
←
←
←
0Ch
Data Memory Address[15:8]
Data Memory Address[7:0]
Size[15:8]
Size[7:0]
1-65536 data bytes
Read Data Memory. The Read Data Memory command reads from Data Memory. This
command is equivalent to the LDE and LDEI instructions. Data can be read 1–65536
bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in
DEBUG mode, this command returns FFh for the data.
DBG
DBG
DBG
DBG
DBG
DBG
←
←
←
←
←
→
0Dh
Data Memory Address[15:8]
Data Memory Address[7:0]
Size[15:8]
Size[7:0]
1-65536 data bytes
Read Program Memory CRC. The Read Program Memory CRC command computes and
returns the CRC (cyclic redundancy check) of Program Memory using the 16-bit CRCCCITT polynomial (x16 + x12 + x5 + 1). The CRC is preset to all 1s. The least-significant
bit of the data is shifted through the polynomial first. The CRC is inverted when it is transmitted. If the device is not in DEBUG mode, this command returns FFFFh for the CRC
value. Unlike most other OCD Read commands, there is a delay from issuing of the command until the OCD returns the data. The OCD reads the Program Memory, calculates the
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CRC value, and returns the result. The delay is a function of the Program Memory size and
is approximately equal to the system clock period multiplied by the number of bytes in the
Program Memory.
DBG ← 0Eh
DBG → CRC[15:8]
DBG → CRC[7:0]
Step Instruction. The Step Instruction command steps one assembly instruction at the
current Program Counter (PC) location. If the device is not in DEBUG mode or the Read
Protect option bit is enabled, the OCD ignores this command.
DBG ← 10h
Stuff Instruction. The Stuff Instruction command steps one assembly instruction and
allows specification of the first byte of the instruction. The remaining 0–4 bytes of the
instruction are read from Program Memory. This command is useful for stepping over
instructions where the first byte of the instruction has been overwritten by a break point. If
the device is not in DEBUG mode or the Read Protect option bit is enabled, the OCD
ignores this command.
DBG ← 11h
DBG ← opcode[7:0]
Execute Instruction. The Execute Instruction command allows sending an entire instruc-
tion to be executed to the eZ8 CPU. This command can also step over break points. The
number of bytes to send for the instruction depends on the Op Code. If the device is not in
DEBUG mode or the Read Protect option bit is enabled, the OCD ignores this command
DBG ← 12h
DBG ← 1-5 byte opcode
Read Baud Reload Register. The Read Baud Reload Register command returns the current value in the Baud Reload register.
DBG ← 1Bh
DBG → BAUD[15:8]
DBG → BAUD[7:0]
OCD Control Register
The OCD Control Register, shown in Table 135, controls the state of the On-Chip Debugger. This register enters or exits DEBUG mode and enables the BRK instruction. It can
also reset the Z8FMC16100 Series Flash MCU.
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A reset and stop function can be achieved by writing 81H to this register. A reset and go
function is achieved by writing 41H to this register. If the device is in DEBUG mode, a run
function is implemented by writing 40h to this register.
A more detailed description of each bit follows the table.
Table 135. OCD Control Register (OCDCTL)
BITS
7
FIELD DBGMODE
6
BRKEN
5
4
DBGACK BRKLOOP
3
2
1
0
BRKPC
BRKZRO
Reserved
RST
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
DBGMODE—Debug Mode
Setting this bit to 1 causes the device to enter Debug mode. When in DEBUG mode, the
eZ8 CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to resume
execution. This bit is automatically set when a BRK instruction is decoded and Breakpoints are enabled.
0 = The device is running (operating in NORMAL mode).
1 = The device is in DEBUG mode.
BRKEN—Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode 00H). By default, Breakpoints are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1 and a
BRK instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit.
0 = BRK instruction is disabled.
1 = BRK instruction is enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
a Debug Acknowledge character (FFH) to the host when a Breakpoint occurs. This bit
automatically clears itself when an acknowledge character is sent.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
BRKLOOP—Breakpoint Loop
This bit determines what action the OCD takes when a BRK instruction is decoded and
breakpoints are enabled (BRKEN is 1). If this bit is 0, the DBGMODE bit is automatically
set to 1 and the OCD enters DEBUG mode. If BRKLOOP is set to 1, the eZ8 CPU loops
on the BRK instruction.
0 = BRK instruction sets DBGMODE to 1.
1 = eZ8 CPU loops on BRK instruction.
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BRKPC—Break when PC == OCDCNTR
If this bit is set to 1, then the OCDCNTR register is used as a hardware breakpoint. When
the program counter matches the value in the OCDCNTR register, DBGMODE is automatically set to 1. If this bit is set, the OCDCNTR register does not count when the CPU is
running.
0 = OCDCNTR is setup as counter
1 = OCDCNTR generates hardware break when PC == OCDCNTR
BRKZRO—Break when OCDCNTR == 0000H
If this bit is set, then the OCD automatically sets the DBGMODE bit when the OCDCNTR register counts down to 0000H. If this bit is set, the OCDCNTR register is not reset
when the part leaves DEBUG Mode.
0 = OCD does not generate BRK when OCDCNTR decrements to 0000H
1 = OCD sets DBGMODE to 1 when OCDCNTR decrements to 0000H
Reserved—Must be 0.
RST—Reset
Setting this bit to 1 resets the device. The controller goes through a normal Power-On
Reset sequence with the exception that the On-Chip Debugger is not reset. This bit is automatically cleared to 0 when the reset finishes.
0 = No effect.
1 = Reset the device.
OCD Status Register
The OCD Status Register, shown in Table 136, reports status information about the current
state of the debugger and the system. A more detailed description of each bit follows the
table.
Table 136. OCD Status Register (OCDSTAT)
BITS
7
6
5
4
3
2
FIELD
IDLE
HALT
RPEN
Reserved
RESET
0
0
0
0
R/W
R
R
R
R
1
0
IDLE—CPU idle
This bit is set if the part is in Debug mode (DBGMODE is 1) or if a BRK instruction has
occurred since the last time OCDCTL was written. This can be used to determine if the
CPU is running or if it is idle.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
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HALT—HALT Mode
0 = The device is not in HALT mode.
1 = The device is in HALT mode.
RPEN—Read Protect Option Bit Enabled
0 = The Read Protect Option Bit is disabled (Flash option bit is 1).
1 = The Read Protect Option Bit is enabled (Flash option bit is 0), disabling many OCD
commands.
Reserved—Must be 0.
Baud Reload Register
The Baud Reload Register, shown in Table 137, contains the measured Autobaud value.
Table 137. Baud Reload Register
BITS
15
14
13
12
11
10
9
8
7
6
5
FIELD
Reserved
RELOAD
RESET
0H
000H
R/W
R
R
4
3
2
1
0
RELOAD—Baud Reload Value
This value is the measured Auto-Baud value. Its value can be calculated using the following formula.
RELOAD =
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Electrical Characteristics
The electrical characteristics of the Z8FMC16100 Series are described in the following
sections.
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows
about this product at this time, but additional features or nonconformance with some
aspects of the document might be found, either by ZiLOG or its customers in the course of
further application and characterization work. In addition, ZiLOG cautions that delivery
might be uncertain at times, because of start-up yield issues.
Absolute Maximum Ratings
The ratings listed in Table 138 are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. For improved reliability, unused inputs must be tied to one of the supply
voltages (VDD or VSS).
Caution: Stresses greater than those listed in Table 138 may cause permanent damage to the device.
Table 138. Absolute Maximum Ratings*
Parameter
Minimum Maximum
Units
Ambient temperature under bias
–40
+105
ºC
Storage temperature
–65
+150
ºC
Voltage on any pin with respect to VSS
–0.3
+5.5
V
Voltage on VDD pin with respect to VSS
–0.3
+3.6
V
Maximum current on input and/or inactive output pin
–5
+5
µA
Maximum output current from digital active output pin
–25
+25
mA
Maximum output current from digital active output pin
–5
+5
mA
Notes
1
*Note: This voltage applies to all pins except VDD and PC0.
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Table 138. Absolute Maximum Ratings* (Continued)
Parameter
Minimum Maximum
Units
Notes
32-pin LQFP Package Maximum Ratings at –40ºC to 70ºC
Total power dissipation
811
mW
Maximum current into VDD or out of VSS
225
mA
Total power dissipation
295
mW
Maximum current into VDD or out of VSS
82
mA
Total power dissipation
1580
mW
Maximum current into VDD or out of VSS
439
mA
Total power dissipation
575
mW
Maximum current into VDD or out of VSS
160
mA
32-pin LQFP Package Maximum Ratings at 70ºC to 105ºC
32-pin QFN Package Maximum Ratings at –40ºC to 70ºC
32-pin QFN Package Maximum Ratings at 70ºC to 105ºC
*Note: This voltage applies to all pins except VDD and PC0.
DC Characteristics
Table 139 lists the DC characteristics of the Z8FMC16100 Series Flash MCU products.
All voltages are referenced to VSS, the primary system ground.
Table 139. DC Characteristics
TA = –40ºC to 105ºC
Symbol Parameter
Minimum Typical2 Maximum Units Conditions
VDD
Supply Voltage
2.7
—
3.6
V
VIL1
Low Level Input Voltage
–0.3
—
0.3*VDD
V
For all input pins except
RESET, DBG, and XIN.
VIL2
Low Level Input Voltage
–0.3
—
0.2*VDD
V
For RESET, DBG, and
XIN.
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
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Table 139. DC Characteristics (Continued)
TA = –40ºC to 105ºC
Symbol Parameter
Minimum Typical2 Maximum Units Conditions
VIH1
High Level Input Voltage
0.7 x VDD
—
5.5
V
Port pins when their
programmable pull-ups
are disabled. Except
PC0.
VIH2
High Level Input Voltage
0.7 x VDD
—
VDD+0.3
V
Port pins when their
programmable pull-ups
are enabled and PC0.
VIH3
High Level Input Voltage
0.8 x VDD
—
VDD+0.3
V
RESET, DBG, and XIN
pins.
VOL1
Low Level Output Voltage
—
—
0.4
V
IOL = 2mA; VDD = 3.0V
High Output Drive
disabled.
VOH1
High Level Output Voltage
2.4
—
—
V
IOH = –2 mA; VDD = 3.0V
High Output Drive
disabled.
VOL2
Low Level Output Voltage
High Drive
—
—
0.6
V
IOL = 20 mA; VDD = 3.3V
High Output Drive
enabled; TA = –40ºC to
+70ºC
VOH2
High Level Output Voltage
High Drive
2.4
—
—
V
IOH = –20 mA; VDD =
3.3V; High Output Drive
enabled; TA = –40ºC to
+70ºC
VOL3
Low Level Output Voltage
High Drive
—
—
0.6
V
IOL = 15mA; VDD = 3.3V
High Output Drive
enabled; TA = +70ºC to
+105ºC.
VOH3
High Level Output Voltage
High Drive
2.4
—
—
V
IOH = 15mA; VDD = 3.3V
High Output Drive
enabled; TA = +70ºC to
+105ºC.
VRAM
RAM Data Retention
0.7
—
—
V
IIL
Input Leakage Current
–5
—
+5
µA
VDD = 3.3V;
VIN = VDD or VSS1.
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
PS024604-1005
PRELIMINARY
DC Characteristics
Z8 Encore!® Motor Control Flash MCUs
Product Specification
260
Table 139. DC Characteristics (Continued)
TA = –40ºC to 105ºC
Symbol Parameter
Minimum Typical2 Maximum Units Conditions
ITL
Tri-State Leakage Current
–5
—
+5
µA
VDD = 3.3V.
IPU1
Weak Pull-up Current
9
20
50
µA
VDD = 2.7–3.6V.
TA = 0ºC to +70ºC.
IPU2
Weak Pull-up Current
7
20
75
µA
VDD = 2.7–3.6V.
TA = –40ºC to +105ºC.
Idd
stop1
Chip leakage current in
STOP mode
2
uA
STOP mode with VBO
disabled, WDT enabled.
Idd
stop2
Chip leakage current in
STOP mode
<1
uA
STOP mode with VBO
and WDT disabled.
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
Figure 45 illustrates the typical active mode current consumption while operating at 25ºC,
3.3 V, versus the system clock frequency. All GPIO pins are configured as outputs and
driven High.
Note:
Figures 45 through 50 are not yet available. At this time, the Z8FMC16100 Series Flash
MCU is not fully characterized.
Electrical Characteristics
PRELIMINARY
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Product Specification
261
TBD
Figure 45. Typical Active Mode IDD Versus System Clock Frequency
Figure 46 illustrates the maximum active mode current consumption across the full operating temperature range of the device and versus the system clock frequency. All GPIO
pins are configured as outputs and driven High.
TBD
Figure 46. Maximum Active Mode IDD Versus System Clock Frequency
PS024604-1005
PRELIMINARY
DC Characteristics
Z8 Encore!® Motor Control Flash MCUs
Product Specification
262
Figure 47 illustrates the typical current consumption in HALT mode while operating at
25ºC versus the system clock frequency. All GPIO pins are configured as outputs and
driven High.
TBD
Figure 47. Typical Halt Mode IDD Versus System Clock Frequency
Figure 48 illustrates the maximum HALT mode current consumption across the full operating temperature range of the device and versus the system clock frequency. All GPIO
pins are configured as outputs and driven High.
TBD
Figure 48. Maximum Halt Mode ICC Versus System Clock Frequency
Electrical Characteristics
PRELIMINARY
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Z8FMC16100 Series Flash MCU
Product Specification
263
Figure 49 illustrates the maximum current consumption in STOP mode with the VBO and
Watch-Dog Timer enabled versus the power supply voltage. All GPIO pins are configured
as outputs and driven High.
TBD
Figure 49. Maximum Stop Mode IDD with VBO enabled versus Supply Voltage
Figure 50 illustrates the maximum current consumption in STOP mode with the VBO disabled and Watch-Dog Timer enabled versus the power supply voltage. All GPIO pins are
configured as outputs and driven High. Disabling the Watch-Dog Timer and its internal
RC oscillator in STOP mode will provide some additional reduction in STOP mode current consumption. This small current reduction would be indistinguishable on the scale of
Figure 50.
PS024604-1005
PRELIMINARY
DC Characteristics
Z8 Encore!® Motor Control Flash MCUs
Product Specification
264
TBD
Figure 50. Maximum Stop Mode IDD with VBO Disabled vs. Supply Voltage
AC Characteristics
The section provides information on the AC characteristics and timing. All AC timing
information assumes a standard load of 50 pF on all outputs. Data in the typical column is
from characterization at 3.3 V and 25 ºC. These values are provided for design guidance
only and are not tested in production.
Table 140. AC Characteristics
VDD = 2.7–3.6V
TA = –40ºC to 105ºC
Symbol
Parameter
FSYSCLK
System clock frequency
FXTAL
Crystal oscillator frequency
TXIN
Minimum Maximum Units Conditions
—
20.0
MHz
0.032768
20.0
MHz System clock frequencies
below the crystal oscillator
minimum require an external
clock driver.
System clock period
50
—
ns
TCLK = 1 ÷ FSYSCLK.
TXINH
System clock high time
20
30
ns
TCLK = 50 ns.
TXINL
System clock low time
20
30
ns
TCLK = 50 ns.
Electrical Characteristics
PRELIMINARY
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Product Specification
265
On-Chip Peripheral AC and DC Electrical Characteristics
Table 141 provides electrical characteristics and timing information for the POR and VBO
circuits.
Table 141. POR and VBO Electrical Characteristics and Timing
TA = –40ºC to 105ºC
Minimum
Typical1
Power-on reset
voltage threshold
2.20
2.45
2.70
V
VDD = VPOR.
Voltage Brown-Out
reset voltage threshold
2.15
2.40
2.65
V
VDD = VVBO.
50
75
mV
Symbol
Parameter
VPOR
VVBO
VPOR–VVBO
Maximum Units Conditions
Starting VDD voltage to
ensure valid Power-On
Reset.
—
VSS
—
V
TANA
Power-On Reset
analog delay
—
50
—
ms
VDD > VPOR; TPOR
Digital Reset delay
follows TANA.
TPOR
Power-On Reset digital
delay
—
5.0
—
ms
50 WDT Oscillator
cycles (10 KHz) + 16
System Clock cycles
(20 MHz).
TVBO
Voltage Brown-Out
pulse rejection period
—
10
—
ms
VDD < VVBO to generate
a Reset.
TRAMP
Time for VDD to
transition from VSS to
VPOR to ensure valid
Reset
0.10
—
100
ms
ICC
Supply current
500
µA
VDD = 3.3 V.
Notes:
1. Data in the typical column is from characterization at 3.3V and 250C. These values are provided for design guidance only and are not tested in production.
PS024604-1005
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On-Chip Peripheral AC and DC Electrical
Z8 Encore!® Motor Control Flash MCUs
Product Specification
266
Table 142 provides electrical characteristics and timing information for the External RC
Oscillator.
Table 142. External RC Oscillator Electrical Characteristics and Timing
TA = –40ºC to 105ºC
Symbol
Parameter
VDD
Operating voltage
range
REXT
External resistance
from XIN to VDD
CEXT
FOSC
Minimum
2.70
1
Typical1
Maximum Units Conditions
—
—
V
40
45
200
K¾
External capacitance
from XIN to VSS
0
20
1000
pF
External RC oscillation
frequency
—
—
4
MHz
Note:
1. When using the external RC oscillator mode, the oscillator may stop oscillating if the power supply drops below
2.7V, but before the power supply drops to the voltage brown-out threshold. The oscillator will resume oscillation
as soon as the supply voltage exceeds 2.7V..
Table 143 provides electrical characteristics and timing information for the Internal Precision Oscillator.
Table 143. Internal Precision Oscillator Electrical Characteristics and Timing
TA = –40ºC to 105ºC
Symbol
Parameter
FOf
Output frequency1
ICC
Supply current
Minimum
Typical
5.308
5.5296
1.6
Maximum Units Conditions
5.75
MHz
mA
VDD = 3.3 V.
Note:
1. The frequency is factory programmed.
Electrical Characteristics
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
267
Table 144 provides electrical characteristics and timing information for the Watch-Dog
Timer.
Table 144. Watch-Dog Timer Electrical Characteristics and Timing
VDD = 2.7–3.6V
TA = –40ºC to 105ºC
Symbol Parameter
FOSC
Output frequency
ICC
Supply current
Minimum
Typical
5
10
Maximum Units Conditions
15
2
KHz
VDD = 3.3 V.
µA
VDD = 3.3 V.
Table 145 provides electrical characteristics and timing information for the Reset and
Stop-Mode Recovery functions.
Table 145. Reset and Stop-Mode Recovery Pin Timing
TA = –40ºC to 105ºC
Symbol Parameter
Minimum
Typical
Maximum Units Conditions
TRESET
RESET pin assertion to
initiate a System Reset.
4
—
—
TSMR
Stop-Mode Recovery pin
pulse rejection period
10
20
40
TCLK Not in STOP mode.
TCLK = System Clock
period.
ns
RESET, DBG, and GPIO
pins configured as SMR
sources.
Table 146 provides electrical characteristics and timing information for the Analog-toDigital Converter and illustrates the input frequency response of the ADC.
Table 146. Analog-to-Digital Converter Electrical Characteristics and Timing
TA = –40ºC to 105ºC
Symbol Parameter
Minimum
Typical
Resolution
10
—
Throughput conversion
13
Maximum Units Conditions
ADCCLK frequency
bits
External VREF = 2.0 V.
CLKs ADC clock cycles.
20
MHz
DNL
Differential nonlinearity
for 8-bit use
–0.99
1.25
LSB
20 MHz sys clock with
ADC clock divided by 4
INL
Integral nonlinearity
for 8-bit use
–1.25
1.25
LSB
20 MHz sys clock with
ADC clock divided by 4
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On-Chip Peripheral AC and DC Electrical
Z8 Encore!® Motor Control Flash MCUs
Product Specification
268
Table 146. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued)
TA = –40ºC to 105ºC
Minimum
Symbol Parameter
Typical
Maximum Units Conditions
DNL
Differential nonlinearity
for 10-bit
2
LSB
20 MHz sys clock with
ADC clock divided by 4
INL
Integral nonlinearity
for 10-bit
2
LSB
20 MHz sys clock with
ADC clock divided by 4
VREF
Offset error
–30
30
mV
Gain error
–25
25
LSB
On-chip voltage reference
1.9
2.1
V
Analog input voltage range
0
VREF
V
500
nA
2
Analog input current
Reference input current
Vref
2.0
mA
External Vref voltage
Analog input capacitance
AVDD
Operation supply voltage
2.7
2.5 V
V
15
pF
3.6
V
Operating current, AVDD
9.0
mA
Power-down current
<1
µA
Worst case code
At 20MHz ADC clock
Table 147 provides electrical characteristics and timing information for the on-chip Comparator.
Table 147. Comparator Electrical Characteristics
= 2.7–3.6V
TA = –40ºC to 105ºC
Symbol Parameter
VCOFF
Input offset
TCPROP Propagation delay
IB
Input bias current
CMVR
Common-mode voltage
range
ICC
Supply current
Electrical Characteristics
Minimum
Typical
—
5
—
200
Maximum Units Conditions
–0.3
40
PRELIMINARY
15
mV
VDD = 3.3 V;
VIN = VDD ÷ 2.
ns
Vcomm mode =1V
Vdiff=100mV
1
µA
VDD – 1
V
µA
VDD = 3.6V.
PS024604-1005
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Product Specification
269
Table 147. Comparator Electrical Characteristics (Continued)
(Continued) = 2.7–3.6V
TA = –40ºC to 105ºC
Minimum
Symbol Parameter
Twup
Typical
Maximum Units Conditions
Wake up time from off
state
5
µs
CINP = 0.9V
CINN= 1.0V
Table 148 provides electrical characteristics and timing information for the on-chip Operational Amplifier.
Table 148. Operational Amplifier Electrical Characteristics
= 2.7–3.6V
TA = –40ºC to 105ºC
Symbol Parameter
Minimum
Typical
Maximum Units Conditions
VOS
Input offset
5
TCVOS
Input offset Average Drift
1
µV/C
IB
Input bias current
TBD
uA
IOS
Input offset current
TBD
uA
CMVR
Common-Mode Voltage
Range
VOL
Output low
VOH
Output high
CMRR
Common-Mode Rejection
Ratio
PSRR
mV
VDD =3.3 V;
VCM = VDD ÷ 2.
VDD – 1
V
0.1
V
ISINK = 100 µA.
V
ISOURCE = 100 µA.
70
dB
0 < VCM < 1.4V;
TA = 25ºC.
Power Supply Rejection
Ratio
80
dB
VDD = 2.7 V – 3.6 V;
TA = 25ºC.
AVOL
Voltage Gain
80
dB
SR+
Slew Rate while rising
12
V/us
PS024604-1005
–0.3
15
VDD – 1
PRELIMINARY
RLOAD = 33 K;
CLOAD = 50 pF;
AVCL = 1,
VIN = 0.7 V to 1.7 V.
On-Chip Peripheral AC and DC Electrical
Z8 Encore!® Motor Control Flash MCUs
Product Specification
270
Table 148. Operational Amplifier Electrical Characteristics (Continued)
(Continued) = 2.7–3.6V
TA = –40ºC to 105ºC
Symbol Parameter
Minimum
Typical
Maximum Units Conditions
SR–
Slew Rate while falling
GBW
Gain-Bandwidth Product
FM
Phase Margin
IS
Supply Current
1
mA
TWUP
Wake up time from off
state
20
us
Electrical Characteristics
16
V/us
5
RLOAD = 33 K;
CLOAD = 50 pF;
AVCL = 1,
VIN = 1.7 V to 0.7 V.
MHz
50
PRELIMINARY
degree
VDD = 3.6V;
VOUT= VDD ÷ 2.
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271
General Purpose I/O Port Input Data Sample Timing
Figure 51 illustrates the timing of the GPIO Port input sampling. Table 149 lists the GPIO
port input timing.
TCLK
System
Clock
GPIO Pin
Input Value
Port Value
Changes to 0
GPIO Input
Data Latch
0 Latched
into Port Input
Data Register
GPIO Data Register
Value 0 Read
by eZ8 CPU
GPIO Data
Read on Data Bus
Figure 51. Port Input Sample Timing
Table 149 and Table 150 provide timing information for the GPIO Port inputs and outputs.
Table 149. GPIO Port Input Timing
Delay (ns)
PS024604-1005
Parameter
Abbreviation
Min
Max
TS_PORT
Port input transition to XIN fall setup time
(Not pictured)
5
—
TH_PORT
XIN fall to port input transition hold time (not pictured).
5
—
TSMR
GPIO port pin pulse width to ensure Stop-Mode
Recovery (for GPIO port pins enabled as SMR
sources) .
PRELIMINARY
1 µs
General Purpose I/O Port Input Data Sample
Z8 Encore!® Motor Control Flash MCUs
Product Specification
272
General Purpose I/O Port Output Timing
Figure 52 and Table 150 provide timing information for the GPIO port pins.
TCLK
XIN
Port Output
T1
T2
Figure 52. GPIO Port Output Timing
Table 150. GPIO Port Output Timing
Delay (ns)
Parameter
Abbreviation
T1
T2
Electrical Characteristics
Minimum
Maximum
XIN Rise to Port Output Valid Delay
—
15
XIN Rise to Port Output Hold Time
2
—
PRELIMINARY
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Product Specification
273
On-Chip Debugger Timing
Figure 53 and Table 151 provide timing information for the DBG pin. The DBG pin timing specifications assume a 4 µs maximum rise and fall time.
TCLK
XIN
DBG Output
Output Data
T1
T2
DBG Input
Input Data
T3
T4
Figure 53. On-Chip Debugger Timing
Table 151. On-Chip Debugger Timing
Delay (ns)
Parameter
Abbreviation
Minimum
Maximum
T1
XIN Rise to DBG Valid Delay
—
15
T2
XIN Rise to DBG Output Hold Time
2
—
T3
DBG to XIN Rise Input Setup Time
10
—
T4
DBG to XIN Rise Input Hold Time
5
—
DBG Frequency
PS024604-1005
PRELIMINARY
System
Clock ÷ 4
On-Chip Debugger Timing
Z8 Encore!® Motor Control Flash MCUs
Product Specification
274
UART Timing
Figure 54 and Table 152 provide timing information for UART pins for the case where the
Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that
the Driver Enable polarity has been configured to be Active Low and is represented here
by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data Register
has been loaded with data prior to CTS assertion.
CTS
(Input)
¥¥¥
T1
DE
(Output)
¥¥¥
T2
TxD
(Output)
T3
Start Bit 0
Bit 1 ¥ ¥ ¥
Bit 7 Parity Stop
End of
Stop Bit(s)
Figure 54. UART Timing with CTS
Table 152. UART Timing with CTS
Delay (ns)
Parameter
Abbreviation
T1
CTS fall to DE assertion delay
T2
DE assertion to TxD falling edge (start)
delay
T3
End of stop bit(s) to DE deassertion delay
Electrical Characteristics
PRELIMINARY
Minimum
Maximum
2 x XIN period
2 x XIN period
+ 1 bit period
1 bit period
1 bit period +
1 x XIN period
1 x XIN period
2 x XIN period
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
275
Figure 55 and Table 153 provide timing information for UART pins for the case where the
Clear To Send input signal (CTS) is not used for flow control. In this example, it is
assumed that the Driver Enable polarity has been configured to be Active Low and is represented here by DE. DE asserts after the UART Transmit Data Register has been written.
DE remains asserted for multiple characters as long as the Transmit Data Register is written with the next character before the current character has completed.
DE
(Output)
¥¥¥
T1
TxD
(Output)
T2
Start Bit 0
Bit 1 ¥ ¥ ¥
Bit 7 Parity Stop
End of
Stop Bit(s)
Figure 55. UART Timing without CTS
Table 153. UART Timing without CTS
Delay (ns)
PS024604-1005
Parameter
Abbreviation
Minimum
Maximum
T1
DE assertion to TxD falling edge (start)
delay
1 bit period
1 bit period +
1 x XIN period
T2
End of stop bit(s) to DE deassertion delay
1 x XIN period
2 x XIN period
PRELIMINARY
UART Timing
Z8 Encore!® Motor Control Flash MCUs
Product Specification
276
Electrical Characteristics
PRELIMINARY
PS024604-1005
Z8FMC16100 Series Flash MCU
Product Specification
277
eZ8 CPU Instruction Set
This chapter describes how to use the eZ8 CPU.
Assembly Language Programming Introduction
The eZ8 CPU assembly language provides a means for writing an application program
without concern for actual memory addresses or machine instruction formats. A program
written in assembly language is called a source program. Assembly language allows the
use of symbolic addresses to identify memory locations. It also allows mnemonic codes
(Op Codes and operands) to represent the instructions themselves. The Op Codes identify
the instruction while the operands represent memory locations, registers, or immediate
data values.
Each assembly language program consists of a series of symbolic commands called statements. Each statement can contain labels, operations, operands and comments.
Labels can be assigned to a particular instruction step in a source program. The label identifies that step in the program as an entry point for use by other instructions.
The assembly language also includes assembler directives that supplement the machine
instruction. The assembler directives, or pseudo-ops, are not translated into a machine
instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the
assembly process.
The source program is processed (assembled) by the assembler to obtain a machine language program called the object code. The object code is executed by the eZ8 CPU. An
example segment of an assembly language program is detailed in the code below.
Assembly Language Source Program Example
JP START
; Everything after the semicolon is a comment.
START:
; A label called START. The first instruction (JP
START) in this
; example causes program execution to jump to the
point within the
; program where the START label occurs.
LD R4, R7
; A Load (LD) instruction with two operands. The
first operand,
; Working Register R4, is the destination. The
second operand,
PS024604-1005
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eZ8 CPU Instruction Set
Z8 Encore!® Motor Control Flash MCUs
Product Specification
278
; Working Register R7, is the source. The contents
of R7 is
; written into R4.
LD 234H, #%01
; Another Load (LD) instruction with two operands.
; The first operand, Extended Mode Register Address
234H,
; identifies the destination. The second operand,
Immediate Data
; value 01h, is the source. The value 01h is
written into the
; Register at address 234h.
Assembly Language Syntax
For proper instruction execution, eZ8 CPU assembly language syntax requires that the
operands be written as ‘destination, source’. After assembly, the object code usually has
the operands in the order ’source, destination’, but ordering is Op Code-dependent. The
following instruction examples illustrate the format of some basic assembly instructions
and the resulting object code produced by the assembler. This binary format must be followed by users that prefer manual program coding or intend to implement their own
assembler.
Example 1. If the contents of registers 43h and 08h are added and the result is stored in
43h, the assembly syntax and resulting object code is:
Assembly Language Code
Object Code
ADD
43H,
08h
(ADD dst, src)
04
08
43
(OPC src, dst)
Example 2. In general, when an instruction format requires an 8-bit register address, that
address can specify any register location in the range 0–255 or, using Escaped Mode
Addressing in working registers R0–R15. If the contents of Register 43h and Working
Register R8 are added and the result is stored in 43h, the assembly syntax and resulting
object code is:
Assembly Language Code
Object Code
PS024604-1005
ADD
43H,
R8
(ADD dst, src)
04
E8
43
(OPC src, dst)
PRELIMINARY
eZ8 CPU Instruction Set
Z8FMC16100 Series Flash MCU
Product Specification
279
Note:
The size of the register file varies depending upon device type. The register file is 512
bytes for the Z8FMC16100 Series Flash MCU.
eZ8 CPU Instruction Notation
In the eZ8 CPU Instruction Summary and Description sections, the operands, condition
codes, status flags, and address modes are represented by a notational shorthand that is
described in Table 154.
.
Table 154. Notational Shorthand
Notation Description
Operand Range
b
Bit
b
b represents a value from 0 to 7 (000b to 111b).
cc
Condition Code
—
See Condition Codes overview in the eZ8 CPU
User Manual (UM0128).
DA
Direct Address
Addrs
Addrs represents a number in the range of 0000h
to FFFFh.
ER
Extended Addressing Register Reg
Reg. represents a number in the range of 000h to
FFFh.
IM
Immediate Data
#Data
Data is a number between 00h to FFh.
Ir
Indirect Working Register
@Rn
n = 0 –15.
IR
Indirect Register
@Reg
Reg. represents a number in the range of 00h to
FFh.
Irr
Indirect Working Register Pair
@RRp
p = 0, 2, 4, 6, 8, 10, 12, or 14.
IRR
Indirect Register Pair
@Reg
Reg. represents an even number in the range 00h
to FEh.
p
Polarity
p
Polarity is a single bit binary value of either 0b or
1b.
r
Working Register
Rn
n = 0–15.
R
Register
Reg
Reg. represents a number in the range of 00h to
FFh.
RA
Relative Address
X
X represents an index in the range of +127 to
–128, which is an offset relative to the address of
the next instruction.
rr
Working Register Pair
RRp
p = 0, 2, 4, 6, 8, 10, 12, or 14.
RR
Register Pair
Reg
Reg. represents an even number in the range of
00h to FEh.
PS024604-1005
PRELIMINARY
eZ8 CPU Instruction Set
Z8 Encore!® Motor Control Flash MCUs
Product Specification
280
Table 154. Notational Shorthand (Continued)
Notation Description
Operand Range
Vector
Vector Address
Vector
Vector represents a number in the range of 00h to
FFh.
X
Indexed
#Index
The register or register pair to be indexed is offset
by the signed Index value (#Index) in a +127 to –
128 range.
Table 155 contains additional symbols that are used throughout the Instruction Summary
and Instruction Set Description sections.
Table 155. Additional Symbols
Symbol
Definition
dst
Destination Operand
src
Source Operand
@
Indirect Address Prefix
SP
Stack Pointer
PC
Program Counter
FLAGS
Flags Register
RP
Register Pointer
#
Immediate Operand Prefix
B
Binary Number Suffix
%
Hexadecimal Number
Prefix
H
Hexadecimal Number
Suffix
Assignment of a value is indicated by an arrow. For example,
dst ← dst + src
indicates the source data is added to the destination data and the result is stored in the destination location.
PS024604-1005
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eZ8 CPU Instruction Set
Z8FMC16100 Series Flash MCU
Product Specification
281
Condition Codes
The C, Z, S, and V flags control the operation of the conditional jump (JP cc and JR cc)
instructions. Sixteen frequently-useful functions of the flag settings are encoded in a 4-bit
field called the condition code (cc), which forms Bits 7:4 of the conditional jump instructions. Table 156 summarizes the condition codes. Some binary condition codes can be created using more than one assembly code mnemonic. The result of the flag test operation
decides whether the conditional jump is executed.
Table 156. Condition Codes
PS024604-1005
Binary
Hex
Assembly
Mnemonic
Definition
Flag Test Operation
0000
0
F
Always False
—
0001
1
LT
Less Than
(S XOR V) = 1
0010
2
LE
Less Than or Equal
(Z or (S XOR V)) = 1
0011
3
ULE
Unsigned Less Than or Equal (C OR Z) = 1
0100
4
OV
Overflow
V=1
0101
5
Ml
Minus
S=1
0110
6
Z
Zero
Z=1
0110
6
EQ
Equal
Z=1
0111
7
C
Carry
C=1
0111
7
ULT
Unsigned Less Than
C=1
1000
8
T (or blank)
Always True
—
1001
9
GE
Greater Than or Equal
(S XOR V) = 0
1010
A
GT
Greater Than
(Z OR (S XOR V)) = 0
1011
B
UGT
Unsigned Greater Than
(C = 0 AND Z = 0) = 1
1100
C
NOV
No Overflow
V=0
1101
D
PL
Plus
S=0
1110
E
NZ
Non-Zero
Z=0
1110
E
NE
Not Equal
Z=0
1111
F
NC
No Carry
C=0
1111
F
UGE
Unsigned Greater Than or
Equal
C=0
PRELIMINARY
eZ8 CPU Instruction Set
Z8 Encore!® Motor Control Flash MCUs
Product Specification
282
eZ8 CPU Instruction Classes
eZ8 CPU instructions can be divided functionally into the following groups:
•
•
•
•
•
•
•
•
Arithmetic
Bit Manipulation
Block Transfer
CPU Control
Load
Logical
Program Control
Rotate and Shift
Tables 157 through 164 contain the instructions belonging to each group and the number
of operands required for each instruction. Some instructions appear in more than one table
as these instruction can be considered as a subset of more than one category. Within these
tables, the source operand is identified as src, the destination operand is dst and a condition code is cc.
Table 157. Arithmetic Instructions
PS024604-1005
Mnemonic
Operands
Instruction
ADC
dst, src
Add with Carry
ADCX
dst, src
Add with Carry using extended addressing
ADD
dst, src
Add
ADDX
dst, src
Add using extended addressing
CP
dst, src
Compare
CPC
dst, src
Compare with Carry
CPCX
dst, src
Compare with Carry using extended addressing
CPX
dst, src
Compare using extended addressing
DA
dst
Decimal Adjust
DEC
dst
Decrement
DECW
dst
Decrement Word
INC
dst
Increment
INCW
dst
Increment Word
PRELIMINARY
eZ8 CPU Instruction Set
Z8FMC16100 Series Flash MCU
Product Specification
283
Table 157. Arithmetic Instructions (Continued)
Mnemonic
Operands
Instruction
MULT
dst
Multiply
SBC
dst, src
Subtract with Carry
SBCX
dst, src
Subtract with Carry using extended addressing
SUB
dst, src
Subtract
SUBX
dst, src
Subtract using extended addressing
Table 158. Bit Manipulation Instructions
Mnemonic
Operands
Instruction
BCLR
bit, dst
Bit Clear
BIT
p, bit, dst
Bit Set or Clear
BSET
bit, dst
Bit Set
BSWAP
dst
Bit Swap
CCF
—
Complement Carry Flag
RCF
—
Reset Carry Flag
SCF
—
Set Carry Flag
TCM
dst, src
Test Complement Under Mask
TCMX
dst, src
Test Complement Under Mask using extended
addressing
TM
dst, src
Test Under Mask
TMX
dst, src
Test Under Mask using extended addressing
Table 159. Block Transfer Instructions
PS024604-1005
Mnemonic
Operands
Instruction
LDCI
dst, src
Load Constant to/from program memory and
autoincrement addresses
LDEI
dst, src
Load External Data to/from data memory and
autoincrement addresses
PRELIMINARY
eZ8 CPU Instruction Set
Z8 Encore!® Motor Control Flash MCUs
Product Specification
284
Table 160. CPU Control Instructions
Mnemonic
Operands
Instruction
CCF
—
Complement Carry Flag
DI
—
Disable Interrupts
EI
—
Enable Interrupts
HALT
—
HALT Mode
NOP
—
No Operation
RCF
—
Reset Carry Flag
SCF
—
Set Carry Flag
SRP
src
Set Register Pointer
STOP
—
STOP mode
WDT
—
Watch-Dog Timer Refresh
Table 161. Load Instructions
PS024604-1005
Mnemonic
Operands
Instruction
CLR
dst
Clear
LD
dst, src
Load
LDC
dst, src
Load Constant to/from program memory
LDCI
dst, src
Load Constant to/from program memory and
autoincrement addresses
LDE
dst, src
Load External Data to/from data memory
LDEI
dst, src
Load External Data to/from data memory and
autoincrement addresses
LDWX
dst, src
Load Word using extended addressing
LDX
dst, src
Load using extended addressing
LEA
dst, X(src)
Load Effective Address
POP
dst
Pop
POPX
dst
Pop using extended addressing
PUSH
src
Push
PUSHX
src
Push using extended addressing
PRELIMINARY
eZ8 CPU Instruction Set
Z8FMC16100 Series Flash MCU
Product Specification
285
Table 162. Logical Instructions
Mnemonic
Operands
Instruction
AND
dst, src
Logical AND
ANDX
dst, src
Logical AND using extended addressing
COM
dst
Complement
OR
dst, src
Logical OR
ORX
dst, src
Logical OR using extended addressing
XOR
dst, src
Logical Exclusive OR
XORX
dst, src
Logical Exclusive OR using extended addressing
Table 163. Program Control Instructions
Mnemonic
Operands
Instruction
ATM
—
Atomic
BRK
—
On-Chip Debugger Break
BTJ
p, bit, src, DA
Bit Test and Jump
BTJNZ
bit, src, DA
Bit Test and Jump if Non-Zero
BTJZ
bit, src, DA
Bit Test and Jump if Zero
CALL
dst
Call Procedure
DJNZ
dst, src, RA
Decrement and Jump Non-Zero
IRET
—
Interrupt Return
JP
dst
Jump
JP cc
dst
Jump Conditional
JR
DA
Jump Relative
JR cc
DA
Jump Relative Conditional
RET
—
Return
TRAP
vector
Software Trap
Table 164. Rotate and Shift Instructions
PS024604-1005
Mnemonic
Operands
Instruction
BSWAP
dst
Bit Swap
RL
dst
Rotate Left
PRELIMINARY
eZ8 CPU Instruction Set
Z8 Encore!® Motor Control Flash MCUs
Product Specification
286
Table 164. Rotate and Shift Instructions (Continued)
Mnemonic
Operands
Instruction
RLC
dst
Rotate Left through Carry
RR
dst
Rotate Right
RRC
dst
Rotate Right through Carry
SRA
dst
Shift Right Arithmetic
SRL
dst
Shift Right Logical
SWAP
dst
Swap Nibbles
eZ8 CPU Instruction Summary
Table 165 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags Register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
.
Table 165. eZ8 CPU Instruction Summary
Address
Mode
Assembly
Mnemonic
Symbolic Operation
ADC dst, src
dst ← dst + src + C
ADCX dst, src
dst ← dst + src + C
dst src
Op
Code(s)
(Hex)
C
Z
S
V
Fetch
Instr.
D H Cycles Cycles
*
*
*
*
0
r
r
12
r
Ir
R
Flags
2
3
13
2
4
R
14
3
3
R
IR
15
3
4
R
IM
16
3
3
IR
IM
17
3
4
ER
ER
18
4
3
ER
IM
19
4
3
*
*
*
*
0
*
*
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
PRELIMINARY
eZ8 CPU Instruction Set
Z8FMC16100 Series Flash MCU
Product Specification
287
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Assembly
Mnemonic
Symbolic Operation
ADD dst, src
dst ← dst + src
ADDX dst, src
AND dst, src
ANDX dst, src
dst ← dst + src
dst ← dst + src
dst ← dst AND src
ATM
Atomic execution
BCLR bit, dst
dst[bit] ← 0
BIT p, bit, dst
dst[bit] ← p
BRK
Debugger Break
BSET bit, dst
dst[bit] ← 1
BSWAP dst
dst[7:0] ← dst[0:7]
BTJ p, bit, src,
dst
if src[bit] = p
PC ← PC + X
dst src
Op
Code(s)
(Hex)
C
Z
S
V
Fetch
Instr.
D H Cycles Cycles
*
*
*
*
0
r
r
02
r
Ir
R
Flags
2
3
03
2
4
R
04
3
3
R
IR
05
3
4
R
IM
06
3
3
IR
IM
07
3
4
ER
ER
08
4
3
ER
IM
09
4
3
r
r
52
2
3
r
Ir
53
2
4
R
R
54
3
3
R
IR
55
3
4
R
IM
56
3
3
IR
IM
57
3
4
ER
ER
58
4
3
ER
IM
59
4
3
*
—
—
*
*
*
*
*
*
*
0
*
*
0 — —
0 — —
2F
— — — — — —
1
1
r
E2
—
*
*
0 — —
2
2
r
E2
—
*
*
0 — —
2
2
00
— — — — — —
1
1
r
E2
—
*
*
0 — —
2
2
R
D5
X
*
*
0
2
2
r
F6
— — — — — —
3
3
Ir
F7
3
4
-
-
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
PRELIMINARY
eZ8 CPU Instruction Set
Z8 Encore!® Motor Control Flash MCUs
Product Specification
288
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Assembly
Mnemonic
Symbolic Operation
BTJNZ bit, src,
dst
if src[bit] = 1
PC ← PC + X
BTJZ bit, src,
dst
if src[bit] = 0
PC ← PC + X
CALL dst
SP ← SP – 2
@SP ← PC
PC ← dst
CCF
C ← ~C
CLR dst
dst ← 00h
COM dst
CP dst, src
CPC dst, src
dst ← ~dst
dst – src
dst – src – C
dst src
Op
Code(s)
(Hex)
r
F6
Ir
F7
r
F6
Ir
F7
IRR
D4
DA
D6
EF
R
B0
IR
B1
R
60
IR
61
Flags
C
Z
S
V
Fetch
Instr.
D H Cycles Cycles
— — — — — —
3
3
3
4
3
3
3
4
2
6
3
3
— — — — —
1
2
— — — — — —
2
2
2
3
2
2
2
3
2
3
— — — — — —
— — — — — —
*
—
*
*
r
A2
r
Ir
A3
2
4
R
R
A4
3
3
R
IR
A5
3
4
R
IM
A6
3
3
IR
IM
A7
3
4
r
r
1F A2
3
3
r
Ir
1F A3
3
4
R
R
1F A4
4
3
R
IR
1F A5
4
4
R
IM
1F A6
4
3
IR
IM
1F A7
4
4
*
*
0 — —
r
*
*
*
*
*
*
— —
— —
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
PRELIMINARY
eZ8 CPU Instruction Set
Z8FMC16100 Series Flash MCU
Product Specification
289
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Code(s)
(Hex)
C
Z
S
V
Fetch
Instr.
D H Cycles Cycles
ER
1F A8
*
*
*
*
— —
ER
IM
1F A9
ER
ER
A8
ER
IM
A9
Assembly
Mnemonic
Symbolic Operation
dst src
CPCX dst, src
dst – src – C
ER
CPX dst, src
DA dst
DEC dst
DECW dst
dst – src
dst ← DA(dst)
dst ← dst – 1
dst ← dst – 1
DI
IRQE ← 0
DJNZ dst, RA
dst ← dst – 1
if dst ≠ 0
PC ← PC + X
EI
R
40
IR
41
R
30
IR
31
RR
80
IRR
81
Flags
*
*
—
—
*
*
*
*
*
*
*
*
*
— —
X — —
*
*
v —
— —
5
3
5
3
4
3
4
3
2
2
2
3
2
2
2
3
2
5
2
6
8F
— — — — — —
1
2
0A–FA
— — — — — —
2
3
IRQE ← 1
9F
— — — — — —
1
2
HALT
HALT Mode
7F
— — — — — —
1
2
INC dst
dst ← dst + 1
R
20
—
2
2
IR
21
2
3
r
0E–FE
1
2
RR
A0
2
5
IRR
A1
2
6
1
5
INCW dst
IRET
dst ← dst + 1
r
FLAGS ← @SP
SP ← SP + 1
PC ← @SP
SP ← SP + 2
IRQE ← 1
BF
—
*
*
*
*
*
*
*
*
*
*
— —
— —
*
*
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
PRELIMINARY
eZ8 CPU Instruction Set
Z8 Encore!® Motor Control Flash MCUs
Product Specification
290
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Code(s)
(Hex)
Assembly
Mnemonic
Symbolic Operation
dst src
JP dst
PC ← dst
DA
8D
IRR
C4
Flags
C
Z
S
V
Fetch
Instr.
D H Cycles Cycles
— — — — — —
3
2
2
3
JP cc, dst
if cc is true
PC ← dst
DA
0D–FD
— — — — — —
3
2
JR dst
PC ← PC + X
DA
8B
— — — — — —
2
2
JR cc, dst
if cc is true
PC ← PC + X
DA
0B–FB
— — — — — —
2
2
LD dst, rc
dst ← src
— — — — — —
2
2
LDC dst, src
LDCI dst, src
LDE dst, src
dst ← src
dst ← src
r←r+1
rr ← rr + 1
dst ← src
r
IM
0C–FC
r
X(r)
C7
3
3
X(r)
r
D7
3
4
r
Ir
E3
2
3
R
R
E4
3
2
R
IR
E5
3
4
R
IM
E6
3
2
IR
IM
E7
3
3
Ir
r
F3
2
3
IR
R
F5
3
3
r
Irr
C2
2
5
Ir
Irr
C5
2
9
Irr
r
D2
2
5
Ir
Irr
C3
2
9
Irr
Ir
D3
2
9
r
Irr
82
2
5
Irr
r
92
2
5
— — — — — —
— — — — — —
— — — — — —
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
PRELIMINARY
eZ8 CPU Instruction Set
Z8FMC16100 Series Flash MCU
Product Specification
291
Table 165. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
LDEI dst, src
Address
Mode
Symbolic Operation
dst ← src
r←r+1
rr ← rr + 1
dst src
Op
Code(s)
(Hex)
Ir
Irr
83
Irr
Ir
93
Flags
C
Z
S
V
Fetch
Instr.
D H Cycles Cycles
— — — — — —
2
9
2
9
LDWX dst, src
dst ← src
ER
ER
1F E8
— — — — — —
5
4
LDX dst, src
dst ← src
r
ER
84
— — — — — —
3
2
Ir
ER
85
3
3
R
IRR
86
3
4
IR
IRR
87
3
5
r
X(rr)
88
3
4
X(rr)
r
89
3
4
ER
r
94
3
2
ER
Ir
95
3
3
IRR
R
96
3
4
IRR
IR
97
3
5
ER
ER
E8
4
2
ER
IM
E9
4
2
r
X(r)
98
3
3
rr
X(rr)
99
3
5
LEA dst, X(src)
dst ← src + X
MULT dst
dst[15:0] ←
dst[15:8] * dst[7:0]
NOP
No operation
RR
— — — — — —
F4
— — — — — —
2
8
0F
— — — — — —
1
2
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
PRELIMINARY
eZ8 CPU Instruction Set
Z8 Encore!® Motor Control Flash MCUs
Product Specification
292
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Assembly
Mnemonic
Symbolic Operation
OR dst, src
dst ← dst OR src
ORX dst, src
POP dst
dst ← dst OR src
dst ← @SP
SP ← SP + 1
dst src
Op
Code(s)
(Hex)
C
Z
S
V
—
*
*
0 — —
r
r
42
r
Ir
R
Flags
Fetch
Instr.
D H Cycles Cycles
2
3
43
2
4
R
44
3
3
R
IR
45
3
4
R
IM
46
3
3
IR
IM
47
3
4
ER
ER
48
4
3
ER
IM
49
4
3
2
2
2
3
R
50
IR
51
—
*
*
0 — —
— — — — — —
POPX dst
dst ← @SP
SP ← SP + 1
ER
D8
— — — — — —
3
2
PUSH src
SP ← SP – 1
@SP ← src
R
70
— — — — — —
2
2
IR
71
2
3
IM
1F 70
3
2
ER
C8
— — — — — —
3
2
PUSHX src
SP ← SP – 1
@SP ← src
RCF
C←0
CF
0 — — — — —
1
2
RET
PC ← @SP
SP ← SP + 2
AF
— — — — — —
1
4
2
2
2
3
2
2
2
3
RL dst
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
RLC dst
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
R
90
IR
91
R
10
IR
11
*
*
*
*
*
*
*
*
— —
— —
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
PRELIMINARY
eZ8 CPU Instruction Set
Z8FMC16100 Series Flash MCU
Product Specification
293
Table 165. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
Address
Mode
Symbolic Operation
RR dst
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
RRC dst
D7 D6 D5 D4 D3 D2 D1 D0
dst
SBC dst, src
SBCX dst, src
SCF
C
dst ← dst – src – C
dst ← dst – src – C
C
Z
S
V
Fetch
Instr.
D H Cycles Cycles
R
E0
*
*
*
*
— —
IR
E1
R
C0
IR
C1
dst src
0
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
SRP src
RP ← src
STOP
STOP mode
Flags
*
*
*
2
2
3
2
3
33
2
4
R
R
34
3
3
R
IR
35
3
4
R
IM
36
3
3
IR
IM
37
3
4
ER
ER
38
4
3
ER
IM
39
4
3
1
*
2
Ir
*
1
3
r
*
*
— —
2
32
*
*
*
2
r
*
*
*
2
r
C←1
SRA dst
SRL dst
Op
Code(s)
(Hex)
*
DF
1 — — — — —
1
2
R
D0
*
2
2
IR
D1
2
3
R
1F C0
3
2
IR
1F C1
3
3
IM
*
*
*
*
0
0 — —
*
— —
01
— — — — — —
2
2
6F
— — — — — —
1
2
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
PRELIMINARY
eZ8 CPU Instruction Set
Z8 Encore!® Motor Control Flash MCUs
Product Specification
294
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Assembly
Mnemonic
Symbolic Operation
SUB dst, src
dst ← dst – src
SUBX dst, src
SWAP dst
TCM dst, src
TCMX dst, src
TM dst, src
dst ← dst – src
dst[7:4] ↔ dst[3:0]
(NOT dst) AND src
(NOT dst) AND src
dst AND src
dst src
Op
Code(s)
(Hex)
C
Z
S
V
Fetch
Instr.
D H Cycles Cycles
*
*
*
*
1
r
r
22
r
Ir
R
Flags
2
3
23
2
4
R
24
3
3
R
IR
25
3
4
R
IM
26
3
3
IR
IM
27
3
4
ER
ER
28
4
3
ER
IM
29
4
3
2
2
2
3
2
3
R
F0
IR
F1
*
X
—
*
*
*
1
*
X — —
r
62
r
Ir
63
2
4
R
R
64
3
3
R
IR
65
3
4
R
IM
66
3
3
IR
IM
67
3
4
ER
ER
68
4
3
ER
IM
69
4
3
r
r
72
2
3
r
Ir
73
2
4
R
R
74
3
3
R
IR
75
3
4
R
IM
76
3
3
IR
IM
77
3
4
—
*
*
*
*
r
—
*
*
*
*
*
0 — —
0 — —
0 — —
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
PRELIMINARY
eZ8 CPU Instruction Set
Z8FMC16100 Series Flash MCU
Product Specification
295
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Code(s)
(Hex)
C
Z
S
V
ER
78
—
*
*
0 — —
IM
79
Vect
or
F2
Assembly
Mnemonic
Symbolic Operation
dst src
TMX dst, src
dst AND src
ER
ER
TRAP Vector
SP ← SP – 2
@SP ← PC
SP ← SP – 1
@SP ← FLAGS
PC ← @Vector
WDT
XOR dst, src
XORX dst, src
dst ← dst XOR src
dst ← dst XOR src
Flags
Fetch
Instr.
D H Cycles Cycles
4
3
4
3
— — — — — —
2
6
5F
— — — — — —
1
2
—
2
3
r
r
B2
r
Ir
B3
2
4
R
R
B4
3
3
R
IR
B5
3
4
R
IM
B6
3
3
IR
IM
B7
3
4
ER
ER
B8
4
3
ER
IM
B9
4
3
—
*
*
*
*
0 — —
0 — —
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
Flags Register
The Flags Register contains the status information regarding the most recent arithmetic,
logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits
of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z,
and S) can be tested for use with conditional jump instructions. Two flags (H and D) cannot be tested and are used for Binary-Coded Decimal (BCD) arithmetic.
The two remaining bits, User Flags (F1 and F2), are available as general-purpose status
bits. User Flags are unaffected by arithmetic operations and must be set or cleared by
instructions. The User Flags cannot be used with conditional Jumps. They are undefined at
PS024604-1005
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eZ8 CPU Instruction Set
Z8 Encore!® Motor Control Flash MCUs
Product Specification
296
initial power-up and are unaffected by Reset. Figure 56 illustrates the flags and their bit
positions in the Flags Register.
Bit
7
C
Bit
0
Z
S
V
D
H F2 F1
Flags Register
User Flags
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
U = Undefined
Figure 56. Flags Register
Interrupts, the software trap (TRAP) instruction, and illegal instruction traps all write the
value of the Flags Register to the stack. Executing an Interrupt Return (IRET) instruction
restores the value saved on the stack into the Flags Register.
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Z8FMC16100 Series Flash MCU
Product Specification
297
Op Code Maps
Figure 57 and Table 166 provide descriptions of the Op Code map data and the abbreviations. Figures 58 and 59 provide information about each of the eZ8 CPU instructions.
Op Code
Lower Nibble
Fetch Cycles
Instruction Cycles
4
3.3
Op Code
Upper Nibble
CP
A
R2,R1
Second Operand
After Assembly
First Operand
After Assembly
Figure 57. Op Code Map Cell Description
Table 166. Op Code Map Abbreviations
Abbreviation
Description
Abbreviation
Description
b
Bit position
IRR
Indirect Register Pair
cc
Condition code
p
Polarity (0 or 1)
X
8-bit signed index or
displacement
r
4-bit Working Register
DA
Destination address
R
8-bit register
ER
Extended Addressing register
r1, R1, Ir1, Irr1, IR1,
rr1, RR1, IRR1, ER1
Destination address
IM
Immediate data value
r2, R2, Ir2, Irr2, IR2,
rr2, RR2, IRR2, ER2
Source address
Ir
Indirect Working Register
RA
Relative
IR
Indirect register
rr
Working Register Pair
Irr
Indirect Working Register Pair
RR
Register Pair
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0
0
1
2
3
4
5
Upper Nibble (Hex)
6
7
8
1
A
B
C
D
E
F
3
4
5
6
Lower Nibble (Hex)
7
8
9
1.1
2.2
2.3
2.4
3.3
3.4
3.3
3.4
BRK
SRP
ADD
ADD
ADD
ADD
ADD
ADD
IM
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
RLC
RLC
ADC
ADC
ADC
ADC
ADC
ADC
4.3
4.3
IR1,IM ER2,ER1 IM,ER1
A
2.3
ADDX ADDX DJNZ
4.3
4.3
ADCX ADCX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
IR1,IM ER2,ER1 IM,ER1
4.3
4.3
SUBX SUBX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
DEC
DEC
SBC
SBC
SBC
SBC
SBC
SBC
IR1,IM ER2,ER1 IM,ER1
4.3
r1,X
B
C
D
E
F
2.2
2.2
3.2
1.2
1.2
JR
LD
JP
INC
NOP
cc,X
r1,IM
cc,DA
r1
See 2nd
Op Code
Map
1.1
ATM
4.3
SBCX SBCX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
4.3
4.3
DA
DA
OR
OR
OR
OR
OR
OR
ORX
ORX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
POP
POP
AND
AND
AND
AND
AND
AND
IR1,IM ER2,ER1 IM,ER1
IR1,IM ER2,ER1 IM,ER1
4.3
4.3
ANDX ANDX
1.2
WDT
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
4.3
4.3
1.2
TM
TM
TM
TM
TM
TM
TMX
TMX
HALT
PUSH PUSH
R2
IR2
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.5
2.6
2.5
2.8
3.2
3.3
3.4
3.5
LDE
LDEI
LDX
LDX
LDX
LDX
r1,Irr2
Ir1,Irr2
r1,ER2
DECW DECW
RR1
9
2
IRR1
4.3
1.2
STOP
IR1,IM ER2,ER1 IM,ER1
3.4
3.4
LDX3
LDX3
Ir1,ER2 IRR2,R1 IRR2,IR1 r1,rr2,X
rr1,r2,X
2.2
2.3
2.5
2.8
3.2
3.3
3.4
3.5
3.3
RL
RL
LDE
LDEI
LDX
LDX
LDX
LDX
LEA
R1
IR1
r2,Irr1
Ir2,Irr1
r2,ER1
2.5
2.6
INCW INCW
4.3
TCMX TCMX
Ir2,ER1 R2,IRR1 IR2,IRR1 r1,r2,X
3.5
LEA3
1.2
DI
1.2
EI
rr1,rr2,X
2.3
2.4
3.3
3.4
3.3
3.4
4.3
4.3
1.4
CP
CP
CP
CP
CP
CP
CPX
CPX
RET
RR1
IRR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
IR1,IM ER2,ER1 IM,ER1
3.4
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
R1,IM
IR1,IM ER2,ER1 IM,ER1
4.3
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
2.2
2.3
2.5
2.8
2.8
3.4
RRC
RRC
LDC
LDCI
2.3
JP2
LDC
LD
PUSHX3
r1,r2,X
ER2
R1
IR1
r1,Irr2
Ir1,Irr2
IRR1
Ir1,Irr2
2.2
2.3
2.5
2.8
2.6
2.2
SRA
SRA
LDC
LDCI CALL2 BSWAP CALL
3.3
3.4
4.3
XORX XORX
3.3
1.2
RCF
3.3
LD
POPX3
ER1
1.5
IRET
1.2
SCF
R1
IR1
r2,Irr1
Ir2,Irr1
IRR1
R1
DA
r2,r1,X
2.2
2.3
2.2
2.3
3.2
3.3
3.3
3.4
4.2
4.2
1.2
RR
RR
BIT
LD
LD
LD
LD
LD
LDX
LDX
CCF
R1
IR1
p,b,r1
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.6
2.3
2.9
3.3
3.3
3.4
LD
MULT
LD
BTJ
BTJ
Ir1,r2
RR1
R2,IR1
p,b,r1,X
p,b,Ir1,X
SWAP SWAP TRAP
R1
IR1
Vector
IR1,IM ER2,ER1 IM,ER1
Figure 58. First Op Code Map
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PRELIMINARY
Op Code Maps
Z8FMC16100 Series Flash MCU
Product Specification
299
0
1
2
3
4
5
6
Lower Nibble (Hex)
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
Upper Nibble (Hex)
6
3.2
7
PUSH
IM
8
9
A
3.3
3.4
4.3
4.4
4.3
4.4
CPC
CPC
CPC
CPC
CPC
CPC
5.3
5.3
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
CPCX CPCX
B
C
3.2
3.3
SRL
SRL
R1
IR1
D
4.2
E
LDWX
ER2,ER1
F
Figure 59. Second Op Code Map After 1Fh
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Op Code Maps
Z8 Encore!® Motor Control Flash MCUs
Product Specification
300
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Op Code Maps
Z8FMC16100 Series Flash MCU
Product Specification
301
Packaging
Figure 60 illustrates the 32-pin quad flat no lead (QFN) package available for the
Z8FMC16100 Series Flash MCU.
Figure 60. 32-Pin Quad Flat No Lead Package
Figure 61 illustrates the 32-pin low quad flat package (LQFP) available for the
Z8FMC16100 Series Flash MCU.
Figure 61. 32-Pin Low Quad Flat Package
PS024604-1005
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Packaging
Z8 Encore!® Motor Control Flash MCUs
Product Specification
302
Ordering Information
Table 167 identifies the basic features available for each device within the Z8FMC16100
Series Flash MCU product line. Table 168 provides ordering information for these products by part number. See the Part Number Description section on page 304 for a description of a part number’s unique identifying attributes.
Table 167. Z8FMC16100 Series Part Selection Guide
Product Feature
Z8FMC16100
Z8FMC08100
Z8FMC04100
Flash (KB)
16
8
4
SRAM (B)
512
512
512
General-Purpose I/O
17
17
17
Motor Control PWM Channels
6
6
6
ADC Inputs
8
8
8
Operational Amplifier
Yes
Yes
Yes
Comparator
Yes
Yes
Yes
16-bit Standard Timers w/ Capture, Compare, PWM
Yes
Yes
Yes
UART with support for LIN, and IrDA
Yes
Yes
Yes
I2C or SPI Controller
Yes
Yes
Yes
Watch-Dog Timer
Yes
Yes
Yes
5.5296 MHz Internal Precision Oscillator
Yes
Yes
Yes
Z8FMC16100
Yes
Yes
Yes
Each of the parts listed in Table 168 is shown in a lead-free package. The use of lead-free
packaging adheres to a socially responsible environmental standard. To order the standard
plastic (lead-soldered) package, please contact ZiLOG Customer Service.
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Ordering Information
Z8FMC16100 Series Flash MCU
Product Specification
303
Table 168. Ordering Information for the Z8FMC16100 Series Products*
Max.
Flash KB SRAM
Speed
(Bytes) Bytes GPIO (MHz)
Part Number
I2C/SPI
Trimmed
IPO
Package
Temp (ºC)
Z8FMC16100 with 16 KB Flash and 512 B SRAM
Z8FMC16100QKSG
Z8FMC16100QKEG
Z8FMC16100AKSG
Z8FMC16100AKEG
16
(16,384)
16
(16,384)
512
17
20
I2C/SPI
Y
QFN-32
0 to +70
–40 to +105
512
17
20
2
I C/SPI
Y
LQFP-32
0 to +70
–40 to +105
Z8FMC08100 with 8 KB Flash and 512 B SRAM
Z8FMC08100QKSG
8 (8,192)
512
17
20
I2C/SPI
20
I2C/SPI
Y
QFN-32
Z8FMC08100QKEG
Z8FMC08100AKSG
0 to +70
–40 to +105
8 (8,192)
512
17
Y
LQFP-32
Z8FMC08100AKEG
0 to +70
–40 to +105
Z8FMC04100 with 4 KB Flash and 512 B SRAM
Z8FMC04100QKSG
4 (4,096)
512
17
20
I2C/SPI
20
I2C/SPI
Y
QFN-32
Z8FMC04100QKEG
Z8FMC04100AKSG
0 to +70
–40 to +105
4 (4,096)
512
17
Z8FMC04100AKEG
Y
LQFP-32
0 to +70
–40 to +105
Z8FMC16100 Series Development Kit
Z8FMC160100KIT
Z8FMC16100 Series Development Kit
Z8FMC161000ZEM
Z8 Encore! Z8FMC16100 Series In-Circuit Emulator Development Tool
ZUSBOPTSC01ZAC USB Opto-isolated Smart Cable Accessory Kit
*Note: Factory-programmed versions of the devices in this table are available upon request from ZiLOG.
Navigate your browser to ZiLOG’s website to order the Z8FMC16100 Series Flash MCU.
Or, contact your local ZiLOG Sales Office. ZiLOG provides additional assistance on its
Customer Service page, and is also here to help with Technical Support issues. For
ZILOG’s valuable development tools and downloadable software, visit the ZiLOG website.
PS024604-1005
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Ordering Information
Z8 Encore!® Motor Control Flash MCUs
Product Specification
304
Part Number Description
ZiLOG part numbers consist of a number of components, as indicated in the following
examples:
Z8
ZiLOG 8-bit microcontroller product
FMC
Flash Motor Controller
16
Memory size
100
Product family
Q
Package type
K
Pin count
S
Temperature
G
Environmental flow*
Note: *An environmental flow of G represents the leadfree packaging option.
Packages
A = LQFP
Q = QFN
Pin Count
K = 32 pins
Temperature
E = –40ºC to +105ºC
S = 0ºC to +70ºC
Environmental Flow
C = Plastic Standard
G = Lead-Free
Example
Part number Z8FMC16100QKSG is a 16-bit Flash Motor Controller with 16 KB Program
Memory in a QFN package with 32 pins, operating over a 0ºC to +70ºC temperature range
and built using lead-free solder.
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows
about this product at this time, but additional features or nonconformance with some
aspects of the document might be found, either by ZiLOG or its customers in the course of
further application and characterization work. In addition, ZiLOG cautions that delivery
might be uncertain at times due to start-up yield issues.
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Ordering Information
Z8FMC16100 Series Flash MCU
Product Specification
305
Document Information
Document Number Description
The Document Control Number that appears in the footer on each page of this document
contains unique identifying attributes, as indicated in the following table:
PS024604-1005
PS
Product Specification
0246
Unique Document Number
02
Revision Number
0605
Month and Year Published
PRELIMINARY
Document Information
Z8 Encore!® Motor Control Flash MCUs
Product Specification
306
Change Log
Rev
Date
Sections
01
April
2005
Original issue
02
August
2005
Revised GPIO count and packages. Updated Figure 60 on page 301.
Added 8K (FMC08100) and 4K (FMC04100) parts to the Z8FMC16100 Series Flash MCU
Features section on page 1, Block Diagram section on page 2, Program Memory section on
page 14, Program Memory chapter on page 211, and Ordering Information section on page
302 for CR 6264.
Added USB Opto-isolated Smart Cable Accessory Kit to Ordering Information section on page
302.
Removed Sample and Hold from Block Diagram section on page 2 and Ordering Information
section on page 302. Updated Figure 36 on page 200. Replaced “Current-Sense Sample and
Hold Control Register” section with Current Sense ADC Trigger Control Register section on
page 87.
Removed “Operational Amplifier” chapter for CR 6261.
Updated Z8FMC16100
Series Flash MCU Features section on page 1 for CR 6262.
Updated General-Purpose I/O chapter on page 35.
Updated Watch-Dog Timer chapter on page 63.
Updated Pulse-Width Modulator chapter on page 67.
Updated General-Purpose Timer chapter on page 91.
Updated I2C Master/Slave Controller chapter on page 163.
Updated Internal Precision Oscillator chapter on page 239.
Updated Electrical Characteristics chapter on page 257.
Updated all register tables throughout manual.
Added Appendix A—Register Tables on page 307.
Added the number of interrupts to Z8FMC16100 Series Flash
the Interrupt Controller chapter on page 51 for CR 6305.
MCU Features on page 1 and
Updated Table 108 on page 206, Table 109 on page 207, and Table 130 on page 233 for CR
6382.
03
Septem- Updated Figure 1 on page 2.
ber 2005
04
October
2005
PS024604-1005
Updated the Register File Address Map chapter on page 17. Updated Table 43 on page 76,
Table 54 on page 85, and Table 168 on page 303. Updated the Electrical Characteristics
chapter on page 257.
PRELIMINARY
Document Information
Z8FMC16100 Series Flash MCU
Product Specification
307
Appendix A—Register Tables
General Purpose RAM
Hex Addresses: 000–1FF
See Register File section on page 13.
Hex Addresses: 200–EFF
Reserved
Timer 0
Hex Address: F00
Timer 0 High Byte Register (T0H)
BITS
7
6
5
4
FIELD
TH
RESET
00H
R/W
R/W
ADDR
F00H
3
2
1
0
3
2
1
0
Hex Address: F01
Timer 0 Low Byte Register (T0L)
BITS
7
6
5
4
FIELD
TL
RESET
01H
R/W
R/W
ADDR
F01H
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Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
308
Hex Address: F02
Timer 0 Reload High Byte Register (T0RH)
BITS
7
6
5
4
FIELD
TRH
RESET
FFH
R/W
R/W
ADDR
F02H
3
2
1
0
3
2
1
0
3
2
1
0
Hex Address: F03
Timer 0 Reload Low Byte Register (T0RL)
BITS
7
6
5
4
FIELD
TRL
RESET
FF
R/W
R/W
ADDR
F03H
Hex Address: F04
Timer 0 PWM High Byte Register (T0PWMH)
BITS
7
6
5
4
FIELD
PWMH
RESET
00H
R/W
R/W
ADDR
F04H
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Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
309
Hex Address: F05
Timer 0 PWM Low Byte Register (T0PWML)
BITS
7
6
5
4
FIELD
PWML
RESET
00H
R/W
R/W
ADDR
F05H
3
2
1
0
3
2
1
0
Hex Address: F06
Timer 0 Control 0 Register (T0CTL0)
BITS
7
6
5
FIELD
TMODE[3]
TICONFIG
TINSEL
PWMD
INCAP
RESET
0
00
0
000
0
R/W
R/W
R/W
R/W
R/W
R
F06H
ADDR
Bit
Position
4
Value
(H)
[7]
TMODE[3]
PS024604-1005
Description
Timer Mode High Bit
This bit along with the TMODE[2:0] field in the T0CTL1 register determines the
operating mode of the timer. This is the most significant bit of the Timer mode
selection value. See the T0CTL1 register description for additional details.
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
310
Bit
Position
Value
(H)
[6–5]
TICONFIG
Description
Timer Interrupt Configuration—This field configures timer interrupt definitions.
These bits affect all modes. The effect per mode is explained below:
ONE SHOT, CONTINUOUS, COUNTER, PWM, COMPARE, DUAL PWM,
TRIGGERED ONE-SHOT, COMPARATOR COUNTER:
0x Timer interrupt occurs on reload.
10 Timer interrupts are disabled.
11 Timer Interrupt occurs on reload.
GATED:
0x Timer interrupt occurs on reload or inactive gate edge.
10 Timer interrupt occurs on inactive gate edge.
11 Timer interrupt occurs on reload.
CAPTURE, CAPTURE/COMPARE, CAPTURE RESTART:
0x Timer interrupt occurs on reload and capture.
10 Timer interrupt occurs on capture only.
11 Timer interrupt occurs on reload only
[4]
TINSEL
0
1
Timer Input Select
Timer input is the Timer input pin.
Timer input is the comparator output.
000
001
010
011
100
101
110
111
PWM Delay Value
This field is a programmable delay to control the number of additional system
clock cycles following a PWM or Reload compare before the Timer Output or the
Timer Output Complement is switched to the active state. This field ensures a
time gap between the deassertion of one PWM output to the assertion of its
complement.
No delay
2 cycles delay
4 cycles delay
8 cycles delay
16 cycles delay
32 cycles delay
64 cycles delay
128 cycles delay
0
Input Capture Event
Previous timer interrupt is not a result of a Timer Input Capture Event
1
Previous timer interrupt is a result of a Timer Input Capture Event.
[3–1]
PWMD
[0]
INCAP
PS024604-1005
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Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
311
Hex Address: F07
Timer 0 Control 1 Register (T0CTL1)
BITS
7
6
5
4
3
2
1
FIELD
TEN
TPOL
PRES
TMODE
RESET
0
0
000
000
R/W
R/W
R/W
R/W
R/W
0
F07H
ADDR
Bit
Position
Value
(H)
[7]
TEN
0
Timer Enable
Timer is disabled.
1
Timer enabled.
PS024604-1005
Description
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
312
Bit
Position
Value
(H)
[6]
TPOL
Description
Timer Input/Output Polarity
This bit is a function of the current operating mode of the timer. It determines the
polarity of the input and/or output signal. When the timer is disabled, the Timer
Output signal is set to the value of this bit.
ONE-SHOT mode–If the timer is enabled the Timer Output signal pulses
(changes state) for one system clock cycle after timer Reload.
CONTINUOUS mode–If the timer is enabled the Timer Output signal is
complemented after timer Reload.
COUNTER mode–If the timer is enabled the Timer Output signal is
complemented after timer reload.
0 = Count occurs on the rising edge of the Timer Input signal.
1 = Count occurs on the falling edge of the Timer Input signal.
PWM SINGLE OUTPUT mode–When enabled, the Timer Output is forced to
TPOL after PWM count match and forced back to TPOL after Reload.
CAPTURE mode–If the timer is enabled the Timer Output signal is
complemented after timer Reload.
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARE mode–The Timer Output signal is complemented after timer
Reload.
GATED mode–The Timer Output signal is complemented after timer Reload.
0 = Timer counts when the Timer Input signal is High and interrupts are
generated on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low and interrupts are
generated on the rising edge of the Timer Input.
CAPTURE/COMPARE mode–If the timer is enabled, the Timer Output signal is
complemented after timer Reload
0 = Counting starts on the first rising edge of the Timer Input signal. The current
count is captured on subsequent rising edges of the Timer Input signal.
1 = Counting starts on the first falling edge of the Timer Input signal. The
current count is captured on subsequent falling edges of the Timer Input signal.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
313
Bit
Position
Value
(H)
Description
PWM DUAL OUTPUT mode–If enabled, the Timer Output is set=TPOL after
PWM match and set=TPOL after Reload. If enabled the Timer Output
Complement takes on the opposite value of the Timer Output. The PWMD field
in the T0CTL1 register determines an optional added delay on the assertion
(Low to High) transition of both Timer Output and the Timer Output
Complement for deadband generation.
CAPTURE RESTART mode–If the timer is enabled the Timer Output signal is
complemented after timer Reload.
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARATOR COUNTER mode–If the timer is enabled the Timer Output
signal is complemented after timer Reload.
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
TRIGGERED ONE-SHOT mode–If the timer is enabled the Timer Output signal
is complemented after timer Reload.
0 = The timer triggers on a Low to High transition on the input.
1 = The timer triggers on a High to Low transition on the input.
[5–3]
PRES
000
001
010
011
100
101
110
111
PS024604-1005
The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7.
The prescaler is reset each time the Timer is disabled. This insures proper clock
division each time the Timer is restarted.
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
314
Bit
Position
Value
(H)
[2–0]
TMODE[2:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Description
This field along with the TMODE[3] bit in T0CTL0 register determines the
operating mode of the timer. TMODE[3:0] selects from the following modes:
ONE-SHOT mode
CONTINUOUS mode
COUNTER mode
PWM SINGLE OUTPUT mode
CAPTURE mode
COMPARE mode
GATED mode
CAPTURE/COMPARE mode
PWM DUAL OUTPUT mode
CAPTURE RESTART mode
COMPARATOR COUNTER mode
TRIGGERED ONE-SHOT mode
Hex Address: F08
ADC Timer Capture High Byte Register (ADCTCAP_H)
BITS
7
6
5
4
3
FIELD
ADCTCAPH
RESET
X
R/W
R
2
1
0
F08H
ADDR
Bit
Position
Value
(H)
[7:0]
00H–FFH ADC Timer Capture Count High Byte
The timer count is held in the data registers until the next ADC conversion is
started.
PS024604-1005
Description
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
315
Hex Address: F09
ADC Timer Capture Low Byte Register (ADCTCAP_L)
BITS
7
6
5
4
3
FIELD
ADCTCAPL
RESET
X
R/W
R
2
1
0
F09H
ADDR
Bit
Position
Value
(H)
Description
[7:0]
00H–FFH ADC Timer Capture Count Low Byte
The timer count is held in the data registers until the next ADC conversion is
started.
Hex Address: F0A–F1F
Reserved
Pulse-Width Modulator
Hex Address: F20
PWM Control 0 Register (PWMCTL0)
BITS
7
6
5
FIELD
PWMOFF
OUTCTL
ALIGN
RESET
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
PS024604-1005
4
3
2
1
0
READY
PWMEN
0
0
0
R/W
R/W
R/W
Reserved ADCTRIG Reserved
F20H
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
316
Bit
Position
Value
(H)
[7]
PWMOFF
0
Place PWM outputs in off-state
Disable modulator control of PWM pins. Outputs are in predefined off-state. This
is not dependent on the reload event.
1
Re-enable modulator control of PWM pins at next PWM reload event.
0
PWM Output Control
PWM outputs are controlled by the Pulse-Width Modulator.
[6]
OUTCTL
1
[5]
ALIGN
PWM outputs selectively disabled (set to off-state) according to values in the
OUTx bits of the PWMOUT register.
0
PWM Edge Alignment
PWM outputs are edge aligned.
1
PWM outputs are center aligned.
[4]
Reserved
[3]
ADCTRIG
Description
Reserved
ADC Trigger Enable
0
No ADC trigger pulses.
1
ADC trigger enabled.
[2]
Reserved
0
[1]
READY
0
PWM values (pre-scale, period, and duty cycle) are not ready. Do not use
values in holding registers at next PWM reload event
1
PWM values (pre-scale, period, and duty cycle) are ready. Transfer all values
from temporary holding registers to working registers at next PWM reload event.
[0]
PWMEN
Reserved
Values Ready for Next Reload Event
0
1
PS024604-1005
PWM Enable
Pulse-width modulator is disabled and enabled PWM output pins are forced to
default off-state. PWM master counter is stopped. Certain control registers may
only written in this state.
Pulse-width modulator is enabled and PWM output pins are enabled as outputs.
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
317
Hex Address: F21
PWM Control 1 Register (PWMCTL1)
BITS
7
6
5
4
3
2
1
0
FIELD
RLFREQ[1:0]
INDEN
Pol45
Pol23
Pol10
PRES[1:0]
RESET
00
0
0
0
0
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F21H
ADDR
Bit
Position
Value
(H)
[7:6]
RLFREQ[1:0]
00
01
10
11
[5]
INDEN
Description
Reload Event Frequency
This bit field is buffered. Changes to the reload event frequency takes effect at
the end of the current PWM period. Reads always return the bit values from the
temporary holding register.
PWM reload event occurs at the end of every PWM period.
PWM reload event occurs once every 2 PWM periods.
PWM reload event occurs once every 4 PWM periods.
PWM reload event occurs once every 8 PWM periods.
0
Independent PWM Mode Enable
This bit may only be altered when PWEN (PWMCTL0) cleared.
PWM outputs operate as 3 complementary pairs.
1
PWM outputs operate as 6 independent channels.
[4]
Pol2
1
Invert Output polarity for channel pair PWM2.
0
Non-inverted polarity for channel pair PWM2.
[3]
Pol1
1
Invert Output polarity for channel pair PWM1.
0
Non-inverted polarity for channel pair PWM1.
[2]
Pol0
1
Invert Output polarity for channel pair PWM0.
0
Non-inverted polarity for channel pair PWM0.
00
01
10
11
PWM Prescaler
The prescaler divides down the PWM input clock (either the system clock or the
PWMIN external input). This field is buffered. Changes to this field take effect at
the next PWM reload event. Reads always return the values from the
temporary holding register.
Divide by 1
Divide by 2
Divide by 4
Divide by 8
[1:0]
PRES
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
318
Hex Address: F22
PWM Dead-Band Register (PWMDB)
BITS
7
6
5
4
3
FIELD
PWMDB[7:0]
RESET
01H
R/W
R/W
ADDR
F22H
Bit
Position
Value
(H)
[7:0]
PWMDB
2
1
0
Description
PWM Dead band
Sets the PWM dead band period for which both PWM outputs of a
complementary PWM output pair are deasserted.
Note: This register can only be written when PWEN is cleared.
Hex Address: F23
PWM Minimum Pulse Width Filter (PWMMPF)
BITS
7
6
5
4
3
FIELD
PWMMPF[7:0]
RESET
00H
R/W
R/W
ADDR
F23H
Bit
Position
[7:0]
PWMMPF
Value
(H)
2
1
0
Description
PWM Minimum Pulse Filter
Sets the minimum allowed output pulse width in PWM clock cycles.
Note: This register can only be written when PWEN is cleared.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
319
Hex Address: F24
PWM Fault Mask Register (PWMFM)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
DBGMSK
Reserved
F1MASK
C0MASK
FMASK
RESET
00
0
000
0
0
0
R/W
R
R/W
R
R/W
R/W
R/W
F24H
ADDR
Bit
Position
Value
(H)
[7:6]
Reserved
[5]
DBGMSK
Must be 0.
0
Debug Entry Fault Mask
Entering CPU DEBUG Mode generates a PWM fault.
1
Entering CPU DEBUG mode does not generate a PWM fault.
[4:3]
Reserved
[2]
F1MASK
[1]
C0MASK
[0]
F0MASK
Description
Must be 0.
0
Fault 1 Fault Mask
Fault 1 generates a PWM fault.
1
Fault 1 does not generate a PWM fault.
0
Comparator Fault Mask
Comparator generates a PWM fault.
1
Comparator does not generate a PWM fault.
0
Fault Pin Mask
Fault0 pin generates a PWM fault.
1
Fault0 pin does not generate a PWM fault.
Note: This register can only be written when PWEN is cleared.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
320
Hex Address: F25
PWM Fault Status Register (PWMFSTAT)
BITS
7
6
FIELD
RLDFlag
RESET
U
0
R/W
R/W1C
R
5
2
1
0
Reserved
F1FLAG
C0FLAG
FFLAG
U
00
U
U
U
R/W1C
R
R/W1C
R/W1C
R/W1C
Reserved DBGFLAG
Value
(H)
[7]
RLDFlag
[6]
Reserved
Description
Reload Flag
This bit is set and latched when a PWM timer reload occurs. Writing a 1 to this bit
clears the flag.
0
[5]
DBGFLAG
[4:3]
Reserved
3
F25H
ADDR
Bit
Position
4
Reserved
Always reads 0.
Debug Flag
This bit is set and latched when DEBUG mode is entered. Writing a 1 to this bit
clears the flag.
0
Reserved
Always reads 0.
[2]
F1FLAG
Fault1 Flag
This bit is set and latched when Fault1 is asserted. Writing a 1 to this bit clears
the flag.
[1]
C0FLAG
Comparator 0 Flag
This bit is set and latched when Comparator is asserted. Writing a 1 to this bit
clears the flag.
[0]
FFLAG
Fault Flag
This bit is set and latched when the FAULT0 input is asserted. Writing a 1 to this
bit clears the flag.
Note: For this register, W1C means you must write one to clear the flag.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
321
Hex Address: F26
PWM Input Sample Register (PWMIN)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
FAULT
IN2L
IN2H
IN1L
IN1H
IN0L
IN0H
RESET
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F26H
ADDR
Bit
Position
Value
(H)
[7]
Reserved
Description
Must be 0.
[6]
FAULT
[5:0]
IN2L/IN2H/
IN1L/IN1H/
IN0L/IN0H
0
Sample Fault0 pin
A Low level signal was read on the FAULT pin.
1
A High level signal was read on the FAULT pin.
0
Sample PWM pins
A Low level signal was read on the pins.
1
A High level signal was read on the pins.
Hex Address: F27
.
PWM Output Control Register (PWMOUT)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
Reserved
OUT2L
OUT2H
OUT1L
OUT1H
OUT0L
OUT0H
RESET
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
PS024604-1005
F27H
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
322
Bit
Position
Value
(H)
[7,6]
Reserved
Description
Must be 0.
[5, 3, 1]
OUT2L/
OUT1L/
OUT0L
[4, 2, 0]
OUT2H/
OUT1H/
OUT0H
0
PWM 2L/1L/0L Output Configuration
PWM 2L/1L/0L output signal is enabled and controlled by PWM.
1
PWM 2L/1L/0L output signal is in low-side off-state.
0
PWM 2H/1H/0H Output Configuration
PWM 2H/1H/0H output signal is enabled and controlled by PWM.
1
PWM 2H/1H/0H output signal is in high-side off-state.
Hex Address: F28
PWM Fault Control Register (PWMFCTL)
BITS
7
6
5
FIELD
Reserved
DBGRST
RESET
0
0
0
R/W
R/W
R/W
R/W
3
2
CMPINT
CMPRST
0
0
0
R/W
R/W
R/W
Fault1INT Fault1RST
1
0
Fault0INT Fault0RST
R/W
R/W
F28H
ADDR
Bit
Position
Value
(H)
[7]
Reserved
0
[6]
DBGRST
0
Description
Reserved.
1
[5]
Fault1INT
4
DebugRestart
Automatic recovery. PWM resumes control of outputs when all fault sources have
deasserted and a new PWM period begins.
Software controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted and all fault flags are cleared and a PWM reload occurs
Fault 1 Interrupt
0
Interrupt on comparator assertion disabled.
1
Interrupt on comparator assertion enabled.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
323
Bit
Position
Value
(H)
[4]
Fault1RST
0
Fault 1 Restart
Automatic recovery. PWM resumes control of outputs when all fault sources have
deasserted.
Software controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted and all fault flags are cleared and a PWM reload occurs
1
[3
CMP0INT
[2]
CMP0RST
Comparator 0 Interrupt
0
Interrupt on comparator 0 assertion disabled.
1
Interrupt on comparator 0 assertion enabled.
0
Comparator 0 Restart
Automatic recovery. PWM resumes control of outputs when all fault sources have
deasserted.
Software controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted and all fault flags are cleared and a PWM reload occurs
1
[1]
Fault0INT
[0]
Fault0RST
Description
Fault 0 Interrupt
0
Interrupt on Fault0 pin assertion disabled.
1
Interrupt on Fault0 pin assertion enabled.
0
Fault 0 Restart
Automatic recovery. PWM resumes control of outputs when all fault sources have
deasserted.
Software controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted and all fault flags are cleared and a PWM reload occurs
1
Note: This register can only be written when PWEN is cleared.
Hex Address: F29
.
Table 169. Current-Sense Trigger Control Register (PWMSHC)
BITS
7
6
5
4
3
FIELD
CSTPOL
HEN
NHEN
LEN
NLEN
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
PS024604-1005
2
1
0
CSTPWM2 CSTPWM1 CSTPWM0
F29H
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
324
Bit
Position
Value
(H)
Description
[7]
CSTPOL
0
Sample Hold Polarity
Hold when terms are active
1
Hold when terms are not active
0
High Side Active enable
Ignore Product of PWM0H, PWM1H, PWM2H in Sample/Hold equation
1
Hold when PWM0H, PWM1H, PWM2H are all active
0
High Side inactive enable
Ignore Product of PWM0H, PWM1H, PWM2H in Sample/Hold equation
1
Hold when are all active
0
Low Side Active enable
Ignore Product of PWM0L, PWM1L, PWM2L in Sample/Hold equation
1
Hold when PWM0L, PWM1L, PWM2L are all active
0
Low Side Inactive enable
Ignore Product of PWM0L, PWM1L, PWM2L in Sample/Hold equation
1
Hold when PWM0L, PWM1L, PWM2L are all active
0
PWM Channel2 Sample/Hold Enable
Channel 2 terms are not used in Sample/Hold Equation
1
Channel 2 terms are used in Sample/Hold Equation
0
PWM Channel1 Sample/Hold Enable
Channel 1 terms are not used in Sample/Hold Equation
1
Channel 1 terms are used in Sample/Hold Equation
0
PWM Channel0 Sample/Hold Enable
Channel 0 terms are not used in Sample/Hold Equation
1
Channel 0 terms are used in Sample/Hold Equation
[6]
HEN
[5]
NHEN
[4]
LEN
[3]
NLEN
[2]
CSTPWM2
[1]
CSTPWM1
[0]
CSTPWM0
Hex Address: F2A–B
Reserved
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
325
Hex Address: F2C
PWM High Byte Register (PWMH)
BITS
7
6
5
4
3
2
FIELD
Reserved
PWMH
RESET
0H
0H
R/W
R/W
R/W
1
0
F2CH
ADDR
Hex Address: F2D
PWM Low Byte Register (PWML)
BITS
7
6
5
4
FIELD
PWML
RESET
01H
R/W
R/W
ADDR
F2DH
3
2
1
0
3
2
1
0
Hex Address: F2E
PWM Reload High Byte Register (PWMRH)
BITS
7
6
5
4
FIELD
Reserved
PWMRH
RESET
0H
FH
R/W
R/W
R/W
ADDR
PS024604-1005
F2EH
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
326
Hex Address: F2F
PWM Reload Low Byte Register (PWMRL)
BITS
7
6
5
4
3
FIELD
PWMRL
RESET
FF
R/W
R/W
ADDR
F2FH
2
1
0
Hex Address: F30
PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH)
BITS
7
6
5
4
3
2
1
FIELD
SIGN
Reserved
DUTYH
RESET
0
00
0_0000
R/W
R/W
R/W
R/W
0
F30H, F32H, F34H, F36H, F38H, F3AH
ADDR
Hex Address: F31
PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)
BITS
7
6
5
4
3
2
FIELD
DUTYL
RESET
00H
R/W
R/W
ADDR
F31H, F33H, F35H, F37H, F39H, F3BH
PS024604-1005
PRELIMINARY
1
0
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
327
Bit
Position
Value
(H)
[7]
SIGN
0
Description
Duty Cycle Sign
Duty Cycle is a positive two’s complement number.
1
Duty Cycle is a negative two’s complement number. Output is forced to the offstate.
[6:0], [7:0]
DUTYH and
DUTYL
PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5
and 6 of the High Byte are always 0). The value is compared to the current 12-bit
PWM count.
Hex Address: F32
PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH)
BITS
7
6
5
4
3
2
1
FIELD
SIGN
Reserved
DUTYH
RESET
0
00
0_0000
R/W
R/W
R/W
R/W
0
F30H, F32H, F34H, F36H, F38H, F3AH
ADDR
Hex Address: F33
PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)
BITS
7
6
5
4
3
2
FIELD
DUTYL
RESET
00H
R/W
R/W
ADDR
F31H, F33H, F35H, F37H, F39H, F3BH
PS024604-1005
PRELIMINARY
1
0
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
328
Bit
Position
Value
(H)
[7]
SIGN
0
Description
Duty Cycle Sign
Duty Cycle is a positive two’s complement number.
1
Duty Cycle is a negative two’s complement number. Output is forced to the offstate.
[6:0], [7:0]
DUTYH and
DUTYL
PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5
and 6 of the High Byte are always 0). The value is compared to the current 12-bit
PWM count.
Hex Address: F34
PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH)
BITS
7
6
5
4
3
2
1
FIELD
SIGN
Reserved
DUTYH
RESET
0
00
0_0000
R/W
R/W
R/W
R/W
0
F30H, F32H, F34H, F36H, F38H, F3AH
ADDR
Hex Address: F35
PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)
BITS
7
6
5
4
3
2
FIELD
DUTYL
RESET
00H
R/W
R/W
ADDR
F31H, F33H, F35H, F37H, F39H, F3BH
PS024604-1005
PRELIMINARY
1
0
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
329
Bit
Position
Value
(H)
[7]
SIGN
0
Description
Duty Cycle Sign
Duty Cycle is a positive two’s complement number.
1
Duty Cycle is a negative two’s complement number. Output is forced to the offstate.
[6:0], [7:0]
DUTYH and
DUTYL
PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5
and 6 of the High Byte are always 0). The value is compared to the current 12-bit
PWM count.
Hex Address: F36
PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH)
BITS
7
6
5
4
3
2
1
FIELD
SIGN
Reserved
DUTYH
RESET
0
00
0_0000
R/W
R/W
R/W
R/W
0
F30H, F32H, F34H, F36H, F38H, F3AH
ADDR
Hex Address: F37
PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)
BITS
7
6
5
4
3
2
FIELD
DUTYL
RESET
00H
R/W
R/W
ADDR
F31H, F33H, F35H, F37H, F39H, F3BH
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PRELIMINARY
1
0
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
330
Bit
Position
Value
(H)
[7]
SIGN
0
Description
Duty Cycle Sign
Duty Cycle is a positive two’s complement number.
1
Duty Cycle is a negative two’s complement number. Output is forced to the offstate.
[6:0], [7:0]
DUTYH and
DUTYL
PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5
and 6 of the High Byte are always 0). The value is compared to the current 12-bit
PWM count.
Hex Address: F38
PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH)
BITS
7
6
5
4
3
2
1
FIELD
SIGN
Reserved
DUTYH
RESET
0
00
0_0000
R/W
R/W
R/W
R/W
0
F30H, F32H, F34H, F36H, F38H, F3AH
ADDR
Hex Address: F39
PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)
BITS
7
6
5
4
3
2
FIELD
DUTYL
RESET
00H
R/W
R/W
ADDR
F31H, F33H, F35H, F37H, F39H, F3BH
PS024604-1005
PRELIMINARY
1
0
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
331
Bit
Position
Value
(H)
[7]
SIGN
0
Description
Duty Cycle Sign
Duty Cycle is a positive two’s complement number.
1
Duty Cycle is a negative two’s complement number. Output is forced to the offstate.
[6:0], [7:0]
DUTYH and
DUTYL
PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5
and 6 of the High Byte are always 0). The value is compared to the current 12-bit
PWM count.
Hex Address: F3A
PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH)
BITS
7
6
5
4
3
2
1
FIELD
SIGN
Reserved
DUTYH
RESET
0
00
0_0000
R/W
R/W
R/W
R/W
0
F30H, F32H, F34H, F36H, F38H, F3AH
ADDR
Hex Address: F3B
PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)
BITS
7
6
5
4
3
2
FIELD
DUTYL
RESET
00H
R/W
R/W
ADDR
F31H, F33H, F35H, F37H, F39H, F3BH
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PRELIMINARY
1
0
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
332
Bit
Position
Value
(H)
[7]
SIGN
0
Description
Duty Cycle Sign
Duty Cycle is a positive two’s complement number.
1
Duty Cycle is a negative two’s complement number. Output is forced to the offstate.
[6:0], [7:0]
DUTYH and
DUTYL
PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5
and 6 of the High Byte are always 0). The value is compared to the current 12-bit
PWM count.
Hex Addresses: F3C–F3F
Reserved
LIN-UART
Hex Address: F40
LIN-UART Transmit Data Register (U0TXD)
BITS
7
6
5
4
3
FIELD
TXD
RESET
X
R/W
W
ADDR
F40H
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PRELIMINARY
2
1
0
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
333
LIN-UART Receive Data Register (U0RXD)
7
BITS
6
5
4
3
FIELD
RXD
RESET
X
R/W
R
ADDR
F40H
2
1
0
Hex Address: F41
LIN-UART Status 0 Register - standard UART mode (U0STAT0)
BITS
7
6
5
4
3
2
1
0
FIELD
RDA
PE
OE
FE
BRKD
TDRE
TXE
CTS
RESET
0
0
0
0
0
1
1
X
R/W
R
R
R
R
R
R
R
R
F41H
ADDR
Hex Address: F42
LIN-UART Control 0 Register (U0CTL0)
BITS
7
6
5
4
3
2
1
0
FIELD
TEN
REN
CTSE
PEN
PSEL
SBRK
STOP
LBEN
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
PS024604-1005
F42H
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
334
Hex Address: F43
MultiProcessor Control Register (U0CTL1 with MSEL = 000b)
BITS
7
6
5
4
3
2
1
0
FIELD
MPMD[1]
MPEN
MPMD[0]
MPBT
DEPOL
BRGCTL
RDAIRQ
IREN
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
F43H with MSEL = 000b
ADDR
Hex Address: F44
LIN-UART Mode Select and Status Register (U0MDSTAT)
7
BITS
6
5
4
3
MSEL
FIELD
2
Mode Status
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
R
1
0
F44H
ADDR
Hex Address: F45
LIN-UART Address Compare Register (U0ADDR)
BITS
7
6
5
4
3
FIELD
COMP_ADDR
RESET
00H
R/W
R/W
ADDR
F45H
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PRELIMINARY
2
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
335
Hex Address: F46
LIN-UART Address Compare Register (U0ADDR)
BITS
7
6
5
4
3
FIELD
COMP_ADDR
RESET
00H
R/W
R/W
ADDR
F45H
2
1
0
2
1
0
Hex Address: F47
LIN-UART Baud Rate Low Byte Register (U0BRL)
BITS
7
6
5
4
3
FIELD
BRL
RESET
FFH
R/W
R/W
ADDR
F47H
Hex Addresses: F48–F5F
Reserved
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
336
I2C
Hex Address: F50
I2C Data Register (I2CDATA)
BITS
7
6
5
4
FIELD
DATA
RESET
0
R/W
R/W
ADDR
F50H
3
2
1
0
Hex Address: F51
I2C Interrupt Status Register (I2CISTAT)
BITS
7
6
5
4
3
2
1
0
FIELD
TDRE
RDRF
SAM
GCA
RD
ARBLST
SPRS
NCKI
RESET
1
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
F51H
ADDR
Hex Address: F52
I2C Control Register (I2CCTL)
BITS
7
6
5
4
3
2
1
0
FIELD
IEN
START
STOP
BIRQ
TXI
NAK
FLUSH
FILTEN
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W1
R/W1
R/W
R/W
R/W1
R/W
R/W
ADDR
PS024604-1005
F52H
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
337
Hex Address: F53
I2C Baud Rate High Byte Register (I2CBRH)
BITS
7
6
5
4
FIELD
BRH
RESET
FFH
R/W
R/W
ADDR
F53H
3
2
1
0
3
2
1
0
Hex Address: F54
I2C Baud Rate Low Byte Register (I2CBRL)
BITS
7
6
5
4
FIELD
BRL
RESET
FFH
R/W
R/W
ADDR
F54H
Hex Address: F55
I2C State Register (I2CSTATE) - Description when DIAG = 0
BITS
7
6
5
4
3
2
1
0
FIELD
ACKV
ACK
AS
DS
10B
RSTR
SCLOUT
BUSY
RESET
0
0
0
0
0
0
X
X
R/W
R
R
R
R
R
R
R
R
1
0
F55H
ADDR
I2C State Register (I2CSTATE) - Description when DIAG = 1
BITS
7
6
5
4
3
I2CSTATE_H
FIELD
2
I2CSTATE_L
RESET
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
ADDR
PS024604-1005
F55H
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
338
Hex Address: F56
I2C Mode Register (I2CMODE)
BITS
7
FIELD
Reserved
RESET
R/W
6
5
4
3
2
1
0
MODE[1:0]
IRM
GCE
SLA[9:8]
DIAG
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
F56H
ADDR
Hex Address: F57
I2C Slave Address Register (I2CSLVAD)
BITS
7
6
5
4
FIELD
SLA[7:0]
RESET
00H
R/W
R/W
ADDR
F57H
3
2
1
0
3
2
1
0
Hex Addresses: F58–F5F
Reserved
SPI
Hex Address: F60
SPI Data Register (SPIDATA)
BITS
7
6
5
4
FIELD
DATA
RESET
X
R/W
R/W
ADDR
F60H
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
339
Hex Address: F61
SPI Control Register (SPICTL)
BITS
7
6
5
4
3
2
1
0
FIELD
IRQE
STR
BIRQ
PHASE
CLKPOL
WOR
MMEN
SPIEN
1
0
TXST
SLAS
0
1
RESET
00H
R/W
R/W
ADDR
F61H
Hex Address: F62
SPI Status Register (SPISTAT)
BITS
7
6
5
4
FIELD
IRQ
OVR
COL
ABT
RESET
0
0
0
0
R/W
3
2
Reserved
0
R/W*
0
R
F62H
ADDR
R/W* = Read access. Write a 1 to clear the bit to 0.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
340
Hex Address: F63
SPI Mode Register (SPIMODE)
BITS
7
6
Reserved
FIELD
5
4
3
DIAG
2
NUMBITS[2:0]
1
0
SSIO
SSV
1
0
00H
RESET
R
R/W
R/W
F63H
ADDR
Hex Address: F64
SPI Diagnostic State Register (SPIDST)
BITS
7
6
FIELD
SCKEN
TCKEN
5
4
3
2
SPISTATE
RESET
00H
R/W
R
ADDR
F64H
Hex Address: F65
Reserved
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
341
Hex Address: F66
SPI Baud Rate High Byte Register (SPIBRH)
BITS
7
6
5
4
3
FIELD
BRH
RESET
FFH
R/W
R/W
ADDR
F66H
2
1
0
2
1
0
Hex Address: F67
SPI Baud Rate Low Byte Register (SPIBRL)
BITS
7
6
5
4
3
FIELD
BRL
RESET
FFH
R/W
R/W
ADDR
F67H
Hex Addresses: F68–F6F
Reserved
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
342
Analog-to-Digital Converter (ADC)
Hex Address: F70
ADC Control Register 0 (ADCCT0)
BITS
7
6
5
4
3
FIELD
START
Reserved
REFEN
ADCEN
Reserved
RESET
0
0
0
0
0
0
0
0
R/W1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
1
0
ANAIN[2:0]
F70H
ADDR
Bit
Position
Value
(H)
[7]
START
0
Description
ADC Start / Busy
Writing to 0 has no effect.
Reading a 0 indicates the ADC is available to begin a conversion.
1
Writing to 1 starts a conversion.
Reading a 1 indicates a conversion is currently in progress.
[6]
0
Reserved—Must Be 0.
[5]
REFEN
0
Reference Enable
Internal reference voltage is disabled allowing an external reference voltage to be
used by the ADC.
1
[4]
ADCEN
[3]
Reserved
Internal reference voltage for the ADC is enabled. The internal reference voltage
can be measured on the VREF pin.
0
ADC Enable
ADC is disabled for low power operation.
1
ADC is enabled for normal use.
Reserved—Must Be 0.
0
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PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
343
[2:0]
ANAIN
000
Analog Input Select
ANA0 input is selected for analog to digital conversion.
001
ANA1 input is selected for analog to digital conversion.
010
ANA2 input is selected for analog to digital conversion.
011
ANA3 input is selected for analog to digital conversion.
100
ANA4 input is selected for analog to digital conversion.
101
ANA5 input is selected for analog to digital conversion.
110
ANA6 input is selected for analog to digital conversion.
111
ANA7 input is selected for analog to digital conversion.
Hex Address: F71
ADC Raw Data High Byte Register (ADCRD_H)
BITS
7
6
5
4
3
FIELD
ADCRDH
RESET
X
R/W
R
2
1
0
F71H
ADDR
Bit
Position
Value
(H)
[7:0]
00H–FFH ADC Raw Data High Byte
The data in this register is the raw data coming from the SAR Block. It will change
as the conversion is in progress. This register is used for testing only.
PS024604-1005
Description
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
344
Hex Address: F72
ADC Raw Data High Byte Register (ADCRD_H)
BITS
7
6
5
4
3
FIELD
ADCRDH
RESET
X
R/W
R
2
1
0
F71H
ADDR
Bit
Position
Value
(H)
Description
[7:0]
00H–FFH ADC Raw Data High Byte
The data in this register is the raw data coming from the SAR Block. It will change
as the conversion is in progress. This register is used for testing only.
Hex Address: F73
ADC Data Low Bits Register (ADCD_L)
BITS
7
6
5
4
3
2
FIELD
ADCDL
Reserved
RESET
X
X
R/W
R
R
Value
(H)
[7:6]
00–11b
[5:0]
Reserved
0
F73H
ADDR
Bit
Position
1
Description
ADC Low Bits
These bits are the 2 least significant bits of the 10-bit ADC output. These bits are
undefined after a Reset. The low bits are latched into this register whenever the
ADC Data High Byte register is read.
Reserved—Must Be 0.
0
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
345
Hex Address: F74
Sample and Settling Time (ADCSST)
BITS
7
6
5
FIELD
Reserved
RESET
0
R/W
R
4
3
2
1
0
1
1
SST
1
1
R/W
F74H
ADDR
Bit
Position
Value
(H)
Description
[7:4]
0H
Reserved - Must be 0.
[3:0]
SST
0H - FH
Sample settling time in number of system clock periods to meet 0.5uS minimum.
Hex Address: F75
Sample Hold Time (ADCST)
BITS
7
6
FIELD
Reserved
RESET
0
5
4
3
1
0
1
1
1
ST
1
1
1
R/W
R/W
2
R/W
F75H
ADDR
Bit
Position
Value
(H)
Description
[7:5]
0H
Reserved - Must be 0.
[4:0]
SHT
0H - FH
Sample Hold time in number of system clock periods to meet 1uS minimum.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
346
Hex Address: F76
ADC Clock Prescale Register (ADCCP)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
DIV16
DIV8
DIV4
DIV2
RESET
0
0
0
0
0
R/W
R/W
ADDR
F76H
Bit
Position
Value
(H)
[0]
DIV2
0
DIV2
Clock is not divided
1
System Clock is divided by 2 for ADC Clock
0
DIV4
Clock is not divided
1
System Clock is divided by 4 for ADC Clock
0
DIV8
Clock is not divided
1
System Clock is divided by 8 for ADC Clock
0
DIV16
Clock is not divided
1
System Clock is divided by 16 for ADC Clock
0H
Reserved - must be 0.
[1]
DIV4
[2]
DIV8
[3]
DIV16
[7:4]
Description
Hex Addresses: F77–F85
Reserved
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
347
Oscillator Control
Hex Address: F86
Oscillator Control Register (OSCCTL)
BITS
7
6
5
4
3
2
1
0
FIELD
INTEN
XTLEN
WDTEN
POFEN
WDFEN
FLPEN
SCKSEL
RESET
1
0
1
0
0
0*
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F86H
ADDR
* The reset value is 1 if the option bit LPDEN is 0.
Bit
Position
Value
(H)
[7]
INTEN
0
Internal Precision Oscillator Enable
Internal precision oscillator is disabled.
1
Internal precision oscillator is enabled.
0
Crystal Oscillator Enable
Crystal oscillator is disabled.
1
Crystal oscillator is enabled.
0
Watch-Dog Timer Oscillator Enable
Watch-Dog Timer oscillator is disabled
1
Watch-Dog Timer oscillator is enabled
0
Primary Oscillator Failure Detection Enable
Failure detection and recovery of primary oscillator is disabled. This bit is cleared
automatically if a primary oscillator failure is detected.
1
Failure detection and recovery of primary oscillator is enabled
0
Watch-Dog Timer Oscillator Failure Detection Enable
Failure detection of Watch-Dog Timer oscillator is disabled.This bit is cleared
automatically if a Watch-Dog Timer oscillator failure is detected.
1
Failure detection of Watch-Dog Timer oscillator is enabled
[6]
XTLEN
[5]
WDTEN
[4]
POFEN
[3]
WDFEN
PS024604-1005
Description
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
348
Bit
Position
Value
(H)
[2]
FLPEN
0
Flash Low Power Mode Enable
Flash Low Power Mode is disabled.
1
[1:0]
SCKSEL
Description
Flash Low Power Mode is enabled. The Flash will be powered down during idle
periods of the clock and powered up during Flash reads. This bit should only be
set if the frequency of the primary oscillator source is 8MHz or lower. The reset
value of this bit is controlled by the LPDEN option bit during reset.
00
01
10
11
System Clock Oscillator Select
Internal precision oscillator functions as system clock at 5.6MHz
Reserved
Crystal oscillator or external clock driver functions as system clock
Watch-Dog Timer oscillator functions as system clock
Hex Address: F87
Oscillator Divide Register (OSCDIV)
BITS
7
6
5
4
3
FIELD
DIV
RESET
00H*
R/W
R/W
ADDR
F87H
2
1
0
* The reset value is 08H if the option bit LPDEN is 0.
Bit
Position
[7:0]
DIV
Value
(H)
00H to
FFH
Description
Oscillator Divide
00H - divider is disabled, all other entries are the divide value for scaling the
system clock.
Trim Control
Hex Addresses: F88–F8F
Reserved
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
349
Comparator and Op Amp
Hex Address: F90
Comparator and Op Amp Control Register (CMPOPC)
BITS
7
6
5
4
3
2
1
0
FIELD
OPEN
Reserved
CPSEL
CMPIRQ
CMPIV
CMPOUT
CMPEN
RESET
0
00
0
0
0
X
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
F90H
ADDR
Bit
Position
Value
(H)
[7]
OPEN
0
Operational Amplifier Disable
Operational amplifier is disabled.
1
Operational amplifier is enabled.
[6:5]
Reserved
[3]
CPSEL
[3]
CMPIRQ
[2]
CMPIV
[1]
CMPOUT
[0]
CMPEN
Description
Must be 0.
0
Comparator Input Select
Comparator input is PA1
1
Comparator input is PB4
0
Comparator Interrupt Edge Select
Interrupt Request on Comparator Rising Edge
1
Interrupt Request on Comparator Falling Edge
0
PWM Fault Comparator Polarity
PWM Fault is active when cp+ > cp-
1
PWM Fault is active when cp- > cp+
0
Comparator Output Value
Comparator output is logical 0.
1
Comparator output is logical 1.
0
Comparator Enable
Comparator is disabled.
1
Comparator is enabled.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
350
Hex Addresses: F91–FBF
Reserved
Interrupt Controller
Hex Address: FC0
Interrupt Request 0 Register (IRQ0)
BITS
7
6
5
4
3
2
1
0
FIELD
PWMI
FLTI
ADCI
CMPI
T0I
U0RXI
U0TXI
SPII
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC0H
ADDR
Bit
Position
Value
(H)
[7]
PWMI
0
PWM Timer Interrupt Request
No interrupt request is pending for the Pulse-Width Modulator.
1
An interrupt request from the Pulse-Width Modulator is awaiting service.
[6]
FLTI
[5]
ADCI
[4]
CMPI
[3]
T0I
0
Description
Fault Interrupt Request. The fault interrupt is generated in the PWM module and
originates from the Fault0 pin, Fault1 pin or the Comparator output. An interrupt
enable for each of these sources exists in the PWM module.
No Fault interrupt request is pending.
1
A Fault interrupt request is awaiting service.
0
ADC Interrupt Request
No interrupt request is pending for the Analog to Digital Converter.
1
An interrupt request from the Analog to Digital Converter is awaiting service.
0
Comparator Interrupt Request
No interrupt request is pending for the Comparators.
1
An interrupt request from the Comparators is awaiting service.
0
Timer 0 Interrupt Request
No interrupt request is pending for Timer 0.
1
An interrupt request from Timer 0 is awaiting service.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
351
Bit
Position
Value
(H)
[2]
U0RXI
0
UART 0 Receiver Interrupt Request
No interrupt request is pending for the UART 0 receiver.
1
An interrupt request from the UART 0 receiver is awaiting service.
0
UART 0 Transmitter Interrupt Request
No interrupt request is pending for the UART 0 transmitter.
1
An interrupt request from the UART 0 transmitter is awaiting service.
0
SPI Interrupt Request
No interrupt request is pending for the SPI.
1
An interrupt request from the SPI is awaiting service.
[1]
U0TXI
[0]
SPII
Description
Hex Address: FC1
IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
7
6
5
4
3
2
1
0
FIELD
PWMENH
FLTENH
ADCENH
CMPENH
T0ENH
U0RENH
U0TENH
SPIENH
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC1H
ADDR
Hex Address: FC2
IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
7
6
5
4
3
2
1
0
FIELD
PWMENL
FLTENL
ADCENL
CMPENL
T0ENL
U0RENL
U0TENL
SPIENL
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
PS024604-1005
FC2H
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
352
Hex Address: FC3
Interrupt Request 1 Register (IRQ1)
BITS
7
6
5
4
3
2
1
0
FIELD
I2CI
Reserved
PC0I
PBI
PA73I
PA62I
PA51I
PA40I
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
FC3H
ADDR
Bit
Position
Value
(H)
[7]
I2CI
0
I2C Interrupt Request
No interrupt request is pending for I2C.
1
An interrupt request from I2C is awaiting service.
0
PC0 Interrupt Request — Logic in the Port C GPIO module selects either the
rising or falling edge.
No interrupt request is pending for PC0.
1
An interrupt request from PC0 is awaiting service.
0
PB3 – PB0 Interrupt Request
No interrupt request is pending for any PB3 – PB0.
1
An interrupt request from PB3 – PB0 is awaiting service.
0
PA7 or PA3 Interrupt Request — Logic in the Port A GPIO module selects either
PA7 or PA3 and either rising or falling edge.
No interrupt request is pending for PA7 or PA3
1
An interrupt request from PA7 or PA3 is awaiting service.
0
PA6 or PA2 Interrupt Request — Logic in the Port A GPIO module selects either
PA6 or PA2 and either rising or falling edge.
No interrupt request is pending for PA6 or PA2
1
An interrupt request from PA6 or PA2 is awaiting service.
0
PA5 or PA1 Interrupt Request — Logic in the Port A GPIO module selects either
PA5 or PA1 and either rising or falling edge.
No interrupt request is pending for PA5 or PA1
1
An interrupt request from PA5 or PA1 is awaiting service.
0
PA4 or PA0 Interrupt Request — Logic in the Port A GPIO module selects either
PA4 or PA0 and either rising or falling edge.
No interrupt request is pending for PA4 or PA0
1
An interrupt request from PA4 or PA0 is awaiting service.
[5]
PC0I
[4]
PBI
[3]
PA73I
[2]
PA62I
[1]
PA51I
[0]
PA40I
PS024604-1005
Description
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
353
Hex Address: FC4
IRQ1 Enable High Bit Register (IRQ1ENH)
BITS
7
6
5
4
3
2
1
0
FIELD
I2CENH
Reserved
PC0ENH
PBENH
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
2
1
0
PA73ENH PA62ENH PA51ENH PA40ENH
FC4H
ADDR
Bit
Name
Position
Description
[7]
I2CENH
I2C Interrupt Request Enable High Bit
[5]
PC0ENH Port C0Interrupt Request Enable High Bit
[4]
PBENH
[3]
PA73ENH Port A73 Interrupt Request Enable High Bit
[2]
PA62ENH Port A62 Interrupt Request Enable High Bit
[1]
PA51ENH Port A51 Interrupt Request Enable High Bit
[0]
PA40ENH Port A40 Interrupt Request Enable High Bit
Port B[3:0] Interrupt Request Enable High Bit
Hex Address: FC5
IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS
7
6
5
4
FIELD
I2CENL
Reserved
PC0ENL
PBENL
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
PS024604-1005
3
PA73ENL PA62ENL PA51ENL PA40ENL
FC5H
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
354
Bit
Name
Position
Description
[7]
I2CENL
I2C Interrupt Request Enable Low Bit
[5]
PC0ENL
Port C0Interrupt Request Enable Low Bit
[4]
PBENL
Port B[3:0] Interrupt Request Enable Low Bit
[3]
PA73ENL Port A73 Interrupt Request Enable Low Bit
[2]
PA62ENL Port A62 Interrupt Request Enable Low Bit
[1]
PA51ENL Port A51 Interrupt Request Enable Low Bit
[0]
PA40ENL Port A40 Interrupt Request Enable Low Bit
Hex Addresses: FC9–FCE
Reserved
Hex Address: FCF
Interrupt Control Register (IRQCTL)
BITS
7
FIELD
IRQE
RESET
0
0
0
0
R/W
R/W
R
R
R
ADDR
PS024604-1005
6
5
4
3
2
1
0
0
0
0
0
R
R
R
R
Reserved
FCFH
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
355
GPIO Port A
Hex Address: FD0
Port A–C GPIO Address Registers (PxADDR)
BITS
7
6
5
4
3
FIELD
PADDR[7:0]
RESET
00H
R/W
R/W
ADDR
FD0H, FD4H, FD8H
2
1
0
2
1
0
Hex Address: FD1
Port A–C Control Registers (PxCTL)
BITS
7
6
5
4
3
FIELD
PCTL
RESET
00H
R/W
R/W
ADDR
FD1H, FD5H, FD9H
Hex Address: FD2
Port A-C Input Data Registers (PxIN)
BITS
7
6
5
4
3
2
1
0
FIELD
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
RESET
X
X
X
X
X
X
X
X
R/W
R
R
R
R
R
R
R
R
FD2H, FD6H, FDAH
ADDR
Bit
Position
Value
(H)
[7:0]
PIN
0
Port Input Data x
Input data is a logical 0 (Low).
1
Input data is a logical 1 (High).
PS024604-1005
Description
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
356
Hex Address: FD3
Port A-C Output Data Register (PxOUT)
BITS
7
6
5
4
3
2
1
0
FIELD
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD3H, FD7H, FDBH
ADDR
Bit
Position
Value
(H)
[7:0]
POUT
0
Description
Port Output Data x
Drive is a logical 0 (Low).
1
Drive is a logical 1 (High). High value is not driven if the drain has been disabled
by setting the corresponding Port Output Control register bit to 1.
GPIO Port B
Hex Address: FD4
Port A–C GPIO Address Registers (PxADDR)
BITS
7
6
5
4
3
FIELD
PADDR[7:0]
RESET
00H
R/W
R/W
ADDR
FD0H, FD4H, FD8H
PS024604-1005
PRELIMINARY
2
1
0
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
357
Hex Address: FD5
Port A–C Control Registers (PxCTL)
BITS
7
6
5
4
3
FIELD
PCTL
RESET
00H
R/W
R/W
ADDR
FD1H, FD5H, FD9H
2
1
0
Hex Address: FD6
Port A-C Input Data Registers (PxIN)
BITS
7
6
5
4
3
2
1
0
FIELD
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
RESET
X
X
X
X
X
X
X
X
R/W
R
R
R
R
R
R
R
R
FD2H, FD6H, FDAH
ADDR
Bit
Position
Value
(H)
Description
[7:0]
PIN
0
Port Input Data x
Input data is a logical 0 (Low).
1
Input data is a logical 1 (High).
Hex Address: FD7
Port A-C Output Data Register (PxOUT)
BITS
7
6
5
4
3
2
1
0
FIELD
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
PS024604-1005
FD3H, FD7H, FDBH
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
358
Bit
Position
Value
(H)
[7:0]
POUT
0
Description
Port Output Data x
Drive is a logical 0 (Low).
1
Drive is a logical 1 (High). High value is not driven if the drain has been disabled
by setting the corresponding Port Output Control register bit to 1.
GPIO Port C
Hex Address: FD8
Port A–C GPIO Address Registers (PxADDR)
BITS
7
6
5
4
3
FIELD
PADDR[7:0]
RESET
00H
R/W
R/W
ADDR
FD0H, FD4H, FD8H
2
1
0
2
1
0
Hex Address: FD9
Port A–C Control Registers (PxCTL)
BITS
7
6
5
4
3
FIELD
PCTL
RESET
00H
R/W
R/W
ADDR
FD1H, FD5H, FD9H
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
359
Hex Address: FDA
Port A-C Input Data Registers (PxIN)
BITS
7
6
5
4
3
2
1
0
FIELD
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
RESET
X
X
X
X
X
X
X
X
R/W
R
R
R
R
R
R
R
R
FD2H, FD6H, FDAH
ADDR
Bit
Position
Value
(H)
Description
[7:0]
PIN
0
Port Input Data x
Input data is a logical 0 (Low).
1
Input data is a logical 1 (High).
Hex Address: FDB
Port A-C Output Data Register (PxOUT)
BITS
7
6
5
4
3
2
1
0
FIELD
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD3H, FD7H, FDBH
ADDR
Bit
Position
Value
(H)
[7:0]
POUT
0
1
PS024604-1005
Description
Port Output Data x
Drive is a logical 0 (Low).
Drive is a logical 1 (High). High value is not driven if the drain has been disabled
by setting the corresponding Port Output Control register bit to 1.
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
360
Reset and Watch-Dog Timer (WDT)
Hex Address: FF0
Reset Status and Control Register (RSTSCR)
BITS
7
6
5
4
3
FIELD
POR
STOP
WDT
EXT
FLT
1
Reserved
R
R
R
0
FLTSEL
See Table 10.
RESET
R/W
2
0
R
R
R
R/W
FF0H
ADDR
Hex Address: FF1
Reserved
Hex Address: FF2
Watch-Dog Timer Reload High Byte Register (WDTH)
BITS
7
6
5
4
3
FIELD
WDTH
RESET
04H
R/W
R/W*
ADDR
FF2H
2
1
0
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
361
Hex Address: FF3
Watch-Dog Timer Reload Low Byte Register (WDTL)
BITS
7
6
5
4
3
FIELD
WDTL
RESET
00H
R/W
R/W*
ADDR
FF3H
2
1
0
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
Hex Addresses: FF4–FF5
Reserved
Hex Address: FF6
Trim Bit Address Register (TRMADR)
BITS
7
6
5
4
3
FIELD
TRMADR
RESET
00H
R/W
R/W
ADDR
FF6H
2
1
0
Bit Position Value (H) Description
[7:0}
TRMADR
00 - 1FH Trim Bit Address Register
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
362
Hex Address: FF7
Trim Bit Data Register (TRMDR)
BITS
7
6
5
4
3
FIELD
TRMDR
RESET
00H
R/W
R/W
ADDR
FF7H
2
1
0
1
0
Bit Position Value (H) Description
[7:0}
TRMDR
00 - FFH Trim Bit Data Register
Flash Memory Controller
Hex Address: FF8
Flash Control Register (FCTL)
BITS
7
6
5
4
3
FIELD
FCMD
RESET
00H
R/W
W
ADDR
FF8H
Bit
Position
[7:0]
FCMD
Value
73H
8CH
95H
63H
5EH
PS024604-1005
2
Description
Flash Command:
First unlock command.
Second unlock command.
Page erase command.
Mass erase command.
Flash Sector Protect register select.
All other commands, or any command out of sequence, locks the Flash
Controller.
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
363
Flash Status Register (FSTAT)
BITS
7
6
5
4
3
FIELD
Reserved
FSTAT
RESET
00B
00_0000B
R/W
R
R
Value
0
2
1
0
Description
[7:6]
Reserved
[5:0]
FSTAT
1
FF8H
ADDR
Bit
Position
2
Must be 00.
00_0000
00_0001
00_0010
00_0011
00_0100
00_1xxx
01_0xxx
10_0xxx
Flash Controller Status
Flash Controller locked.
First unlock command received.
Second unlock command received.
Flash Controller unlocked.
Flash Sector Protect register selected.
Program operation in progress.
Page erase operation in progress.
Mass erase operation in progress.
Hex Address: FF9
Flash Status Register (FSTAT)
BITS
7
6
5
4
3
FIELD
Reserved
FSTAT
RESET
00B
00_0000B
R/W
R
R
ADDR
PS024604-1005
FF8H
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
364
Bit
Position
Value
[7:6]
Reserved
[5:0]
FSTAT
Description
Must be 00.
00_0000
00_0001
00_0010
00_0011
00_0100
00_1xxx
01_0xxx
10_0xxx
Flash Controller Status
Flash Controller locked.
First unlock command received.
Second unlock command received.
Flash Controller unlocked.
Flash Sector Protect register selected.
Program operation in progress.
Page erase operation in progress.
Mass erase operation in progress.
Flash Sector Protect Register (FPROT)
BITS
7
6
5
4
3
2
1
0
FIELD
SECT7
SECT6
SECT5
SECT4
SECT3
SECT2
SECT1
SECT0
RESET
0
0
0
0
0
0
0
0
R/W
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
FF9H
ADDR
R/W1 = Register is accessible for Read operations. Register can be written to 1 only (through user code).
Bit
Position
Value
Description
[7:0]]
SECTn
0
Sector Protect
Sector n can be programmed or erased from user code.
1
Sector n is protected and cannot be programmed or erased from user code.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
365
Hex Address: FFA
Flash Frequency High Byte Register (FFREQH)
BITS
7
6
5
4
FIELD
FFREQH
RESET
00H
R/W
R/W
ADDR
FFAH
3
2
1
0
3
2
1
0
Hex Address: FFB
.
Flash Frequency Low Byte Register (FFREQL)
BITS
7
6
5
4
FIELD
FFREQL
RESET
00H
R/W
R/W
ADDR
FFBH
eZ8 CPU
Refer to the eZ8 CPU User Manual (UM0128).
Op Code Maps
The following two figures provide information about each of the eZ8 CPU instructions.
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
366
0
0
1
2
3
4
5
Upper Nibble (Hex)
6
7
8
1
A
B
C
D
E
F
3
4
5
6
Lower Nibble (Hex)
7
8
9
1.1
2.2
2.3
2.4
3.3
3.4
3.3
3.4
BRK
SRP
ADD
ADD
ADD
ADD
ADD
ADD
IM
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
RLC
RLC
ADC
ADC
ADC
ADC
ADC
ADC
4.3
4.3
IR1,IM ER2,ER1 IM,ER1
A
2.3
ADDX ADDX DJNZ
4.3
r1,X
4.3
ADCX ADCX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
IR1,IM ER2,ER1 IM,ER1
4.3
4.3
SUBX SUBX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
DEC
DEC
SBC
SBC
SBC
SBC
SBC
SBC
IR1,IM ER2,ER1 IM,ER1
4.3
B
C
D
E
F
2.2
2.2
3.2
1.2
1.2
JR
LD
JP
INC
NOP
cc,X
r1,IM
cc,DA
r1
See 2nd
Op Code
Map
1.1
ATM
4.3
SBCX SBCX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
4.3
4.3
DA
DA
OR
OR
OR
OR
OR
OR
ORX
ORX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
POP
POP
AND
AND
AND
AND
AND
AND
IR1,IM ER2,ER1 IM,ER1
IR1,IM ER2,ER1 IM,ER1
4.3
4.3
ANDX ANDX
1.2
WDT
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4
4.3
4.3
1.2
TM
TM
TM
TM
TM
TM
TMX
TMX
HALT
PUSH PUSH
R2
IR2
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.5
2.6
2.5
2.8
3.2
3.3
3.4
3.5
LDE
LDEI
LDX
LDX
LDX
LDX
r1,Irr2
Ir1,Irr2
r1,ER2
DECW DECW
RR1
9
2
IRR1
4.3
1.2
STOP
IR1,IM ER2,ER1 IM,ER1
3.4
3.4
LDX3
LDX3
Ir1,ER2 IRR2,R1 IRR2,IR1 r1,rr2,X
rr1,r2,X
2.2
2.3
2.5
2.8
3.2
3.3
3.4
3.5
3.3
RL
RL
LDE
LDEI
LDX
LDX
LDX
LDX
LEA
R1
IR1
r2,Irr1
Ir2,Irr1
r2,ER1
2.5
2.6
INCW INCW
4.3
TCMX TCMX
Ir2,ER1 R2,IRR1 IR2,IRR1 r1,r2,X
3.5
LEA3
1.2
DI
1.2
EI
rr1,rr2,X
2.3
2.4
3.3
3.4
3.3
3.4
4.3
4.3
1.4
CP
CP
CP
CP
CP
CP
CPX
CPX
RET
RR1
IRR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.3
2.4
3.3
3.4
3.3
IR1,IM ER2,ER1 IM,ER1
3.4
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
R1,IM
IR1,IM ER2,ER1 IM,ER1
4.3
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
2.2
2.3
2.5
2.8
2.8
3.4
RRC
RRC
LDC
LDCI
2.3
JP2
LDC
LD
PUSHX3
r1,r2,X
ER2
R1
IR1
r1,Irr2
Ir1,Irr2
IRR1
Ir1,Irr2
2.2
2.3
2.5
2.8
2.6
2.2
SRA
SRA
LDC
LDCI CALL2 BSWAP CALL
3.3
3.4
4.3
XORX XORX
3.3
1.2
RCF
3.3
LD
POPX3
ER1
1.5
IRET
1.2
SCF
R1
IR1
r2,Irr1
Ir2,Irr1
IRR1
R1
DA
r2,r1,X
2.2
2.3
2.2
2.3
3.2
3.3
3.3
3.4
4.2
4.2
1.2
RR
RR
BIT
LD
LD
LD
LD
LD
LDX
LDX
CCF
R1
IR1
p,b,r1
r1,Ir2
R2,R1
IR2,R1
R1,IM
2.2
2.3
2.6
2.3
2.9
3.3
3.3
3.4
LD
MULT
LD
BTJ
BTJ
Ir1,r2
RR1
R2,IR1
p,b,r1,X
p,b,Ir1,X
SWAP SWAP TRAP
R1
IR1
Vector
IR1,IM ER2,ER1 IM,ER1
First Op Code Map
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
367
0
1
2
3
4
5
6
Lower Nibble (Hex)
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
Upper Nibble (Hex)
6
3.2
7
PUSH
IM
8
9
A
3.3
3.4
4.3
4.4
4.3
4.4
CPC
CPC
CPC
CPC
CPC
CPC
5.3
5.3
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
CPCX CPCX
B
C
3.2
3.3
SRL
SRL
R1
IR1
D
4.2
E
LDWX
ER2,ER1
F
Second Op Code Map After 1Fh
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8 Encore!® Motor Control Flash MCUs
Product Specification
368
PS024604-1005
PRELIMINARY
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
369
Index
Symbols
arithmetic instructions 282
assembly language programming 277
assembly language syntax 278
ATM 285
atomic 285
# 280
% 280
@ 280
Numerics
B
10-bit ADC 4
32-pin QFN and LQFP packages 8
A
absolute maximum ratings 257
AC characteristics 264
ADC 282
block diagram 200
electrical characteristics and timing 267
overview 199
ADC Channel Register 1 (ADCCTL) 203, 342
ADC Data High Byte Register (ADCDH) 204,
205, 208, 209, 314, 315, 343, 344
ADC Data Low Bit Register (ADCDL) 205, 206,
207, 344, 345, 346
ADC Timer Capture Register 208
ADCX 282
ADD 282
add - extended addressing 282
add with carry 282
add with carry—extended addressing 282
additional symbols 280
address space 13
ADDX 282
analog block/PWM signal synchronization 202
analog signals 10
analog-to-digital converter
overview 199
AND 285
ANDX 285
architecture
voltage measurements 199
PS024604-1005
B 280
b 279
baud rate generator, UART 127
BCLR 283
binary number suffix 280
BIT 283
bit 279
clear 283
manipulation instructions 283
set 283
set or clear 283
swap 283
test and jump 285
test and jump if non-zero 285
test and jump if zero 285
bit jump and test if non-zero 285
bit swap 285
block diagram 2
block transfer instructions 283
BRK 285
BSET 283
BSWAP 283, 285
BTJ 285
BTJNZ 285
BTJZ 285
C
calibration and compensation, motor control measurements 203
CALL procedure 285
cc 279
PRELIMINARY
Index
Z8FMC16100 Series Flash MCU
Product Specification
370
CCF 284
Change Log 306
characteristics
pin 11
characteristics, electrical 257
clear 284
clock phase (SPI) 152
CLR 284
COM 285
comparator
definition 195
noninverting/inverting input 195
operation 195
compare - extended addressing 282
compare with carry 282
compare with carry - extended addressing 282
complement 285
complement carry flag 283, 284
condition code 279
control register definition, UART 130
control register, I2C 186
CP 282
CPC 282
CPCX 282
CPU and peripheral overview 3
CPU control instructions 284
CPX 282
current measurement
architecture 199
operation 200
Customer Feedback Form 379
D
DA 279, 282
data register, I2C 184
DC characteristics 258
debugger, on-chip 241
DEC 282
decimal adjust 282
decrement 282
decrement and jump non-zero 285
decrement word 282
DECW 282
PS024604-1005
destination operand 280
device, port availability 35
DI 284
direct address 279
disable interrupts 284
DJNZ 285
DMA
controller 4
Document Information 305
Document Number Description 305
dst 280
E
EI 284
electrical characteristics 257
ADC 267
GPIO input data sample timing 271
watch-dog timer 267
electrical noise 199
enable interrupt 284
ER 279
extended addressing register 279
external pin reset 27
external RC oscillator 266
eZ8 CPU features 3
eZ8 CPU instruction classes 282
eZ8 CPU instruction notation 279
eZ8 CPU instruction set 277
eZ8 CPU instruction summary 286
F
FCTL register 217, 227, 361, 362
first opcode map 298, 366
FLAGS 280
flags register 280
flash
controller 4
option bit address space 224
option bit configuration - reset 224
program memory address 0000H 224
program memory address 0001H 225
PRELIMINARY
Index
Z8FMC16100 Series Flash MCU
Product Specification
371
flash memory
arrangement 212
byte programming 215
code protection 213
configurations 211
controller bypass 216
flash control register 217, 227, 361, 362
flash status register 218
frequency high and low byte registers 220
mass erase 216
operation 213
operation timing 213
page erase 216
page select register 218
FPS register 218
FSTAT register 218
G
general-purpose I/O 35
GPIO 4, 35
alternate functions 36
architecture 35
control register definitions 39
input data sample timing 271
interrupts 39
port A-C pull-up enable sub-registers 45
port A-H address registers 40
port A-H alternate function sub-registers 42,
47
port A-H control registers 41
port A-H data direction sub-registers 41
port A-H high drive enable sub-registers 44
port A-H input data registers 48
port A-H output control sub-registers 43
port A-H output data registers 49
port A-H STOP mode recovery sub-registers
44
port availability by device 35
port input timing 271
port output timing 272
PS024604-1005
H
H 280
HALT 284
halt mode 31, 284
hexadecimal number prefix/suffix 280
I
I2C 4
10-bit address read transaction 175
10-bit address transaction 172
10-bit addressed slave data transfer format
172, 180
7-bit address transaction 169, 177
7-bit address, reading a transaction 174
7-bit addressed slave data transfer format 171,
179
7-bit receive data transfer format 175, 181,
182
baud high and low byte registers 187, 188,
193
C status register 185, 189, 336, 337
controller 163
interrupts 167
operation 166
SDA and SCL signals 166
stop and start conditions 169
I2CBRH register 188, 190, 192, 193, 337, 338
I2CBRL register 188, 337
I2CCTL register 186, 336
I2CDATA register 184, 336
I2CSTAT register 185, 189, 336, 337
IM 279
immediate data 279
immediate operand prefix 280
INC 282
increment 282
increment word 282
INCW 282
indexed 280
indirect address prefix 280
indirect register 279
indirect register pair 279
indirect working register 279
PRELIMINARY
Index
Z8FMC16100 Series Flash MCU
Product Specification
372
indirect working register pair 279
infrared encoder/decoder (IrDA) 145
instruction set, ez8 CPU 277
instructions
ADC 282
ADCX 282
ADD 282
ADDX 282
AND 285
ANDX 285
arithmetic 282
ATM 285
BCLR 283
BIT 283
bit manipulation 283
block transfer 283
BRK 285
BSET 283
BSWAP 283, 285
BTJ 285
BTJNZ 285
BTJZ 285
CALL 285
CCF 283, 284
CLR 284
COM 285
CP 282
CPC 282
CPCX 282
CPU control 284
CPX 282
DA 282
DEC 282
DECW 282
DI 284
DJNZ 285
EI 284
HALT 284
INC 282
INCW 282
IRET 285
JP 285
LD 284
LDC 284
PS024604-1005
LDCI 283, 284
LDE 284
LDEI 283
LDWX 284
LDX 284
LEA 284
load 284
logical 285
MULT 283
NOP 284
OR 285
ORX 285
POP 284
POPX 284
program control 285
PUSH 284
PUSHX 284
RCF 283, 284
RET 285
RL 285
RLC 286
rotate and shift 285
RR 286
RRC 286
SBC 283
SCF 283, 284
SRA 286
SRL 286
SRP 284
STOP 284
SUB 283
SUBX 283
SWAP 286
TCM 283
TCMX 283
TM 283
TMX 283
TRAP 285
watch-dog timer refresh 284
XOR 285
XORX 285
instructions, eZ8 classes of 282
interrupt control register 61
interrupt controller 4, 51
PRELIMINARY
Index
Z8FMC16100 Series Flash MCU
Product Specification
373
LDX 284
LEA 284
load 284
load constant 283
load constant to/from program memory 284
load constant with auto-increment addresses 284
load effective address 284
load external data 284
load external data to/from data memory and autoincrement addresses 283
load external to/from data memory and auto-increment addresses 284
load instructions 284
load using extended addressing 284
load word using extended addressing 284
logical AND 285
logical AND/extended addressing 285
logical exclusive OR 285
logical exclusive OR/extended addressing 285
logical instructions 285
logical OR 285
logical OR/extended addressing 285
low power modes 31
architecture 51
interrupt assertion types 54
interrupt vectors and priority 54
register definitions 55
software interrupt assertion 55
interrupt edge select register 46
Interrupt Port Select Register 47
interrupt request 0 register 55
interrupt request 1 register 57
interrupt return 285
interrupt vector listing 51
interrupts
SPI 156
UART 124
introduction 1
IR 279
Ir 279
IrDA
architecture 128, 145
block diagram 128, 145
control register definitions 148
operation 128, 145
receiving data 147
transmitting data 146
IRET 285
IRQ0 enable high and low bit registers 58
IRQ1 enable high and low bit registers 59
IRR 279
Irr 279
M
J
JP 285
jump, conditional, relative, and relative conditional
285
L
LD 284
LDC 284
LDCI 283, 284
LDE 284
LDEI 283, 284
LDWX 284
PS024604-1005
master interrupt enable 53
master-in, slave-out and-in 151
memory
program 14
MISO 151
MOSI 151
motor control measurements
calibration and compensation 203
interrupts 202
overview 199
MULT 283
multiply 283
multiprocessor mode, UART 118
N
noise, electrical 199
NOP (no operation) 284
PRELIMINARY
Index
Z8FMC16100 Series Flash MCU
Product Specification
374
notation
b 279
cc 279
DA 279
ER 279
IM 279
IR 279
Ir 279
IRR 279
Irr 279
p 279
R 279
r 279
RA 279
RR 279
rr 279
vector 280
X 280
notational shorthand 279
O
OCD
architecture 241
auto-baud detector/generator 244
baud rate limits 244
block diagram 241
breakpoints 245
commands 247
data format 243
DBG pin to RS-232 Interface 242
debug mode 243
debugger break 285
interface 241
serial errors 244
status register 254
timing 273
OCD commands
execute instruction (12H) 252
read data memory (0DH) 251
read OCD control register (05H) 249
read OCD revision (00H) 248
read OCD status register (02H) 249
read program counter (07H) 250
PS024604-1005
read program memory (0BH) 251
read program memory CRC (0EH) 251
read register (09H) 250
read runtime counter (03H) 249
step instruction (10H) 252
stuff instruction (11H) 252
write data memory (0CH) 251
write OCD control register (04H) 249
write program counter (06H) 249
write program memory (0AH) 250
write register (08H) 250
on-chip debugger 4
on-chip debugger (OCD) 241
on-chip debugger signals 10
opcode map
abbreviations 297
cell description 297
first 298, 366
second after 1FH 299, 367
operation 202
current measurement 200
voltage measurement timing diagram 201, 202
operational amplifier
operation 196
overview 195
Operational Description 67, 91, 111, 231, 239
OR 285
ordering information 302
ORX 285
oscillator signals 10
P
p 279
package
32-pin QFN and LQFP 8
part number description 304
PC 280
peripheral AC and DC electrical characteristics 265
PHASE=0 timing (SPI) 153
PHASE=1 timing (SPI) 154
pin characteristics 11
polarity 279
POP 284
PRELIMINARY
Index
Z8FMC16100 Series Flash MCU
Product Specification
375
pop using extended addressing 284
POPX 284
port availability, device 35
port input timing (GPIO) 271
port output timing, GPIO 272
power supply signals 11
power-on reset (POR) 25
precharacterization product 304
program control instructions 285
program counter 280
program memory 14
PUSH 284
push using extended addressing 284
PUSHX 284
PxADDR register 40, 355, 356, 358
PxCTL register 41, 355, 357, 358
R
R 279
r 279
RA
register address 279
RCF 283, 284
receive
7-bit data transfer format (I2C) 175, 181, 182
IrDA data 147
receiving UART data-interrupt-driven method 116
receiving UART data-polled method 115
register 160, 279, 340
baud low and high byte (I2C) 187, 188, 193
baud rate high and low byte (SPI) 162
control (SPI) 158
control, I2C 186
data, SPI 157
flash control (FCTL) 217, 227, 361, 362
flash high and low byte (FFREQH and FREEQL) 220
flash page select (FPS) 218
flash status (FSTAT) 218
GPIO port A-H address (PxADDR) 40, 355,
356, 358
GPIO port A-H alternate function sub-registers
43, 48
PS024604-1005
GPIO port A-H control address (PxCTL) 41,
355, 357, 358
GPIO port A-H data direction sub-registers 42
I2C baud rate high (I2CBRH) 188, 190, 192,
193, 337, 338
I2C control (I2CCTL) 186, 336
I2C data (I2CDATA) 184, 336
I2C status 185, 189, 336, 337
I2C status (I2CSTAT) 185, 189, 336, 337
I2Cbaud rate low (I2CBRL) 188, 337
mode, SPI 160
OCD status 254
SPI baud rate high byte (SPIBRH) 162, 341
SPI baud rate low byte (SPIBRL) 162, 341
SPI control (SPICTL) 158, 339
SPI data (SPIDATA) 157, 338
SPI status (SPISTAT) 159, 339
status, SPI 159
UARTx baud rate high byte (UxBRH) 140
UARTx baud rate low byte (UxBRL) 141, 335
UARTx Control 0 (UxCTL0) 135, 140, 333,
334, 335
UARTx control 1 (UxCTL1) 136, 138, 139,
334
UARTx receive data (UxRXD) 130, 333
UARTx status 0 (UxSTAT0) 131, 132, 333
UARTx status 1 (UxSTAT1) 133, 334
UARTx transmit data (UxTXD) 130, 332
watch-dog timer control (WDTCTL) 233,
235, 347, 348
watch-dog timer reload high byte (WDTH) 66,
360
watch-dog timer reload low byte (WDTL) 66,
361
Register File
address map 17
register file 13
register pair 279
register pointer 280
registers
ADC channel 1 203, 342
ADC data high byte 204, 205, 208, 209, 314,
315, 343, 344
PRELIMINARY
Index
Z8FMC16100 Series Flash MCU
Product Specification
376
ADC data low bit 205, 206, 207, 344, 345,
346
reset
and STOP mode characteristics 23
and STOP mode recovery 23
carry flag 283
controller 4
RET 285
return 285
RL 285
RLC 286
rotate and shift instructions 285
rotate left 285
rotate left through carry 286
rotate right 286
rotate right through carry 286
RP 280
RR 279, 286
rr 279
RRC 286
S
SBC 283
SCF 283, 284
SCK 151
SDA and SCL (IrDA) signals 166
second opcode map after 1FH 299, 367
serial clock 152
serial peripheral interface (SPI) 149
set carry flag 283, 284
set register pointer 284
shift right arithmetic 286
shift right logical 286
signal descriptions 9
SIO 4
slave data transfer formats (I2C) 172, 180
slave select 152
software trap 285
source operand 280
SP 280
SPI
architecture 149
baud rate generator 156
PS024604-1005
baud rate high and low byte register 162
clock phase 152
configured as slave 150
control register 158
data register 157
error detection 155
interrupts 156
mode fault error 155
mode register 160
multi-master operation 154
operation 151
overrun error 155
signals 151
single master, multiple slave system 150
single master, single slave system 149
status register 159
timing, PHASE = 0 153
timing, PHASE=1 154
SPI mode (SPIMODE) 160, 340
SPIBRH register 162, 341
SPIBRL register 162, 341
SPICTL register 158, 339
SPIDATA register 157, 338
SPIMODE register 160, 340
SPISTAT register 159, 339
SRA 286
src 280
SRL 286
SRP 284
SS, SPI signal 151
stack pointer 280
STOP 284
STOP mode 31, 284
STOP mode recovery
sources 28
using a GPIO port pin transition 28
using watch-dog timer time-out 28
SUB 283
subtract 283
subtract - extended addressing 283
subtract with carry 283
subtract with carry - extended addressing 283
SUBX 283
SWAP 286
PRELIMINARY
Index
Z8FMC16100 Series Flash MCU
Product Specification
377
swap nibbles 286
symbols, additional 280
system and core resets 24
T
TCM 283
TCMX 283
test complement under mask 283
test complement under mask - extended addressing
283
test under mask 283
test under mask - extended addressing 283
timer signals 9
timers 4, 91
architecture 67, 91
block diagram 68, 92
capture mode 99
compare mode 101
continuous mode 95
counter mode 96
gated mode 101
operating mode 93
PWM mode 97
reading the timer count values 102
reload high and low byte registers 76, 104
timers 0-3
control registers 106, 107
high and low byte registers 75, 77, 102, 105
timing diagram, voltage measurement 201, 202
TM 283
TMX 283
transmit
IrDA data 146
transmitting UART data-interrupt-driven method
114
transmitting UART data-polled method 113
TRAP 285
U
UART 4
architecture 111
asynchronous data format without/with parity
PS024604-1005
113
baud rate generator 127
baud rates table 142, 143
control register definitions 130
controller signals 9
data format 112
interrupts 124
multiprocessor mode 118
receiving data using interrupt-driven method
116
receiving data using the polled method 115
transmitting data using the interrupt-driven
method 114
transmitting data using the polled method 113
x baud rate high and low registers 140
x control 0 and control 1 registers 134, 136
x status 0 and status 1 registers 131, 133
UxBRH register 140
UxBRL register 141, 335
UxCTL0 register 135, 140, 333, 334, 335
UxCTL1 register 136, 138, 139, 334
UxRXD register 130, 333
UxSTAT0 register 131, 132, 333
UxSTAT1 register 133, 334
UxTXD register 130, 332
V
vector 280
voltage brown-out reset (VBR) 25
voltage measurement timing diagram 201, 202
W
watch-dog timer
approximate time-out delay 64
approximate time-out delays 63, 231, 239
control register 233, 234
electrical characteristics and timing 267
interrupt in normal operation 64
interrupt in STOP mode 64
operation 63, 231, 239
refresh 64, 284
reload unlock sequence 65
PRELIMINARY
Index
Z8FMC16100 Series Flash MCU
Product Specification
378
reload upper, high and low registers 65
reset 26
reset in normal operation 65
reset in STOP mode 65
time-out response 64
WDTCTL register 233, 235, 347, 348
WDTH register 66, 360
WDTL register 66, 361
working register 279
working register pair 279
X
X 280
XOR 285
XORX 285
Z
Z8 Encore!
block diagram 2
introduction 1
PS024604-1005
PRELIMINARY
Index
Z8FMC16100 Series Flash MCU
Product Specification
379
Customer Feedback Form
The Z8FMC16100 Series MCU Product Specification
If you experience any problems while operating this product, or if you note any inaccuracies while reading
this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return
Information, below). We also welcome your suggestions!
Customer Information
Name
Country
Company
Phone
Address
Fax
City/State/Zip
Email
Product Information
Serial # or Board Fab #/Rev. #
Software Version
Document Number
Host Computer Description/Type
Return Information
ZiLOG
System Test/Customer Support
532 Race Street
San Jose, CA 95126
Phone: (408) 558-8500
Fax: (408) 558-8536
Problem Description or Suggestion
Provide a complete description of the problem or your suggestion. If you are reporting a specific problem,
include all steps leading up to the occurrence of the problem. Attach additional pages as necessary.
_____________________________________________________________________________________________
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PS024604-1005
PRELIMINARY
Customer Feedback Form