Data Sheet TLE 7230R Smart Octal Low-Side Switch Features Product Summary ♦ Protection Supply voltage VS 4.5 – 5.5 V Overload, short circuit Drain source clamping voltage VDS(AZ)max 60 V Overtemperature Overvoltage On resistance RON 0.8 Ω ♦ Low Quiescent Current< 10µA ♦ 16 bit SPI (for Daisychain) ♦ Direct Parallel Control of Four Channels ♦ PWM input (demux) ♦ Parallel Inputs High or Low Active Programmable ♦ Programmable functions Boolean operation Overload behavior Overtemperature behavior Switching time Power PG-DSO 36-47 ♦ General Fault Flag ♦ Digital Ports Compatible to 5V and 3,3 V Micro Controllers ♦ Electrostatic Discharge (ESD) Protection ♦ Full reverse current capability without latch up ♦ Green Product (RoHS compliant) ♦ AEC qualified Application • µC-compatible 8-channel low-side switch • Switch for Automotive and Industrial Applications • Solenoids, Relays and Resistive Loads General description The TLE 7230 R is an Octal Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and eight open drain DMOS output stages. It is protected by embedded protection functions and designed for automotive and industrial applications. The output stages are controlled via an SPI Interface. Additionally, four channels can be controlled in parallel for PWM applications. These features make the TLE 7230 R particularly suitable for engine management and body systems. Detailed Block Diagram PRG GND RESET FAULT VS VDO VS VBB Protection Functions IN1 IN2 as Ch. 1 IN3 as Ch. 1 LOGIC Output Stage IN4 as Ch. 1 16 SCLK SI CS OUT1 8 Serial Interface SPI 4 1 Output Control Buffer 8 OUT8 SO V3.4 GND Page 1 2009-07-15 Data Sheet TLE 7230R Power SO 36 package Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Symbol GND NC NC OUT1 OUT2 IN1 IN2 VS Reset CS PRG IN3 IN4 OUT3 OUT4 NC NC GND GND NC NC OUT5 OUT6 NC VDO 26 27 28 29 30 31 32 33 34 35 36 Fault SO SCLK SI NC NC OUT7 OUT8 NC NC GND Pin Configuration (Top view) Function Ground not connected not connected Output Channel 1 Output Channel 2 Input Channel 1 Input Channel 2 Supply Voltage Reset Chip Select Program Input Channel 3 Input Channel 4 Output Channel 3 Output Channel 4 not connected not connected Ground Ground not connected not connected Output Channel 5 Output Channel 6 not connected Supply for digital Outputs General Fault Flag Serial Data Output Serial Clock Serial Data Input not connected not connected Output Channel 7 Output Channel 8 not connected not connected Ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND NC NC Out1 Out2 IN1 IN2 VS Reset CS PRG IN3 IN4 Out3 Out4 NC NC GND GND NC NC Out8 Out7 NC NC SI SCLK SO Fault VDO NC Out6 Out5 NC NC GND 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 Power- PG-DSO-36 Heat Slug internally connected to ground pins V3.4 Page 2 2009-07-15 Data Sheet TLE 7230R Maximum Ratings for Tj = – 40°C to 150°C Parameter Supply Voltage Continuous Drain Source Voltage (OUT1...OUT8) Symbol VS, V VDO VDS Values -0.3 ... + 6 48 Unit V V Input Voltage, All Inputs and Data Lines Operating Temperature Range Storage Temperature Range Output Current per Channel (see el. characteristics) VIN Tj Tstg ID(lim) - 0.3 ... + 6 - 40 ... + 150 - 55 ... + 150 ID(lim)min V °C Reverse current per channel IR - ID(lim)min A A Output Clamping Energy per channel (single pulse, triangular shape, individual switch off) ID = 0.3 A, TJ(start) = 150°C ID = 0.4 A, TJ(start) = 85°C Output Clamping Energy per channel (repetitive pulses, triangular shape) ID = 0.25 A, TJ(aver.) = 150°C, repetitive (1⋅ 106 cycles) EAS Maximum Battery Voltage for full OVL = 0 4 short circuit protection (single pulse) OVL = 1 Electrostatic Discharge Voltage (Human Body Model) HBM according to EIA/JESD 22-A114 Output 1-8 Pins All other Pins VBAT(SC) 20 28 V VESD VESD 2000 2000 V V mJ 50 65 EAR mJ 15 DIN Humidity Category, DIN 40 040 IEC Climatic Category, DIN IEC 68-1 E 40/150/56 Thermal Characteristics Parameter Symbol Thermal Resistance, Junction – Case (all channels active, 0.3W power dissipation each channel) (only one channel active, 0.5W power dissipation) RthJC V3.4 Page 3 Values min max --- 2.6 12 Unit K/W 2009-07-15 Data Sheet TLE 7230R Electrical Characteristics Parameter and Conditions VS = 4.5 to 5.5 V ; VVDO = 3.0 to 5.5V; Tj = - 40 °C to + 150 °C ; Reset = H (unless otherwise specified) Symbol Values min Unit typ max -- 5.5 V 5.5 V 1. Power Supply, Reset Supply Voltage1 VS 4.5 Supply Voltage Digital Output VVDO 3.0 Supply Current Supply Current (reset mode) IS IS(reset) --- 3 5 10 mA µA tReset,min 10 -- -- µs TJ = 25°C 2 TJ = 150°C RDS(ON) --- 0.8 -- 1 1.7 Ω Output OFF VDS(AZ) 48 -- 60 V ID(lim) 1 2 A ID(lkg) -- 2 µA tON -- 15 60 µs tOFF -- 15 60 µs 3. Digital Inputs Input Low Voltage Input High Voltage Input Voltage Hysteresis VINL VINH VINHys - 0.3 2.0 --100 1.0 -- V V mV Input Pull Down/Up Current (IN1 ... IN4) PRG, Reset Pull Up Current Input Pull Down Current (SI, SCLK) IIN(1..4) IIN(PRG,Res) IIN(SI,SCLK) 20 20 10 50 50 20 100 100 50 µA µA µA Input Pull Up Current (CS) IIN(CS) 10 20 50 µA Reset = L Minimum Reset Duration 2. Power Outputs ON Resistance VS = 5 V; ID = 500 mA Output Clamping Voltage Current Limit Output Leakage Current VReset = L Tj =125°C ; Vbb=13.5V Turn-On Time SLE = 0 ID = 0.5 A, resistive load SLE = 1 Turn-Off Time SLE = 0 ID = 0.5 A, resistive load SLE = 1 4. Digital Outputs (SO, Fault) SO High State Output Voltage SO Low State Output Voltage ISOH = 2 mA VVDO = 5V VVDO = 3V ISOL = 2.5 mA VSOH V VVDO–0.4 -- -- VVDO–0.6 Output Tristate Leakage Current, CS = H, 0 ≤ VSO ≤ VS Fault Output Low Voltage IFAULT = 1.6 mA 1 -- VSOL -- -- 0.4 V ISOlkg VFAULTL -10 -- 0 -- 10 0.4 µA V For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely switched off. The undervoltage reset becomes active at VS = 3V (typ. value) and is specified by design. Not subject to production test. V3.4 Page 4 2009-07-15 Data Sheet TLE 7230R Electrical Characteristics cont. Parameter and Conditions VS = 4.5 to 5.5 V; VVDO = 3.0 to 5.5V; Tj = - 40 °C to + 150 °C ; Reset = H (unless otherwise specified) Symbol Values min Unit typ max 5. Diagnostic Functions Open Load Detection Voltage VDS(OL) VS -2.5 VS -2 Output Pull Down Current IPD(OL) 50 Fault Delay Time Overload switch off delay time td(fault) Td(off) 50 10 Short to Ground Detection Voltage Short to Ground Detection Current VDS(SHG) ISHG VS -3.6 VS -3.0 VS -2.6 V -50 -100 -150 µA Overload Threshold Current Overtemperature Shutdown Threshold2,4 Hysteresis2 ID(OVL) 1...8 Tth(sd) Thys 1 170 -- 6. SPI-Timing (for VVDO = 4.5V to 5.5V) Serial Clock Frequency (depending on SO load) Serial Clock Period (1/fclk) fSCK VS -1.3 V 90 150 µA 100 200 50 µs µs -10 2 200 -- A °C K tp(SCK) DC 200 --- 5 -- MHz ns tSCKH tSCKL tlead 50 50 250 ---- ---- ns ns ns Enable Lag Time (falling edge of CLK to rising edge ofCS) tlag 250 --- -- ns Data Setup Time (required time SI to falling of CLK) Data Hold Time (falling edge of CLK to SI) Disable Time2 tSU tH tDIS 20 20 -- ---- --150 ns ns ns Transfer Delay Time3 (CS high time between two accesses) Data Valid Time (for VVDO = 4.5V to 5.5V) tdt 200 -- -- ns tvalid ---- 100 120 150 ns tvalid ---- 100 140 240 ns Serial Clock High Time Serial Clock Low Time Enable Lead Time (falling edge of CS to rising edge of CLK) Data Valid Time (for VVDO = 3.0V to 3.6V) 2 3 CL = 50 pF2 CL = 100 pF2 CL = 220 pF2 CL = 50 pF2 CL = 100 pF2 CL = 220 pF2 This parameter is not subject to production test. Specified by design. This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay time td(fault)max = 200µs. V3.4 Page 5 2009-07-15 Data Sheet TLE 7230R Functional Description The TLE 7230 R is an octal low-side power switch with a serial peripheral interface (SPI) for control and diagnostic feedback of the 8 power DMOS switches. The power transistors are protected4 against overload (current limitation), overtemperature and overvoltage (by active zener clamping). The diagnostic logic recognizes a fault condition which can be read out via the serial diagnostic output (SO). Output Stage Control: Parallel Control or SPI Control The Output stages can be controlled by parallel Inputs or by SPI commands. The IC can be programmed via SPI to switch the outputs according to the corresponding SPI command bit or to a combination of SPI bit and parallel input signal. The Boolean logic combination of parallel and serial signal is programmable by SPI to logic "AND" or "OR". The respective SPI data bits are active high and the parallel Inputs are active high or low according to the PRG pin (see pin description). Boolean operation: The logic combination of the parallel and the serial input signal can be configured by an SPI command for each of the 8 channels individually. Logic "AND" or logic "OR" is possible. parallel in off off on on serial in off on off on Output "OR" off on on on Output "AND" off off off on Map able parallel input (IN 4): The parallel input 4 (IN4) can be defined via SPI command as parallel input for one or more power outputs. Depending on the Input Map Register this input can be used to control one up to eight of the parallel outputs. Default operation: IN4 is the parallel input for channel 4. Input Map register Input buffer IN n (1..3) Input buffer IN 4 Boolean register Input buffer IN 4 Boolean register & & Output Latch ≥1 Output Latch ≥1 serial controll register Channel 4 to 8 serial controll register Channel 1 to 3 Signal logic channel 1 to 3 Input Map register Signal logic channel 4 to 8 Switching speed / Slew rate: The switching speed / slew rate of each individual channel can be configured by SPI for slow or fast switching speed (max. 15µs or 60µs). Overtemperature Behavior: Each channel has an overtemperature sensor and is individually protected against overtemperature. As soon as an overtemperature event occurs, the channel is immediately turned off and the overtemperature information is reported by diagnosis. In this case, there are two different behaviors of the affected channel that can be selected by SPI (for all channels individually). • Auto restart: as long as the input signal of the channel remains on (e.g. parallel input high) the channel turns automatically on again after cooling down. • Latching: In the event of an overtemperature shutdown, the channel stays off until the overtemperature latch is reset by a new LàH transition of the input signal. 4 The integrated protection functions help to prevent damage to the device under fault conditions and may not be used in normal operation or permanently. V3.4 Page 6 2009-07-15 Data Sheet TLE 7230R Note: The overtemperature sensors of the output channels are only active if the channel is turned on. Low Quiescent Current Mode (Sleep Mode) : By applying a low signal at the Reset Pin, the device can be set to sleep mode. In this mode, all outputs are turned off, diagnosis and biasing are disabled, the diagnosis and the on/off register are reset and the current consumption is drastically reduced (<10µA). Once the reset signal returns to high, all outputs except for those controlled by parallel inputs remain off. Overload Protection: The IC can be programmed to react in different ways to overload. • Only Current limit: The IC actively limits the current to the specified current limit value. If the current limitation is active for longer than the fault filtering time, a fault is reported and stored in the Fault register. Unless the channel reaches the overtemperature shutdown threshold, the channel is not shutdown. • Current limit + shutdown: The IC actively limits the current to the specified current limit value. If this current limit is active for more than the specified Overload switch off delay time the affected channel is turned off and the fault is reported and stored in the fault register. To turn on the channel again this overload latch must be reset with a Là H transition of the input signal (parallel /SPI depending on the programmed operation). Pin description: OUTPUT 1 to 8 – Drain pins of the 8 channels. Output pins to connect to loads. GND – Ground pins. IN 1 to 3 – Parallel Input Pins of the channels 1 to 3 IN 4 – Mapable parallel Input Pin. Can be assigned to different outputs by SPI command. Default Output is OUT4 PRG - Program pin. PRG = High (VS): Parallel inputs 1 to 4 are high active PRG = Low (GND): Parallel inputs 1 to 4 are low active. If the parallel input pins are not connected (independent of high or low activity) it is guaranteed that the channels 1 to 4 are switched OFF. PRG pin itself is internally pulled up when not connected. Reset - If the reset pin is in a logic low state, it clears the SPI shift register and switches all outputs OFF. An internal pull-up structure is provided on chip. Fault - There is a general fault pin (open drain) which shows a high to low transition as soon as an error occurs at any one of the eight channels. This fault indication can be used to generate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called after this fault indication. This saves processor time compared to a cyclic reading of the SO information. VDO – Supply pin of the Signal Output (SO) pin of the SPI interface . This pin can be used to vary the high-state output voltage of the SO pin. Vs – Logic supply pin. This pin is used to supply the integrated circuitry. V3.4 Page 7 2009-07-15 Data Sheet TLE 7230R CS – Chip Select of the Serial Peripheral Interface SO – Signal Output of the Serial Peripheral Interface SI – Signal Input of the Serial Peripheral Interface. The pin has an internal pull down structure. SCLK – Clock Input of the Serial Peripheral Interface. The pin has an internal pull down structure SPI The SPI is a Serial Peripheral Interface with 4 digital pins and a 16 bit shift register. The SPI is used to configure and program the device, turn on and off channels and to read detailed diagnostic information. CS SCLK SI SO SPI SPI Signal Description: CS - Chip Select. The system microcontroller selects the TLE 7230 R by means of the CS pin. Whenever the pin is in a logic low state, data can be exchanged between the µC and TLE 7230 R. LSB CS = H: Any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. MSB internal logic registers CS = HàL: • diagnostic information is transferred from the diagnosis register into the SPI shift register. (in sleep mode no transfer of diagnostic information) • serial input data can be clocked into the SPI shift register from then on • SO changes from high impedance state to logic high or low state corresponding to the SO bits CS SI SO Serial input data MSB first 16 bit SPI shift register CS Serial output (diagnosis) data MSB first diagnosis register LSB MSB CS = L: SPI functions as a shift register. With each clock signal at the SCLK pin the state of the SI is read into the SPI shift-register (falling clock edge) and one diagnosis bit is written out of SO (rising edge). CS = LàH: • transfer of SI bits from SPI shift register into the internal logic registers sent command is valid • reset of diagnosis register if sent command is valid To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low transition of CS. The SPI of the TLE 7230 R has an integrated modulo 8 counter. If the number of clock signals is not an integer multiple of 8 the SPI will not accept the data in the shift register and the fault register will not be reset. SCLK - Serial Clock. The serial clock pin clocks the internal SPI shift register of the TLE 7230 R. The serial input (SI) accepts data into the input SPI shift register on the falling edge while the serial output (SO) shifts diagnostic information out of the SPI shift register on the rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select (CS) makes any transition. V3.4 Page 8 2009-07-15 Data Sheet TLE 7230R SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit (MSB) first. SI information is read in on the falling edge. Input data is latched in the SPI shift register and then transferred to the internal registers of the logic. The input data consist of 16 bit, made up of x control bits and y data bits. The control bits are used address the desired SPI register and the data bits are used to program in user-specified settings. SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit (MSB) first. SO is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin following the rising edge. SPI Control and Commands: MSB SI: 14 CMD 13 12 11 x x x 10 9 8 6 5 4 ADDR SO: SO standard diagnosis Ch 8 Ch 7 SO: SO after read command in previous frame 0 1 0 0 0 ADDR CMD 7 Ch 6 3 2 1 LSB DATA Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 DATA Command: 0 0 : Diagnosis Only : Reads out the diagnosis register. This command has no other influence on the device. 0 1 : Read register : With the next SO data frame the content of the addressed register will be sent. 1 0 : Reset Registers: Resets back all internal registers. Logic registers to default and Fault registers to no error. 1 1 : Write register : The data of the SI word will be written to the addressed register. No valid Commands: If the first 8 bit of the SI word contains an invalid command, it will not result in any reaction by the TLE 7230 R (register value change, switching channels, ...). Additionally an LàH of Chip Select (CS) will not reset the diagnosis register. ADDR Address: Pointer to register for read and write command DATA Data: Data written to or read from register selected by address ADDR Ch x Standard diagnosis for channel x: For details see "SPI Diagnostics" V3.4 Page 9 2009-07-15 Data Sheet TLE 7230R Register Description: Name Nr. 7 6 5 4 3 2 1 0 ADDR default MAP BOL OVL OVT SLE STA CTL 1 2 3 4 5 6 7 Ch8 Ch8 Ch8 Ch8 Ch8 OUT8 Ch8 Ch7 Ch7 Ch7 Ch7 Ch7 OUT7 Ch7 Ch6 Ch6 Ch6 Ch6 Ch6 OUT6 Ch6 Ch5 Ch5 Ch5 Ch5 Ch5 OUT5 Ch5 Ch4 Ch4 Ch4 Ch4 Ch4 OUT4 Ch4 Ch3 Ch3 Ch3 Ch3 Ch3 OUT3 Ch3 Ch2 Ch2 Ch2 Ch2 Ch2 OUT2 Ch2 Ch1 Ch1 Ch1 Ch1 Ch1 OUT1 Ch1 001 010 011 100 101 110 111 08H 00H 00H 00H 00H 00H 00H Input Mapping Register (MAP) Defines to which outputs the input IN4 is assigned (can be one up to all) 0.. No connection to IN4 1.. Output can be controlled with IN4 pin Boolean operation Register (BOL) The logic operation for serial and parallel control signal can be individually defined for each channel. 0.. Logic "OR" 1.. Logic "AND" Overload Behavior Register (OVL) The overload behavior of individual channels can be defined. 0.. Current limit without shutdown of the channel 1.. Current limit with latching overload shutdown of the channel Overtemperature Behavior Register (OVT) The overtemperature behavior of individual channels can be defined 0.. Auto restart after cooling down 1.. Latching shutdown on overtemperature Switching Speed / Slew Rate Register (SLE) The switching speed of individual channels can be defined. 0.. fast (10µs) 1.. slow (50µs) Output State Register (STA) Reads back the state of the output (this register is read-only) 0: DMOS off 1: DMOS on Serial Output Control Register (CTL) Sets the serial control bits for switching of output stages. 0: Output off 1: Output on V3.4 Page 10 2009-07-15 Data Sheet TLE 7230R SPI Diagnostics: As soon as a fault occurs for longer than the fault filtering time, the fault information is latched into the diagnosis register (the Fault pin will also change from high to low state). A new error on the same channel will overwrite the old error report. Serial data out pin (SO) is in high impedance state when CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially. If the sent command is valid the rising edge of CS will reset all diagnosis registers and restart the fault filtering time. In case of an invalid command the device will ignore the data bits and the diagnosis register will not be reset at the rising CS edge. Figure 1: Two bits per channel diagnostic feedback Diagnostic Serial Data Out SO MSB LSB 15 3 Ch.8 HH HL LH LL 2 Ch.2 1 0 Ch.1 Normal function Overload , Shorted Load or Overtemperature Open Load (off) Short to GND For Full Diagnosis there are two dedicated diagnostic bits per channel, as shown in Figure 1. Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function. Overload, Shorted Load or Overtemperature: HL is set if the current limitation becomes active, i.e. in the event of an overload or short to supply event. Additionally, this bit combination is set in the event of overtemperature of the corresponding channel. Open load: LH is set if an open load is detected (in off state of the channel) Short to GND: LL is set if a short to ground condition is detected (in off state) Timing Figures Figure 5: Power Outputs VIN t VDS tON tOFF 80% 20% t V3.4 Page 11 2009-07-15 Data Sheet TLE 7230R Figure 6: Serial Interface Timing Diagram CS 0.7VS tdt 0.2 VS tlag tSCKH tlead 0.7VS SCLK 0.2VS tSCKL tSU tH 0.7VS SI 0.2VS Figure 7: Input Timing Diagram 0.7 V S SCLK CS 0.2 V S t valid t Dis SO 0.7 V VDO SO 0.2 V VDO SO 0.7 V VDO 0.2 V VDO SO Valid Time Waveforms V3.4 Enable and Disable Time Waveforms Page 12 2009-07-15 Data Sheet TLE 7230R (all dimensions in mm) PG-DSO 36-47 TLE 7230 R Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). V3.4 Page 13 2009-07-15 Data Sheet TLE 7230R Revision History Version V3.4 >V3.3 V3.3 -> V3.2 V3.1 -> V3.2 V3.4 Date 2009-07-15 2008-07-22 Changes Short to Ground Detection Voltage min limit changed from VS -3.4 to VS -3.6 Version Change : changed Package naming only 2007-06-11 Version Change 2007-06-11 Revision History cleaned – only “final” data sheet related contents Page 14 2009-07-15 Data Sheet TLE 7230R Edition 2009-07-1415 Published by Infineon Technologies AG 81726 Munich, Germany © 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. V3.4 Page 15 2009-07-15