SPICE Device Model Si7423DN Vishay Siliconix P-Channel 30-V (D-S) MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72636 24-May-04 www.vishay.com 1 SPICE Device Model Si7423DN Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data VGS(th) VDS = VGS, ID = −250 µA 1.8 Measured Data Unit Static Gate Threshold Voltage On-State Drain Current b Drain-Source On-State Resistanceb ID(on) rDS(on) V VDS = −5 V, VGS = −10 V 60 VGS = −10 V, ID = −11.7 A 0.014 0.014 VGS = −4.5 V, ID = −9 A 0.023 0.023 A Ω Forward Transconductanceb gfs VDS = −15 V, ID = −11.7 A 29 29 S Diode Forward Voltageb VSD IS = −3.2 A, VGS = 0 V −0.83 −0.76 V 34 37.5 VDS = −15 V, VGS = −10 V, ID = −11.7 A 5.8 5.8 9.6 9.6 Dynamica Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) 15 11 tr 11 10 72 74 25 50 Rise Time Turn-Off Delay Time Fall Time td(off) tf VDD = −15 V, RL = 15 Ω ID ≅ −1 A, VGEN = −10 V, RG = 6 Ω nC ns Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. www.vishay.com 2 Document Number: 72636 24-May-04 SPICE Device Model Si7423DN Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 72636 24-May-04 www.vishay.com 3