New Product Si5906DU Vishay Siliconix Dual N-Channel 30-V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) 30 RDS(on) (Ω) ID (A)a 0.031 at VGS = 10 V 6 0.040 at VGS = 4.5 V 6 • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • New Thermally Enhanced PowerPAK® ChipFET® Package - Small Footprint Area - Low On-Resistance - Thin 0.8 mm Profile • 100 % Rg Tested • Compliant to RoHS Directive 2002/95/EC Qg (Typ.) 8 nC PowerPAK ChipFET Dual APPLICATIONS • Network • System Power DC/DC D1 D2 Marking Code 3. 0 CD XXX m m m 1.8 m Lot Traceability and Date Code G1 G2 Part # Code Bottom View Ordering Information: Si5906DU-T1-GE3 (Lead (Pb)-free and Halogen-free) S1 S2 N-Channel MOSFET N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Drain-Source Voltage Gate-Source Voltage Symbol VDS VGS Continuous Drain Current (TJ = 150 °C) TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C Limit 30 ± 20 6a 6a a, b, c 6 5.3b, c 25 6a 1.9b, c 10.4 6.7 ID IDM Pulsed Drain Current TC = 25 °C TA = 25 °C TC = 25 °C TC = 70 °C Maximum Power Dissipation TA = 25 °C TA = 70 °C Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature)d, e Continuous Source-Drain Diode Current IS PD Unit V A 2.3b, c 1.5b, c - 55 to 150 260 TJ, Tstg W °C THERMAL RESISTANCE RATINGS Parameter b, f t≤5s Steady State Symbol RthJA RthJC Typical 43 9.5 Maximum 55 12 Unit Maximum Junction-to-Ambient °C/W Maximum Junction-to-Case (Drain) Notes: a. Package limited b. Surface Mounted on 1" x 1" FR4 board. c. t = 5 s. d. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 105 °C/W. Document Number: 65168 S09-1394-Rev. A, 20-Jul-09 www.vishay.com 1 New Product Si5906DU Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Symbol Test Conditions Min. VDS VGS = 0 V, ID = 250 µA 30 Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS Temperature Coefficient ΔVDS/TJ VGS(th) Temperature Coefficient ΔVGS(th)/TJ Gate-Source Threshold Voltage ID = 250 µA VGS(th) VDS = VGS , ID = 250 µA Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V Zero Gate Voltage Drain Current IDSS On-State Drain Currenta ID(on) Drain-Source On-State Resistancea Forward Transconductancea RDS(on) gfs V 33 mV/°C - 3.5 1.2 2.2 V ± 100 nA VDS = 30 V, VGS = 0 V 1 VDS = 30 V, VGS = 0 V, TJ = 55 °C 10 VDS ≥ 5 V, VGS = 10 V 20 µA A VGS = 10 V, ID = 4.8 A 0.025 0.031 VGS = 4.5 V, ID = 4.1 A 0.033 0.040 VDS = 15 V, ID = 4.8 A 14 Ω S b Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time 300 VDS = 15 V, VGS = 0 V, f = 1 MHz 72 VDS = 15 V, VGS = 10 V, ID = 6.6 A 5.7 8.6 2.9 4.4 34 tr 1.0 VDS = 15 V, VGS = 4.5 V, ID = 6.6 A VDD = 15 V, RL = 2.8 Ω ID ≅ 5.3 A, VGEN = 4.5 V, Rg = 1 Ω 0.3 1.8 3.6 10 15 90 135 12 20 tf 50 75 td(on) 5 10 15 25 tr td(off) nC 1.1 f = 1 MHz td(on) td(off) pF VDD = 15 V, RL = 2.8 Ω ID ≅ 5.3 A, VGEN = 10 V, Rg = 1 Ω tf 12 20 5 10 Ω ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulse Diode Forward Current ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb TC = 25 °C 6 25 IS = 6 A, VGS = 0 V IF = 5.3 A, dI/dt = 100 A/µs, TJ = 25 °C A 0.8 1.2 V 12 20 ns 5 10 nC 6 6 ns Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 % b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 65168 S09-1394-Rev. A, 20-Jul-09 New Product Si5906DU Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 25 10 VGS = 10 V thru 4 V 8 I D - Drain Current (A) I D - Drain Current (A) 20 15 10 VGS = 3 V 5 6 TC = - 55 °C 4 TC = 25 °C 2 TC = 125 °C 0 0.0 0.5 1.0 1.5 2.0 2.5 0 0.0 3.0 0.5 0.06 0.12 0.05 0.10 0.03 VGS = 10 V 0.02 0.01 2.5 3.0 0.08 0.06 VGS = 4.5 V 0.04 VGS = 10 V 0.02 0.00 0.00 0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 ID - Drain Current (A) ID - Drain Current (A) On-Resistance vs. Drain Current and Gate Voltage On-Resistance vs. Drain Current and Gate Voltage 10 400 ID = 6.6 A VGS - Gate-to-Source Voltage (V) 350 Ciss 300 C - Capacitance (pF) 2.0 Transfer Characteristics R DS(on) - On-Resistance (Ω) R DS(on) - On-Resistance (Ω) Output Characteristics VGS = 4.5 V 1.5 VGS - Gate-to-Source Voltage (V) VDS - Drain-to-Source Voltage (V) 0.04 1.0 250 200 150 Coss 100 8 VDS = 7.5 V 6 VDS = 24 V 4 VDS = 15 V 2 50 Crss 0 0 0 5 10 15 20 VDS - Drain-to-Source Voltage (V) Capacitance Document Number: 65168 S09-1394-Rev. A, 20-Jul-09 25 30 0 1 2 3 4 5 6 Qg - Total Gate Charge (nC) Gate Charge www.vishay.com 3 New Product Si5906DU Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 100 1.8 ID = 4.8 A 1.4 (Normalized) R DS(on) - On-Resistance I S - Source Current (A) VGS = 10 V 1.6 VGS = 4.5 V 1.2 1.0 TJ = 150 °C 10 TJ = 25 °C 1 0.8 0.6 - 50 - 25 0 25 50 75 100 125 0.1 0.0 150 0.3 TJ - Junction Temperature (°C) 0.6 0.9 1.2 VSD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Junction Temperature 2.0 0.08 1.8 0.06 ID = 4.8 A; TJ = 125 °C VGS(th) (V) R DS(on) - On-Resistance (Ω) 1.9 0.04 ID = 1 A; TJ = 125 °C 1.7 ID = 250 µA 1.6 1.5 ID = 4.8 A; TJ = 25 °C 1.4 0.02 ID = 1 A; TJ = 25 °C 1.3 1.2 - 50 0.00 0 2 4 6 8 10 - 25 0 25 50 75 VGS - Gate-to-Source Voltage (V) TJ - Temperature (°C) On-Resistance vs. Gate-to-Source Voltage Threshold Voltage 100 125 150 100 30 Limited by RDS(on)* 25 I D - Drain Current (A) 10 Power (W) 20 15 10 100 µs 1 1 ms 10 ms 100 ms 1 s, 10 s 0.1 5 0 0.001 TA = 25 °C Single Pulse 0.01 0.1 1 10 100 1000 Time (s) Single Pulse Power (Junction-to-Ambient) www.vishay.com 4 0.01 0.1 BVDSS Limited DC 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient Document Number: 65168 S09-1394-Rev. A, 20-Jul-09 New Product Si5906DU Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 16 12 Power Dissipation (W) I D - Drain Current (A) 10 12 8 Package Limited 8 6 4 4 2 0 0 0 25 50 75 100 TC - Case Temperature (°C) Current Derating* 125 150 25 50 75 100 125 150 TC - Case Temperature (°C) Power Derating * The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 65168 S09-1394-Rev. A, 20-Jul-09 www.vishay.com 5 New Product Si5906DU Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 Notes: 0.1 PDM t1 0.05 t2 t 1. Duty Cycle, D = t1 2 2. Per Unit Base = R thJA = 105 °C/W 0.02 3. TJM - TA = PDM Z thJA(t) 4. Surface Mounted Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.05 Single Pulse 0.01 10-4 0.02 10-3 10-2 Square Wave Pulse Duration (s) 10-1 1 Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?65168. www.vishay.com 6 Document Number: 65168 S09-1394-Rev. A, 20-Jul-09 Package Information Vishay Siliconix PowerPAK® ChipFET® SINGLE PAD D D (8) D (7) D (6) S (5) E D (1) D (2) D (3) G (4) Z C b A e A1 K D2 H D (1) L D (2) D (3) G (4) K1 DETAIL Z E2 E3 D3 D (8) D (7) D (6) S (5) Backside view of single pad MILLIMETERS INCHES DIM. MIN. NOM. MAX. MIN. NOM. A 0.70 0.75 0.85 0.028 0.030 MAX. 0.033 A1 0 - 0.05 0 - 0.002 0.014 b 0.25 0.30 0.35 0.010 0.012 C 0.15 0.20 0.25 0.006 0.008 0.010 D 2.92 3.00 3.08 0.115 0.118 0.121 D2 1.75 1.87 2.00 0.069 0.074 0.079 D3 0.20 0.25 0.30 0.008 0.010 0.012 E 1.82 1.90 1.98 0.072 0.075 0.078 E2 1.38 1.50 1.63 0.054 0.059 0.064 E3 0.45 0.50 0.55 0.018 0.020 0.022 e 0.65 BSC 0.026 BSC H 0.15 0.20 0.25 0.006 0.008 K 0.25 - - 0.010 - - K1 0.30 - - 0.012 - - L 0.30 0.35 0.40 0.012 0.014 0.016 Document Number: 73203 19-Jul-10 0.010 www.vishay.com 1 Package Information Vishay Siliconix PowerPAK® ChipFET® DUAL PAD D D1 (8) D1 (7) D2 (6) S2 (5) E SI (1) GI (2) S2 (3) G2 (4) Z A C b e A1 SI (1) GI (2) S2 (3) G2 (4) L K DETAIL Z E2 H D1 (8) D1 (7) D2 (6) D2 (5) K1 Backside view of dual pad MILLIMETERS INCHES DIM. MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.85 0.028 0.030 0.033 A1 0 - 0.05 0 - 0.002 b 0.25 0.30 0.35 0.010 0.012 0.014 C 0.15 0.20 0.25 0.006 0.008 0.010 D 2.92 3.00 3.08 0.115 0.118 0.121 D2 1.07 1.20 1.32 0.042 0.047 0.052 E 1.82 1.90 1.98 0.072 0.075 0.078 E2 0.92 1.05 1.17 0.036 0.041 0.046 e 0.65 BSC 0.026 BSC H 0.15 0.20 0.25 0.006 0.008 0.010 K 0.20 - - 0.008 - - K1 0.20 - - 0.008 - - L 0.30 0.35 0.40 0.012 0.014 0.016 ECN: C10-0618-Rev. C, 19-Jul-09 DWG: 5940 www.vishay.com 2 Document Number: 73203 19-Jul-10 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR PowerPAK® ChipFET® Dual 2.700 (0.106) 0.300 (0.012) 0.350 (0.014) 0.650 (0.026) 1.900 (0.075) 0.300 (0.012) 1.050 (0.041) 0.350 (0.014) 0.200 (0.008) 0.300 (0.012) 0.225 (0.009) 0.650 (0.026) 1.175 (0.046) 1.525 (0.060) Recommended Minimum Pads Dimensions in mm/(Inches) APPLICATION NOTE Note: This is Flipped Mirror Image Pin #1 Location is Top Left Corner Return to Index www.vishay.com 10 Document Number: 69949 Revision: 21-Jan-08 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1