CY7C197B 256 Kb (256K x 1) Static RAM General Description1 Features The CY7C197B is a high-performance CMOS Asynchronous SRAM organized as 256K × 1 bits that supports an asynchronous memory interface. The device features an automatic power-down feature that significantly reduces power consumption when deselected. • Fast access time: 12 ns and 25 ns • Wide voltage range: 5.0V ± 10% (4.5V to 5.5V) • CMOS for optimum speed/power • TTL-compatible Inputs and Outputs See the Truth Table in this data sheet for a complete description of read and write modes. • Available in 24 DIP and 24 SOJ The CY7C197B is available in 24 DIP and 24 SOJ package(s). Logic Block Diagram Din Sense Amps Row Decoder Input Buffer RAM Array Dout CE Column Decoder WE Power Down Circuit x Ax Product Portfolio 12 ns 25 ns Unit Maximum Access Time 12 25 ns Maximum Operating Current 150 95 mA Maximum CMOS Standby Current 10 10 mA Notes: 1. For best-practice recommendations, please refer to the Cypress application note System Design Guidelines at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05410 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 15, 2003 CY7C197B Pin Layout and Specifications 24 DIP (6.6 × 31.8 × 3.5 mm) – P13 A0 1 24 VCC A1 2 23 A17 A2 3 22 A16 A3 4 21 A15 A4 5 20 A14 A5 6 19 A13 A6 7 18 A12 A7 8 17 A11 A8 9 16 A10 Dout 10 15 A9 WE 11 14 Din GND 12 13 CE 24 SOJ (8 × 15 × 3.5 mm) – V13 Document #: 38-05410 Rev. ** A0 1 24 VCC A1 2 23 A17 A2 3 22 A16 A3 4 21 A15 A4 5 20 A14 A5 6 19 A13 A6 7 18 A12 A7 8 17 A11 A8 9 16 A10 Dout 10 15 A9 WE 11 14 Din GND 12 13 CE Page 2 of 10 CY7C197B Pin Description Pin Type Description DIP SOJ AX Input Address Inputs. CE Control Chip Enable. 13 13 Din Input Data Input Pins. 14 14 Dout Output Data Output Pins. 10 10 VCC Supply Power (5.0V). 24 24 WE Control Write Enable. 11 11 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 18, 19, 20, 21, 22, 23 23 Truth Table CE WE H X L L Mode Power High Z Deselect/Power-Down Standby (ISB) H Data Out Read Active (ICC) L Data In Write Active (ICC ) Document #: 38-05410 Rev. ** Input/Output Page 3 of 10 CY7C197B Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Value Unit TSTG Parameter Storage Temperature Description –65 to +150 °C TAMB Ambient Temperature with Power Applied (i.e., case temperature) –55 to +125 °C VCC Core Supply Voltage Relative to VSS –0.5 to +7.0 V VIN, VOUT DC Voltage Applied to any Pin Relative to VSS IOUT Output Short-Circuit Current VESD Static Discharge Voltage (per MIL-STD-883, Method 3015) > 2001 V ILU Latch-up Current > 200 mA –0.5 to VCC + 0.5 V 20 mA Operating Range Range Ambient Temperature (TA) Voltage Range (VCC) Commercial 0°C to 70°C 5.0V ± 10% DC Electrical Characteristics2 12 ns Parameter Description VIH Input HIGH Voltage VIL Input LOW Voltage Condition – 25 ns Min Max Min Max 2.2 –0.3 Unit VCC+0.3 2.2 VCC+0.3 V 0.8 –0.3 0.8 V VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 – 2.4 – V VOL Output LOW Voltage VCC = Min., lol = 8.0 mA – 0.4 – 0.4 V ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = FMAX = 1/tRC – 150 – 95 mA ISB1 Automatic CE Power-down Current TTL Inputs VCC = Max., CE ≥ VIH, VIN ≥ VIH or VIN ≤ VIL, f = FMAX – 30 – 30 mA ISB2 Automatic CE Power-down Current CMOS Inputs VCC = Max., CE ≥ VCC – 0.3v, VIN ≥ VCC – 0.3v or VIN < 0.3v, f = 0 – 10 – 10 mA IOZ Output Leakage Current GND ≤ Vi ≤ VCC, Output Disabled –5 +5 –5 +5 uA IIX Input Load Current –5 +5 –5 +5 uA GND ≤ Vi ≤ VCC Capacitance3 Max Parameter Description Conditions ALL – PACKAGES Unit CIN Input Capacitance pF Output Capacitance TA = 25C, f = 1 MHz, VCC = 5.0V 8 COUT 10 Notes: 2. VIL (min) = –2.0V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05410 Rev. ** Page 4 of 10 CY7C197B AC Test Loads Output Loads Output Loads for tHZOE, tHZCE & tHZWE R1 R3 VCC VCC Output C1 R2 C2 (A)* (B)* All Input Pulses Thevenin Equivalent Output R4 VCC 90% 90% VT Rth VSS 10% 10% Rise Time 1 V/ns Fall Time 1 V/ns * including scope and jig capacitance AC Test Conditions Parameter Description Nom. Unit C1 Capacitor 1 30 pF C2 Capacitor 2 5 R1 Resistor 1 480 R2 Resistor 2 255 R3 Resistor 3 480 R4 Resistor 4 255 RTH Resistor Thevenin 167 VTH Voltage Thevenin 1.73 Ω V Thermal Resistance4 Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Conditions All – Packages Unit Still Air, soldered on a 3 × 4.5 square inches, two-layer printed circuit board TBD °C/W TBD Notes: 4. Test conditions assume a transition time of 3 ns or less for –12 speed and 5 ns or less for –25 speed, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. Document #: 38-05410 Rev. ** Page 5 of 10 CY7C197B AC Electrical Characteristics5 6 7 12 ns Parameter Description Min 25 ns Max Min Max Unit tRC Read Cycle Time 12 – 25 – ns tAA Address to Data Valid – 12 – 25 ns tOHA Data Hold from Address Change 3 – 3 – ns tACE CE to Data Valid – 12 – 25 ns tLZCE CE to Low Z 3 – 3 – ns tHZCE CE to High Z – 5 – 11 ns tPU CE to Power-up 0 – 0 – ns tPD CE to Power-down – 12 – 20 ns tWC Write Cycle Time 12 – 25 – ns tSCE CE to Write End 9 – 20 – ns tAW Address Set-up to Write End 9 – 20 – ns tHA Address Hold from Write End 0 – 0 – ns tSA Address Set-up to Write Start 0 – 0 – ns tPWE WE Pulse Width 8 – 20 – ns tSD Data Set-up to Write End 8 – 15 – ns tHD Data Hold from Write End 0 – 0 – ns tHZWE WE LOW to High Z – 7 – 11 ns tLZWE WE HIGH to Low Z 2 – 3 – ns Notes: 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZCE and tLZCE are specified with CL = 5 pF as in part (B) in AC Test Loads and Waveforms. Transition is measured +/-500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05410 Rev. ** Page 6 of 10 CY7C197B Timing Waveforms Read Cycle No. 1 8 9 tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Read Cycle No. 2 8 tRC Address CE tHZCE tACE tLZCE High Z Data Out ICC Vcc Supply Current High Z Data Valid ISB tPU tPD 50% 50% Notes: 8. WE is HIGH for ready cycle. 9. Device is continuously selected, CE = VIL. Document #: 38-05410 Rev. ** Page 7 of 10 CY7C197B Write Cycle No. 1 (WE Controlled)7 tWC Address tSCE CE tAW tHA tPWE tSA WE tHD tSD Data Valid Data In tLZWE tHZWE Data Out Data Undefined High Impedance Write Cycle No. 2 (CE Controlled)7 10 tWC Address tSCE tSA CE tHA tAW tPWE WE tSD Data In Data Out tHD Data Valid High Z Notes: 10. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state. Document #: 38-05410 Rev. ** Page 8 of 10 CY7C197B Ordering Information Speed Ordering Code Package Name Package Type Power Option Operating Range 12 ns CY7C197B-12VC V13 24 SOJ (8 x 15 x 3.5 mm) Standard Commercial 25 ns CY7C197B-25PC P13 24 DIP (6.6 x 31.8 x 3.5 mm) Standard Commercial Package Diagram 24-Lead (300-Mil) Molded SOJ V13 51-85030-*A 24-Lead (300-Mil) PDIP P13 51-85013-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05410 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C197B Document History Page Document Title: CY7C197B 256 Kb (256K x 1) Static RAM Document Number: 38-05410 REV. ECN No. Issue Date Orig. of Change ** 129235 09/16/03 HGK Document #: 38-05410 Rev. ** Description of Change New Data Sheet Page 10 of 10