SiP1759
Vishay Siliconix
Buck-Boost Regulator
DESCRIPTION
FEATURES
The SiP1759 is a buck-boost regulating charge pump. It is
designed to provide a regulated output from 1 cell Li Ion or 2/
3 cell NiMH voltages found in handheld portable equipment,
1.6 V to 5.5 V. SiP1759 allows the option of a fixed 3.3 V
output voltage, or an adjustable output which can be set from
2.5 V to 5.5 V. The output current is up to 100 mA.
•
•
•
•
•
•
•
For flexibility in application, SiP1759 has a shutdown pin
(SD) and an ERROR output to indicate when the output
voltage is in regulation.
SiP1759 is available in a 10 pin MSOP package and is rated
over the industrial temperature range of - 40 °C to 85 °C.
Output voltage - fixed 3.3 V or adjustable from 2.5 V to 5.5 V
1.6 V to 5.5 V input voltage range
100 mA output current
60 µA quiescent current
Shutdown current < 1 µA
Short circuit crotection
Thermal shutdown
• MSOP-10 package
APPLICATIONS
•
•
•
•
1 cell Li ion battery powered equipment
2 to 3 cell NiMH battery powered equipment
2 to 3 cell alkaline battery powered equipment
Backup battery boost converters
TYPICAL APPLICATION CIRCUIT
CX
CX
CX-
CX+
VIN
CX-
VOUT
CX+
VIN
VOUT
PGND
CiN
R
SiP1759
SD
GND
ERROR
PGND
FB
COUT
CiN
R
SiP1759
SD
GND
R1
COUT
ERROR
PGND
FB
R2
Fixed Output
Document Number: 72949
S09-1453-Rev. D, 03-Aug-09
Adjustable Output Voltage
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SiP1759
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (all voltages referenced to GND = 0 V)
Parameter
Limit
Input Voltage (VIN)
Unit
- 0.3 to 6
OUT SD, FB, ERROR to GND
- 0.3 to 6
V
CX- to GND
- 0.3 to (VIN + 0.3)
CX+ to GND
- 0.3 to (the greater of VIN or VOUT) + 1)
Storage Temperature
- 55 to 150
Maximum Junction Temperature
°C
150
Power Dissipationa,b
MSOP-10 (TA = 70 °C)
444
mW
Notes:
a. Device Mounted with all leads soldered or welded to PC board.
b. Derate 5.6 mW/°C above 25 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE (all voltages referenced to GND = 0 V)
Parameter
Input Voltage Range
Limit
1.6 to 5.5
Output Voltage Adjustment Range
2.5 to 5.5
CIN
10
CX
0.33
COUT
Unit
V
µF
10
Operating Temperature Range
- 40 to 85
°C
SPECIFICATIONS
Parameter
Input Voltage Range
Input Undervoltage Lockout
Test Condition Unless Specified
VIN = VSD = 2 V, FB = PGND = GND
CIN = 10 µF, Cx = 0.33 µF, COUT = 10 µF
Temp.a
Min.
VIN
Full
1.6
VUVLO
Full
0.7
Full
2.5
0 °C to
85 °C
3.17
3.3
3.43
3.17
3.3
3.43
Symbol
Output Voltage Adjustment
Range
1.6 V ≤ VIN ≤ 5.5 V
2 V ≤ VIN ≤ 5.5 V, 1 mA ≤ IOUT ≤ 50 mA
Output Voltage
Maximum Output Current
VOUT
IOUT(max)
Transient Load Current
2.5 V ≤ VIN ≤ 5.5 V, 1 mA ≤ IOUT ≤ 100 mA
2 V ≤ VIN ≤ 5.5 V, 1 mA ≤ IOUT ≤ 50 mA
2.5 V≤ VIN ≤ 5.5 V, 1 mA ≤ IOUT ≤ 100 mA
Full
2.5 V ≤ VIN ≤ 5.5 V
Full
IOUT ≤ 100 mA (RMS)
0 °C to 85 °C
VIN = VSD = 4 V, VFB = 0 V, Stepping Down
1.0
5.5
3.15
3.45
3.15
3.45
100
100
5
VIN = 2 V, VOUT = 3.3 V, VSD = 0 V
Full
1
5
1 6 V ≤ VIN ≤ 5 5 V
Full
Output Leakage Current in
Shutdown
SD
Full
Full
0.25 * VIN
0.7 * VIN
VSD = 5.5 V
Full
-1
FB Regulation Voltage
VFB
VIN = 1.65 V, VOUT = 3.3 V
Full
1.205
FB Input Current
IIFB
VFB = 1.27 V
Full
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2
V
mA
200
1
1.6 V ≤ VIN ≤ 5.5 V, VSD = 0 V
SD Input Leakage Current
1.5
Full
IQSD
VIN = VSD = 2 V, VFB = 0 V, Stepping Up
Unit
5.5
100
Shutdown Supply Current
VIL
Max.
60
IQ
VIH
Typ.b
60
Quiescent Supply Current
SD Logic Input Voltage
Limits
- 40 °C to 85 °C
µA
V
1
µA
1.235
1.265
V
25
200
nA
Document Number: 72949
S09-1453-Rev. D, 03-Aug-09
SiP1759
Vishay Siliconix
SPECIFICATIONS
Parameter
Symbol
Temp.a
Internal feedback
Full
External feedback
Full
200
100
1.0
1.1
1.2
V
5
100
mV
0.01
0.2
µA
1.5
1.8
MHz
FB Dual Mode Threshold
ERROR Trip Voltage
ERROR Leakage Current
fOSC
Switching Frequency
Output Short-Circuit Current
Min.
Typ.b
Max.
100
50
Falling edge at FB
Full
IOL = 0.5 mA, VIN = 2 V
Full
VERROR = 5.5 V, VFB = 1.27 V
Full
1.6 V ≤ VIN ≤ 5.5 V, VFB = 1 V
Full
VOUT = 0 V, 2.5 V ≤ VIN ≤ 5.5 V
foldback current limit
Full
110
Temperature rising
Full
160
Full
20
Full
90
VOL
ERROR Output Low Voltage
Limits
- 40 °C to 85 °C
Test Condition Unless Specified
VIN = VSD = 2 V, FB = PGND = GND
CIN = 10 µF, Cx = 0.33 µF, COUT = 10 µF
Thermal Shutdown
Temperature
Thermal Shutdown Hysteresis
VIN = 3.6 V, IOUT = 10 mA
Efficiency
1.2
Unit
mV
mA
°C
%
Notes:
a. Full = as determined by the operating suffix.
b. Typical values are for Design Aid only, not guaranteed nor subject to production testing.
PIN CONFIGURATION AND TRUTH TABLE
ORDERING INFORMATION
MSOP-10
ERROR
1
10
FB
SD
2
9
VOUT
VIN
3
8
CX+
VIN
4
7
CX-
GND
5
6
PGND
Part Number
Temperature Range
SiP1759DH-T1
- 40 °C to 85 °C
Marking
1759
Eval Kit
Temperature Range
Board
SiP1759DB
- 40 °C to 85 °C
Surface Mount
Top View
PIN DESCRIPTION
Pin Number
Name
1
ERROR
Function
Open drain error flag - a low output indicates that the output voltage is out of range
2
SD
Shutdown input
3, 4
VIN
Input voltage
5
GND
6
PGND
7
CX-
Negative terminal of the charge pump capacitor
8
CX+
Positive terminal of the charge pump capacitor
9
VOUT
10
FB
Ground
Power ground
Regulated output voltage
Feedback input - connected to GND for fixed 3.3 V output. Connected to a resistive divider for an adjustable output
Document Number: 72949
S09-1453-Rev. D, 03-Aug-09
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SiP1759
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
VIN
PGND
CX-
CX+
S1
S2
VOUT
Control
SD
Bias
Oscillator
+
-
1.235 V
ERROR
+
-
FB
+
-
GND
+
+
-
+
-
DETAILED DESCRIPTION
The SiP1759 is a buck-boost regulating charge pump. This
allows for the VIN to be a higher or lower voltage than the
regulated output. This is done with a charge pump that when
VIN is lower than VOUT is a regulated voltage doubler. When
VIN is higher than VOUT the charge pump is a step down
gated switch.
In boost mode, the IC controls the transfer capacitor through
CX+ and CX- pins, switching the charge to the output keeping
it regulated. In this mode the charge pump only switches to
maintain regulation, the output ripple does not increase with
light loads. In buck mode, the CX- pin is internally connected
to PGND and the CX+ is switched internally between VIN and
VOUT. Unless VIN is significantly larger than VOUT (VIN ≥
VOUT + 1 V), in heavy load the IS will slip from buck mode to
boost mode as necessary to charge the transfer capacitor.
Shutdown Mode
The IC is designed to conserve power by decreasing current
consumption during normal operation as well as shutdown
mode. Pulling the SD pin logic low, the output is
disconnected from the input and is in high impedance; the
internal circuitry of the oscillator, control logic, and the
charge-pump switches are turned off, decreasing the current
consumption to less than 1 µA.
Undervoltage Lockout
Power OK Output
POK is an open-drain output that goes low when the
regulator feedback voltage falls below 1.1 V. A 10 kΩ to 1 MΩ
pull-up resistor from POK to OUT should be used to provide
a logic output and keep current consumption to a minimum.
Connect POK to GND or leave floating if not used. The POK
output is high impedance when the IC is in shutdown mode.
Fixed Output
The SiP1759 can be configured as a fixed 3.3 V output
regulator or as an adjustable output from 2.5 V to 5.5 V. In
the fixed 3.3 V output mode the feedback voltage is
generated from the internal resistor-divider network. The FB
pin must be tied to GND.
Soft-Start and Short Circuit Protection
The IC features a soft-start mechanism that limits the inrush
current during start-up and if the output is short circuited the
SiP1759 limits the output current to 110 mA.
Thermal Shutdown
The SiP 1759 is designed with a thermal shutdown circuit
that will shut down the IC when the die temperature exceeds
160 °C. The thermal shutdown has 20 °C of hysteresis,
insuring when the die cools down the IC will turn on again.
When VIN falls below 1 V the undervoltage lockout disables
the SiP1759.
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Document Number: 72949
S09-1453-Rev. D, 03-Aug-09
SiP1759
Vishay Siliconix
DESIGNS CONSIDERATIONS
Setting the Adjustable Output Voltage
The SiP1759 regulated output can be adjusted from 2.5 V to
5.5 V via resistor divider network from VOUT to GND (see
Typical Application Circuits). R1 and R2 should be kept in the
50 kΩ to 100 kΩ range for low power consumption, while
maintaining adequate noise immunity. The value R1 is
calculated using the following formula:
R1 = R2 {(VOUT/VFB) - 1}
VFB is nominally 1.235 V.
Capacitor Selection
Capacitor selection for CIN, COUT and CX will have an impact
in the voltage output ripple, output current and overall
physical size of the circuit.
Ceramic capacitors are recommenced for their low ESR
(≤ 20 mΩ) which will help keep the output voltage ripple at a
minimum. The initial values for the CIN and COUT capacitors
should be 10 µF, the CX capacitor should be 0.33 µF.
Output Voltage Ripple
The SiP1759 automatically decides whether to be in step up
mode or step down mode depending on the VIN, VOUT and
current load conditions, therefore the voltage output ripple
will vary. In step-up mode the voltage output ripple is higher
than step-down mode. But unless VIN is significant larger
than VOUT (VIN ≥ VOUT + 1 V) , in heavy load the IC will slip
from buck mode to boost mode as necessary to charge the
transfer capacitor and the ripple will increase. Reducing the
CX capacitor value will cause an increase in the switching
frequency and a reduction of the output ripple.
TYPICAL CHARACTERISTICS
120
1.00E-01
IOUT at 10 mA
1.00E-02
Efficiency (%)
IOUT at 50 mA
IOUT at 100 mA
80
60
40
1.00E-03
1.00E-04
1.00E-05
1.00E-06
20
0
1.5
Quiescent Current (A)
100
1.00E-07
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.5
1.5
Input Voltage (V)
5.5
0.20
4.0
(VOUT < VIN) RLOAD = 33 Ω
Output Ripple Voltage (V)
Output Voltage (V)
4.5
Quiescent Current vs. Input Voltage (No Load)
Efficiency vs. Input Voltage
3.5
2.5
3.5
Input Voltage (V)
3.0
2.5
2.0
1.5
0.16
100 mA
0.12
0.08
50 mA
1.0
0.04
0.5
10 mA
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Input Voltage (V)
Start-Up Input Voltage
Document Number: 72949
S09-1453-Rev. D, 03-Aug-09
4.5
5.0
5.5
0.00
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Output voltage Ripple vs. Input Voltage
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SiP1759
Vishay Siliconix
TYPICAL WAVEFORMS
VOUT
50 mV/div
VOUT
50 mV/div
VC+
5 V/div
VC+
5 V/div
VIN
50 mV/div
VIN
50 mV/div
5 µs/div
5 µs/div
VIN = 2.5 V
VOUT = 3.3 V
RLOAD = 33 Ω
VIN = 4.2 V
VOUT = 3.3 V
RLOAD = 33 Ω
Figure 1. Typical Switching Waveform (VOUT > VIN)
Figure 2. Typical Switching Waveforms (VOUT > VIN)
VOUT
50 mV/div
VOUT
50 mV/div
IOUT
100 mA/div
IOUT
100 mA/div
100 µs/div
100 µs/div
VIN = 4.2 V
VOUT = 3.3 V
IOUT Step: 10 mA - 100 mA
VIN = 2.5 V
VOUT = 3.3 V
IOUT Step: 10 mA - 100 mA
Figure 3. Load Transient Response (VOUT > VIN)
Figure 4. Load Transient Response (VOUT < VIN)
VOUT
1 V/div
VOUT
1 V/div
IIN
200 mA /div
VERROR
5 V /div
IIN
200 mA /div
VERROR
5 V /div
VSD
2 V/div
VSD
2 V/div
0.5 ms/div
VIN = 2.5 V
VOUT = 3.3 V
Figure 5. Turn On/Off Response (VIN = 2.5 V)
0.5 ms/div
VIN = 4.2 V
VOUT = 3.3 V
Figure 6. Turn On/Off Response (VIN = 4.2 V)
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72949.
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Document Number: 72949
S09-1453-Rev. D, 03-Aug-09
Package Information
Vishay Siliconix
MSOP:
10-LEADS (POWER IC ONLY)
JEDEC Part Number: MO-187, (Variation AA and BA)
(N/2) Tips)
2X
5
N N-1
A B C 0.20
0.60
0.48 Max
Detail “B”
(Scale: 30/1)
Dambar Protrusion
E
0.50
1 2
0.60
N/2
0.08 M C B S
b
Top View
A S
7
b1
e1
With Plating
e
A
See Detail “B”
c1
0.10 C
A1
-H-
D
6
Seating Plane
c
Section “C-C”
Scale: 100/1
(See Note 8)
Base Metal
-A-
3
See Detail “A”
Side View
0.25
BSC
Parting Line
C
0.07 R. Min
2 Places
A2
Seating Plane
L 4
T
0.95
C
ς
0.05 S
E1
-B-
-C-
3
End View
Detail “A”
(Scale: 30/1)
NOTES:
1.
2.
Dimensioning and tolerances per ANSI.Y14.5M-1994.
3.
Dimensions “D” and “E1” do not include mold flash or protrusions, and are
measured at Datum plane -H- , mold flash or protrusions shall not exceed
0.15 mm per side.
4.
Dimension is the length of terminal for soldering to a substrate.
5.
Terminal positions are shown for reference only.
6.
Formed leads shall be planar with respect to one another within 0.10 mm at
seating plane.
7.
N = 10L
Die thickness allowable is 0.203"0.0127.
The lead width dimension does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08 mm total in excess of the lead width
dimension at maximum material condition. Dambar cannot be located on the
lower radius or the lead foot. Minimum space between protrusions and an
adjacent lead to be 0.14 mm. See detail “B” and Section “C-C”.
8.
Section “C-C” to be determined at 0.10 mm to 0.25 mm from the lead tip.
9.
Controlling dimension: millimeters.
10. This part is compliant with JEDEC registration MO-187, variation AA and BA.
11. Datums -A- and -B- to be determined Datum plane -H- .
12. Exposed pad area in bottom side is the same as teh leadframe pad size.
Document Number: 72817
28-Jan-04
MILLIMETERS
Dim
A
A1
A2
b
b1
c
c1
D
E
E1
e
e1
L
N
T
Min
Nom
Max
Note
−
−
1.10
0.05
0.10
0.15
0.75
0.85
0.95
0.17
−
0.27
8
0.17
0.20
0.23
8
0.13
−
0.23
0.15
0.18
0.13
3.00 BSC
3
4.90 BSC
2.90
3.00
3.10
3
0.70
4
0.50 BSC
2.00 BSC
0.40
0.55
10
0_
4_
5
6_
ECN: S-40082—Rev. A, 02-Feb-04
DWG: 5922
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Document Number: 91000
Revision: 11-Mar-11
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