Preliminary Datasheet R2J20654NP R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 Integrated Driver - MOS FET (DrMOS) Description The R2J20654NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating the need for an external SBD for this purpose. Features Compliant with Intel 6 6 DrMOS Specification. Built-in power MOS FET suitable for Desktop, Server application. Low-side MOS FET with built-in SBD for lower loss and reduced ringing. Built-in driver circuit which matches the power MOS FET Built-in tri-state input function which can support a number of PWM controllers High-frequency operation (above 1 MHz) possible VIN operating-voltage range: 20 Vmax Large average output current (Max.40 A) Achieve low power dissipation Controllable driver: Remote on/off Zero current detection for a diode emulation operation Double thermal protection: Thermal Warning & Thermal Shutdown Built-in bootstrapping Switch Small package: QFN40 (6 mm 6 mm 0.95 mm) Terminal Pb-free/Halogen-free Outline Integrated Driver-MOS FET (DrMOS) QFN40 package 6 mm × 6 mm VCIN BOOT GH VIN 1 10 11 40 THWN Driver Pad High-side MOS Pad DISBL# VSWH MOS FET Driver ZCD_EN# Low-side MOS Pad PWM 31 CGND VDRV GL PGND 20 30 21 (Bottom view) R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 Page 1 of 15 R2J20654NP Preliminary Block Diagram Driver Chip VCIN THWN THWN VDRV BOOT GH Boot SW THDN VIN DISBL# High-side MOS FET 2 μA UVL CGND Level Shifter 20 k CGND VCIN 160 k Zero Current Det. ZCD_EN# VSWH Overlap Protection. & Logic Input Logic (TTL Level) (3 state in) PWM Low-side MOS FET VDRV VCIN 35 k PGND CGND GL Notes: 1. Truth table for the DISBL# pin DISBL# Input Driver Chip Status "L" "Open" "H" Shutdown (GL, GH = "L") Shutdown (GL, GH = "L") Enable (GL, GH = "Active") 3. Output signal from the UVL block UVL output Logic Level 4. Output signal from the THWN block For active "H" For shutdown "L" VCIN VL 2. Truth table for the ZCD_EN# pin ZCD_EN# Input GL Status "L" "Diode Emulation Mode" "Open" "Continuous Conduction Mode" "H" "Continuous Conduction Mode" VH "H" Thermal Warning Logic Level "L" Normal operating Thermal Warning TIC(°C) TwarnL TwarnH 5. Truth table for the THDN block Driver IC Temp. Driver Chip Status < 150°C Enable (GL, GH = "Active") > 150°C Shutdown (GL, GH = "L") (latch-off) R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 Page 2 of 15 R2J20654NP Preliminary VIN VIN VIN VSWH GH CGND BOOT VDRV VCIN ZCD_EN# Pin Arrangement 10 9 8 7 6 5 4 3 2 1 VIN 11 40 PWM VIN 12 39 DISBL# VIN 13 38 THWN VIN 14 37 CGND VSWH 15 36 GL PGND 16 35 VSWH PGND 17 34 VSWH PGND 18 33 VSWH PGND 19 32 VSWH PGND 20 31 VSWH VIN CGND VSWH VSWH PGND VSWH PGND PGND PGND PGND PGND PGND PGND 21 22 23 24 25 26 27 28 29 30 (Top view) Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name ZCD_EN# 1 Pin No. Description Zero current detection enable VCIN VDRV BOOT CGND GH VIN VSWH PGND GL THWN 2 3 4 5, 37, Pad 6 8 to 14, Pad 7, 15, 29 to 35, Pad 16 to 28 36 38 Control input voltage (+5 V input) Gate supply voltage (+5 V input) Bootstrap voltage pin Control signal ground High-side gate signal Input voltage Phase output/Switch output Power ground Low-side gate signal Thermal warning DISBL# 39 Signal disable PWM 40 PWM drive logic input R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 Remarks When asserted "L" signal, zero crossing detection is enabled Driver Vcc input 5 V gate drive To be supplied +5 V through internal switch Should be connected to PGND externally Pin for monitor Pin for monitor Thermal warning when over 115°C Disabled when DISBL# is "L". This Pin is pulled low when internal IC over the thermal shutdown level, 150°C. Capable of both 3.3 V and 5 V logic input Page 3 of 15 R2J20654NP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Power dissipation Average output current Input voltage Supply voltage & Drive voltage Switch node voltage BOOT voltage I/O voltage THWN/THDN current Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. 5. Symbol Pt(25) Pt(110) Iout VIN(DC) VIN(AC) VCIN & VDRV VSWH(DC) VSWH(AC) VBOOT(DC) VBOOT(AC) Rating 25 8 40 –0.3 to +20 30 –0.3 to +6 20 30 25 36 Units W Vpwm, Vdisbl, Vlsdbl, Vthwn Ithwn, Idisbl Tj-opr Tstg –0.3 to VCIN + 0.3 V 2, 5 0 to 1.0 –40 to +150 –55 to +150 mA °C °C 3 A V V V V Note 1 2 2, 4 2 2 2, 4 2 2, 4 Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. Rated voltages are relative to voltages on the CGND and PGND pins. For rated current, (+) indicates inflow. The specification values indicated "AC" is limited within 10 ns. VCIN + 0.3 V < 6 V Safe Operating Area 50 Average Output Current (A) 45 40 35 30 25 20 15 VIN = 12 V VCIN = VDRV = 5 V VOUT = 1.3 V fPWM = 1 MHz L = 0.45 μH 10 5 0 0 R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 25 50 75 100 PCB Temperature (°C) 125 150 175 Page 4 of 15 R2J20654NP Preliminary Recommended Operating Condition Item Input voltage Supply voltage & Drive voltage Symbol VIN VCIN & VDRV Rating 4.5 to 16 4.5 to 5.5 Units V V Note Electrical Characteristics (Ta = 25°C, VCIN = 5 V, VDRV = 5 V, VSWH = 0 V, unless otherwise specified) Supply PWM input DISBL# input ZCD_EN# Thermal warning Thermal shutdown Note: Item VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN operating current Symbol VH VL dUVL ICIN Min 4.1 3.6 — — Typ 4.3 3.8 0.5 62 Max 4.5 4.0 — — Units V V V mA VCIN disable current ICIN-DISBL — — 350 A PWM input high level VH-PWM 2.6 — — V PWM input low level PWM input resistance VL-PWM RIN-PWM — 6.5 — 12.5 0.8 25 V k 1.4 — 2.0 — — 0.2 2.0 — –52 100 — 0.2 — 130 — 150 — — 2.0 0.5 — — –25 115 15 0.5 — 150 2.0 — — 0.8 5.0 1.0 — 0.8 –12 130 — 1.0 1.0 — V ns V V A k V V A °C °C k A °C PWM input tri-state range VIN-tri Shutdown hold-off time Enable level Disable level Input current THDN on resistance ZCD disable level ZCD enable level Input current Warning temperature Temperature hysteresis THWN on resistance tHOLD-OFF * VENBL VDISBL IDISBL 1 RTHDN * Vzcddisbl Vzcden Izcden TTHWN *1 THYS *1 RTHWN *1 THWN leakage current Shutdown temperature ILEAK 1 Tstdn * 1 Test Conditions VH – VL fPWM = 1 MHz, Ton_pwm = 120 ns DISBL# = 0 V, PWM = LSDBL# = Open 3.3 V/5.0 V PWM interface PWM = 1 V 3.3 V/5.0 V PWM interface DISBL# = 1 V DISBL# = 0.2 V ZCD_EN# = 1 V Driver IC temperature THWN = 0.2 V THWN = 5 V Driver IC temperature 1. Reference values for design. Not 100% tested in production. R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 Page 5 of 15 R2J20654NP Preliminary Typical Application 4.5 to 16 V +5 V VCIN VDRV BOOT GH VIN THWN DISBL# R2J20654NP VSWH ZCD_EN# PGND PWM CGND VCIN GL VDRV BOOT GH THWN VIN DISBL# R2J20654NP VSWH ZCD_EN# PGND PWM CGND GL PWM1 PWM Control Circuit +1.3 V PWM2 PWM3 PWM4 VCIN VDRV BOOT GH THWN VIN DISBL# R2J20654NP VSWH Power GND Signal GND ZCD_EN# PGND PWM CGND VCIN GL VDRV BOOT GH THWN VIN DISBL# R2J20654NP VSWH ZCD_EN# PGND PWM CGND R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 GL Page 6 of 15 R2J20654NP Preliminary Pin Connection +5 V 1.0 μF 0 to 10 Ω 0.1 μF VIN (4.5 V to 16 V) CGND ZCD_enable Signal INPUT 8 7 6 5 4 3 2 1 GH CGND BOOT VDRV VCIN ZCD_EN# 9 VIN 10 VSWH CGND 10 μF × 4 11 VIN PAD 12 13 PGND CGND PAD 14 VIN PWM INPUT PWM 40 DISBL# 39 THWN 38 CGND 37 10 kΩ 15 VSWH +5 V GL 36 R2J20654NP 16 PGND VSWH 35 10 kΩ VSWH PAD 17 18 Signal GND 23 24 25 26 27 VSWH 31 PGND 32 20 22 Thermal Shutdown 33 19 21 Power GND +5 V 34 28 29 30 Thermal Warning 0.45 μH Vout PGND R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 PGND Page 7 of 15 R2J20654NP Preliminary Test Circuit Vinput A IIN V VIN Vcont A ICIN VCIN V VCIN BOOT DISBL# VIN R2J20654NP VDRV VSWH LSDBL# 5 V pulse PWM CGND Note: PIN = IIN × VIN + ICIN × VCIN POUT = IO × VO Efficiency = POUT / PIN PLOSS(DrMOS) = PIN – POUT Ta = 27°C R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 PGND GH Electric load IO GL Averaging Output Voltage Averaging V VO circuit Page 8 of 15 R2J20654NP Preliminary Typical Data Power Loss vs. Output Current Power Loss vs. Input Voltage 1.8 8 VCIN = VDRV = 5 V VIN = 12 V 1.7 VOUT = 1.3 V 1.6 fPWM = 600 kHz 7 VCIN = VDRV = 5 V Normalized Power Loss @ VIN = 12 V Power Loss (W) VOUT = 1.3 V f = 600 kHz 6 LPWM = 0.45 μH 5 4 3 2 L = 0.45 μH 1.5 IOUT = 25 A 1.4 1.3 1.2 1.1 1.0 0.9 1 0 0.8 0 5 10 15 20 25 30 35 0.7 40 4 6 8 Output Current (A) 12 14 16 Input Voltage (V) Power Loss vs. Switching Frequency Power Loss vs. Output Voltage 1.8 1.8 VIN = 12 V VIN = 12 V 1.7 VCIN = VDRV = 5 V 1.6 VOUT = 1.3 V L = 0.45 μH 1.5 IOUT = 25 A 1.4 1.3 1.2 1.1 1.0 Normalized Power Loss @ fPWM = 600 kHz 1.7 VCIN = VDRV = 5 V 1.6 fPWM = 600 kHz Normalized Power Loss @ VOUT = 1.3 V 10 L = 0.45 μH 1.5 IOUT = 25 A 1.4 1.3 1.2 1.1 1.0 0.9 0.9 0.8 0.8 0.7 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 0.7 250 Output Voltage (V) R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 500 750 1000 1250 Switching Frequency (kHz) Page 9 of 15 R2J20654NP Preliminary Typical Data (cont.) Power Loss vs. Output Inductance Power Loss vs. VCIN 1.8 1.8 VIN = 12 V VIN = 12 V 1.7 VOUT = 1.3 V 1.6 fPWM = 600 kHz fPWM = 600 kHz Normalized Power Loss @ VCIN = VDRV = 5 V Normalized Power Loss @ L = 0.45 μH 1.7 VCIN = VDRV = 5 V 1.6 VOUT = 1.3 V 1.5 IOUT = 25 A 1.4 1.3 1.2 1.1 1.0 L = 0.45 μH 1.5 IOUT = 25 A 1.4 1.3 1.2 1.1 1.0 0.9 0.9 0.8 0.8 0.7 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.7 4.5 5.0 5.5 6.0 VCIN = VDRV (V) Output Inductance (μH) Average ICIN vs. Switching Frequency 90 VIN = 12 V Average ICIN (mA) 80 VCIN = VDRV = 5 V 70 VOUT = 1.3 V L = 0.45 μH IOUT = 0 A 60 50 40 30 20 10 250 500 750 1000 1250 Switching Frequency (kHz) R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 Page 10 of 15 R2J20654NP Preliminary Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, lowside MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & DISBL# The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN is 4.3 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 3.8 V or less. The signal on pin DISBL# also enables or disables the circuit. Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor, etc., to pull the DISBL# line up to VCIN are both possible. VCIN L H H H DISBL# L H Open Driver State Disable (GL, GH = L) Disable (GL, GH = L) Active Disable (GL, GH = L) The pulled-down MOSFET, which is turned on when internal IC temperature becomes over thermal shutdown level, is connected to the DISBL# pin. The detailed function is described in THDN section. PWM & ZCD_EN# The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (VCIN + 0.3 V). When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. PWM L H GH L H GL H L The ZCD_EN# pin is the Zero Current Detection Operation Enable pin for "Diode Emulation Mode (DEM)" when ZCD_EN# is low. This function improves light load efficiency by preventing negative inductor current from output capacitor. Driver IC monitors inductor current and when inductor current crosses zero, driver IC turn off low-side MOS FET automatically. Figure 1.1 shows the Typical high side and low side gate switching and Inductor current (IL) during Continuous Conduction Mode (CCM), and Figure 1.2 shows DEM when asserting Zero Current Detection Enable signal. ZCD_EN# pin is internally pulled up to VCIN with 160 k resistor. When Zero Current Detection function is not used, keep this pin open or pulled up to VCIN. CCM Operation (ZCD_EN# = "H" or Open mode) IL 0A PWM GH GL Figure 1.1 Typical Signals during CCM R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 Page 11 of 15 R2J20654NP Preliminary DEM Operation (ZCD_EN# = "L" in Light load condition) IL 0A PWM GH GL Figure 1.2 Typical Signals during DEM The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tristate function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 150 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 2.6 V or more is required to make the circuit return to normal operation. 150 ns (tHOLD-OFF) 150 ns (tHOLD-OFF) 2.0 V PWM 1.4 V GH GL 150 ns (tHOLD-OFF) 150 ns (tHOLD-OFF) 2.0 V PWM 1.4 V GH GL Figure 2 PWM Shutdown-Hold Time Signal R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 Page 12 of 15 R2J20654NP Preliminary The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal operation; after the PWM input signal has stayed in the hysteresis window for 150 ns (typ.) and the tri-state detection signal has been driven high, the transistor M1 is turned off. When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is asserted high signal, M1 becomes ON and shifts to normal operation. VCIN M1 25 k PWM Pin Tri-state detection signal Input Logic To internal control 12.5 k Figure 3 Equivalent Circuit for the PWM-pin Input THWN & THDN This device has two level thermal detection, one is thermal warning and the other is thermal shutdown function. This Thermal Warning feature is the indication of the high temperature status. THWN is an open drain logic output signal and need to connect a pull-up resistor (ex.51 k) to THWN for Systems with the thermal warning implementation. When the chip temperature of the internal driver IC becomes over 115°C, Thermal warning function operates. This signal is only indication for the system controller and does not disable DrMOS operation. When thermal warning function is not used, keep this pin open. "H" THWN output Logic Level "L" Thermal warning Normal operating 100 115 TIC (°C) Figure 4 THWN Trigger Temperature R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 Page 13 of 15 R2J20654NP Preliminary THDN is an internal thermal shutdown signal when driver IC becomes over 150°C. This function makes High-Side MOS FET and Low-Side MOS FET turn off for the device protection from abnormal high temperature situation and at the same time DISBL# pin is pulled low internally to give notice to the system controller. Once thermal shutdown function operates, driver IC keeps DISBL# pin pulled low until VCIN becomes under UVL level (3.8 V). Figure 5 shows the example of two types of DISBL# connection with the system controller signal. Driver IC Temp. < 150°C > 150°C Driver Chip Status Enable (GL, GH = "Active") Shutdown (GL, GH = "L") 5V To Internal Logic 10 k DISBL# 2 μA To shutdown signal To Internal Logic 10 k DISBL# 2 μA Thermal Shutdown Detection Figure 5.1 THDN Signal to the System Controller ON/OFF signal Thermal Shutdown Detection Figure 5.2 ON/OFF Signal from the System Controller MOS FET The MOS FETs incorporated in R2J20654NP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the lowside MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 Page 14 of 15 R2J20654NP Preliminary Package Dimensions JEITA Package Code P-VQFN40-6x6-0.50 RENESAS Code PVQN0040KC-A Previous Code ⎯ MASS[Typ.] 0.10g NOTE) b1,c1: DIMENSION BEFORE PLATING HD 30pin 21pin 2.2 2.0 D 21pin 30pin 20pin 31pin 31pin E HE 2.0 0.2 0.7 2.2 40pin 11pin 40pin 3.1 10pin 1pin 0.2 0.2 ZD 2.2 ZE e 10pin 2.2 1pin c1 ×M S Lp A1 b1 A S b c S Outer lead detail y S Reference Dimension in Millimeters Symbol Min Nom Max D 6.00 E 6.00 A 0.95 A1 0.005 b 0.17 0.22 0.27 b1 0.20 e 0.50 Lp 0.40 0.50 0.60 x y 0.05 y1 t HD 6.20 HE 6.20 ZD 0.75 ZE 0.75 c 0.17 0.22 0.27 c1 0.20 Ordering Information Part Name R2J20654NP#G3 R07DS0246EJ0100 Rev.1.00 Jan 25, 2011 Quantity 2500 pcs Shipping Container Taping Reel Page 15 of 15 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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