PT6306 64-Bit High Voltage Display Driver IC DESCRIPTION FEATURES PT6306 is a 64-Bit High-Voltage Display Driver utilizing CMOS Technology specially designed for VFD display panels. It provides 64-bit bidirectional shift register, 64-bit latch and high-voltage CMOS Driver. The logic circuit operates on 5V power supply (CMOS Level Input) making it possible for PT6306 to be used in conjunction with a microcomputer. The driver block consists of 80V, 50mA (max.) high voltage output buffer. Pin assignments and application circuits are optimized for easy PCB Layout and cost saving benefits. • • • • APPLICATION • • • • • CMOS Technology Low Power Consumption 64-Bit Bidirectional shift registers Data Controlled via External Transfer Clock and Latch High Speed Data Transfer (fmax=25MHz, Min.: 16MHz in cascade connection) Wide Operating temperature Range: -40 to +85℃ High Voltage Output (80V, 50mA max.) Polarities of all Drivers may be inverted by using PCB Pin Available in COB and 100-pin, QFP • Micro Computer Peripheral BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6306 APPLICATION CIRCUIT Note: C=0.1μF, VEXT=External Supply Voltage (Maximum Value=70V) V2.1 2 January 2010 PT6306 ORDER INFORMATION Valid Part Number PT6306 PT6306-H Package Type 100 Pins, QFP COB Top Code PT6306/PT6306-Q - PIN CONFIGURATION 100-PIN, QFP V2.1 3 January 2010 PT6306 Pin Name VDD2 VSS2 HVO1 to HVO23 HVO24 to HVO41 HVO42 to HVO64 LDIO RDIO CLKB VSS1 I/O - Description Power Supply: 10 to 70V Ground O High Voltage Output Pins I/O I/O I - VDD1 LATB PCB BK I I I Left Data I/O Pin Right Data I/O Pin Clock Input Pin Ground Shift Directional Control Input Pin When this pin is set to “H” the Right Shift Mode is active: RDIOÆHVO1…..HVO64ÆLDIO When this pin is set to “L” the Left Shift Mode is active: LDIOÆHVO64…..HVO1ÆRDIO Power Supply: 5V +10% Latch Strobe Input Pin Reversed Polarity Pin Blank Input Pin NC - Not Connected DIR Pin No. 2, 31, 50, 79 5, 34, 47, 76 51 to 73 82 to 99, 8 to 30 36 37 38 39 41 42 43 44 45 1, 3, 4, 6, 7, 32, 33, 35, 40, 46, 48, 49, 74, 75, 77, 78, 80, 81, 100 Notes: 1. Use all the Power Supply Pins: VDD1, VDD2, VSS1, VSS2 (Make sure that VSS1 and VSS2 Pins have the same voltage level.) 2. Power must be supplied to VDD1, Logic Input and VDD2 so that the device may be protected from any harm caused by latch up. Power must be turned off in a reversed manner. Power ON. OFF sequences must be observed at all times, even during the transition period. V2.1 4 January 2010 PT6306 COB V2.1 5 January 2010 PT6306 Pin Name VDD2 VSS2 HVO1 to HVO23 HVO24 to HVO41 HVO42 to HVO64 LDIO RDIO CLKB VSS1 I/O - Description Power Supply: 10 to 70V Ground O High Voltage Output Pins I/O I/O I - Left Data I/O Pin Right Data I/O Pin Clock Input Pin Ground Shift Directional Control Input Pin When this pin is set to “H” the Right Shift Mode is active: RDIOÆHVO1…..HVO64ÆLDIO When this pin is set to “L” the Left Shift Mode is active: LDIOÆHVO64…..HVO1ÆRDIO Power Supply: 5V +10% Latch Strobe Input Pin Reversed Polarity Pin Blank Input Pin DIR VDD1 LATB PCB BK I I I Pin No. 1, 26, 38, 63 2, 27, 37, 62 39 to 61 64 to 81 3 to 25 28 29 30 31 32 33 34 35 36 Notes: 1. Use all the Power Supply Pins: VDD1, VDD2, VSS1, VSS2 (Make sure that VSS1 and VSS2 Pins have the same voltage level.) 2. Power must be supplied to VDD1, Logic Input and VDD2 so that the device may be protected from any harm caused by latch up. Power must be turned off in a reversed manner. Power ON. OFF sequences must be observed at all times, even during the transition period. V2.1 6 January 2010 PT6306 INPUT/OUTPUT PORT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below. INPUT PIN: CLKB INPUT PINS: DIR, LATB, PCB, BK INPUT/OUTPUT PINS: RDIO/LDIO OUTPUT PINS: HVO1 TO HVO64 V2.1 7 January 2010 PT6306 FUNCTION DESCRIPTION SHIFT REGISTER TRUTH TABLE Input DIR I/O CLKB RDIO H H Input H or L L L LDIO Output (see Note2) H or L Shift Register Output (see Note1) Right Shift Output Hold Input Output Left Shift Hold Notes: 1. SQ63 is shifted to the SQ64 position and the output from LDIO at the falling edge of the clock. 2. SQ2 is shifted to the SQ1 position and the output from RDIO at the falling edge of the clock. SHIFT REGISTER TRUTH TABLE RDIO (LDIO) x x H H L L x x Input LATB x x L L L L H H BK H H L L L L L L PCB H L H L H L H L Driver Output Stage H (All Driver Output are “High”) L (All Driver Output are “Low”) H L L H Output Data immediately before LATB goes to “High” Reverses & Outputs Data immediately before LATB goes to “High” Note: x=“High” or “Low” State, H=“High” State, L=“Low” State. V2.1 8 January 2010 PT6306 TIMING CHARACTERISTIC WAVEFORMS An example of function control timing waveforms are given in the diagram below. V2.1 9 January 2010 PT6306 ABSOLUTE MAXIMUM RATINGS (Unless otherwise specified, Ta=25℃, VSS1=VSS2=0V) Parameter Symbol Logic Power Supply Voltage VDD1 Logic Input Voltage V1 Logic Output Voltage VO1 Driver Power Supply Voltage VDD2 Driver Output Voltage VO2 Driver Output Current IO2 Power Dissipation PD Operating Temperature Topr Storage Temperature Tstg Rating -0.3 ~ +7 -0.3 ~ VDD1+0.3 -0.3 ~ VDD1+0.3 0.3 ~ +80 -0.3 ~ VDD2+0.3 +50 1000 -40 ~ +85 -65 ~ +150 Unit V V V V V mA mW ℃ ℃ RECOMMENDED OPERATING CONDITIONS (Unless otherwise specified, Topr=-40 to +85℃, VSS1=VSS2=0V) Parameter Symbol Min. Logic Power Supply Voltage VDD1 3.0 High Level Input Voltage VIH 0.8VDD1 Low Level Input Voltage VIL 0 Driver Power Supply Voltage VDD2 10 IOL2 Driver Output Current IOH2 - Typ. 5.0 - Max. 5.5 VDD1 0.2VDD1 70 +40 -40 Unit V V V V mA mA ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta=25℃, VDD1=3.3V/5.0V, VDD2=70V, VSS1=VSS2=0V) Parameter Symbol Conditions Min. Typ. High Level Output Voltage VOH1 Logic IOH1=-1.0mA 0.9VDD1 Low Level Output Voltage VOL1 Logic IOL1=1.0mA HVO1 to HVO64, 69 VOH21 IOH2=-1.0mA High Level Output Voltage HVO1 to HVO64, VOH22 65 IOH2=-10.0mA HVO1 to HVO64, VOL21 IOL2=5.0mA Low Level Output Voltage HVO1 to HVO64, VOL22 IOL2=40.0mA High Level Input Current IIH VI=VDD1 Low Level Input Current IIL VI=0V High Level Input Voltage VIH Logic 0.8VDD1 Low Level Input Voltage VIL Logic Logic, Ta=25℃ IDD11 Logic, Topr=-40 to +85℃ IDD12 State Current Dissipation Driver, Ta=25℃ IDD21 Driver, Topr=-40 to +85℃ IDD22 - V2.1 10 Max. 0.1VDD1 Unit V V - V - V 1.0 V 10 V 1.0 -1.0 0.2VDD1 10 100 100 1000 µA µA V V µA µA µA µA January 2010 PT6306 SWITCHING CHARACTERISTICS (Unless otherwise specified, Ta=25℃, VDD1=3.3V/5.0V, VDD2=70V, VSS1=VSS2=0V, Logic CL=15pF, Driver CL=50pF) Parameter Symbol Conditions Min. Typ. Max. Unit tPHL1 50 ns CLKB→RDIO/LDIO tPLH1 50 ns VDD1=3.3V 1000 CLKB→HVO1 to HVO64 tPHL2 ns VDD1=5.0V 160 CLKB→HVO1 to HVO64 VDD1=3.3V 700 CLKB→HVO1 to HVO64 tPLH2 ns VDD1=5.0V 160 CLKB→HVO1 to HVO64 VDD1=3.3V 1000 LATB→HVO1 to HVO64 tPHL3 ns VDD1=5.0V 150 LATB→HVO1 to HVO64 VDD1=3.3V 700 LATB→HVO1 to HVO64 tPLH3 ns VDD1=5.0V 150 Propagation Delay Time LATB→HVO1 to HVO64 VDD1=3.3V 1000 BK→HVO1 to HVO64 tPHL4 ns VDD1=5.0V 145 BK→HVO1 to HVO64 VDD1=3.3V 700 BK→HVO1 to HVO64 tPLH4 ns VDD1=5.0V 145 BK→HVO1 to HVO64 VDD1=3.3V 1000 PCB→HVO1 to HVO64 tPHL5 ns VDD1=5.0V 140 PCB→HVO1 to HVO64 VDD1=3.3V 700 PCB→HVO1 to HVO64 tPLH5 ns VDD1=5.0V 140 PCB→HVO1 to HVO64 VDD=5V 100 HVO1 to HVO64 Rise Time tTLH ns VDD=3.3V 200 HVO1 to HVO64 VDD=5V 100 HVO1 to HVO64 Fall Time tTHL ns VDD=3.3V 300 HVO1 to HVO64 Duty=50%, data loading 25 MHz Clock Frequency f In Cascade Connection 16 MHz Input Capacitance CI 20 pF V2.1 11 January 2010 PT6306 TIMING CHARACTERISTICS (Unless otherwise specified, Topr=-40 to +80℃, VDD1=3.3 to 5.0 V, VSS1=VSS2=0V) Parameter Symbol Conditions Min. Clock Pulse Width PWCLKB (L), (H) 20 Strobe Pulse Width PWLATB 20 Blank Pulse Width PWBK 200 PCB Pulse Width PWPCB 200 Data Setup Time tSETUP 10 Data Hold Time tHOLD 10 Clock-Strobe Time tCLKB-LATB 50 CLKB↓ → LATB↑ Typ. - Max. - Unit ns ns ns ns ns ns ns SWITCHING CHARACTERISTICS WAVEFORMS (Unless otherwise specified, VIH=VIL=0.5VDD1) V2.1 12 January 2010 PT6306 V2.1 13 January 2010 PT6306 PAD CONFIGURATION (unit: μm) . Die Size: . Driver Pad Size: . Driver Pad Pitch: . Logic Pad Size: V2.1 X=2654±5 Y=3240±5 (Extended Buffer) X=70 Y=70 90 70 x 70 14 January 2010 PT6306 PAD LOCATION Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 V2.1 Pad Name VDD2 VSS2 HVO42 HVO43 HVO44 HVO45 HVO46 HVO47 HVO48 HVO49 HVO50 HVO51 HVO52 HVO53 HVO54 HVO55 HVO56 HVO57 HVO58 HVO59 HVO60 HVO61 HVO62 HVO63 HVO64 VDD2 VSS2 LDIO RDIO CLKB VSS1 DIR VDD1 LATB PCB BK VSS2 VDD2 HVO1 HVO2 HVO3 HVO4 HVO5 HVO6 HVO7 HVO8 HVO9 HVO10 HVO11 HVO12 HVO13 HVO14 Location [1217, 1510] [853, 1510] [763, 1510] [673, 1510] [583, 1510] [493, 1510] [403, 1510] [313, 1510] [223, 1510] [133, 1510] [43, 1510] [-47, 1510] [-137, 1510] [-227, 1510] [-317, 1510] [-407, 1510] [-497, 1510] [-587, 1510] [-677, 1510] [-767, 1510] [-857, 1510] [-947, 1510] [-1037, 1510] [-1127, 1510] [-1217, 1510] [-1217, 1287.2] [-1217, 1197.2] [-1217, 1011.8] [-1217, 735.5] [-1217, 479.3] [-1217, 283.7] [-1217, 88.1] [-1217, -97.3] [-1217, -479.3] [-1217, -735.5] [-1217, -1011.8] [-1217, -1197.2] [-1217, -1287.2] [-1217, -1510] [-1127, -1510] [-1037, -1510] [-947, -1510] [-857, -1510] [-767, -1510] [-677, -1510] [-587, -1510] [-497, -1510] [-407, -1510] [-317, -1510] [-227, -1510] [-137, -1510] [-47, -1510] 15 January 2010 PT6306 Pad No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 V2.1 Pad Name HVO15 HVO16 HVO17 HVO18 HVO19 HVO20 HVO21 HVO22 HVO23 VSS2 VDD2 HVO24 HVO25 HVO26 HVO27 HVO28 HVO29 HVO30 HVO31 HVO32 HVO33 HVO34 HVO35 HVO36 HVO37 HVO38 HVO39 HVO40 HVO41 Location [43, -1510] [133, -1510] [223, -1510] [313, -1510] [403, -1510] [493, -1510] [583, -1510] [673, -1510] [763, -1510] [853, -1510] [1217, -1510] [1213.9, -940.1] [1213.9, -829.5] [1213.9, -718.9] [1213.9, -608.3] [1213.9, -497.7] [1213.9, -387.1] [1213.9, -276.5] [1213.9, -165.9] [1213.9, -55.3] [1213.9, 55.3] [1213.9, 165.9] [1213.9, 276.5] [1213.9, 387.1] [1213.9, 497.7] [1213.9, 608.3] [1213.9, 718.9] [1213.9, 829.5] [1213.9, 940.1] 16 January 2010 PT6306 PACKAGE INFORMATION 100-PIN, QFP (BODY SIZE: 14 X20 mm) Symbol A A1 A2 b c e D D1 E E1 L L1 θ Min. 0.00 2.55 0.22 0.13 Nom. 2.80 0.30 0.65BSC. 23.90BSC. 20.00BSC. 17.90BSC. 14.00BSC. 0.73 0.88 0.95REF. 0° - Max. 3.40 0.25 3.05 0.33 0.17 1.03 7° Notes: 1. Refer to JEDEC MO-112 CC-1 2. All dimensions are in millimeter. V2.1 17 January 2010 PT6306 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V2.1 18 January 2010