DG9232, DG9233 Vishay Siliconix Low-Voltage Dual SPST Analog Switch DESCRIPTION The DG9232, 9233 is a single-pole/single-throw monolithic CMOS analog device designed for high performance switching of analog signals. Combining low power, high speed (tON: 35 ns, tOFF: 20 ns), low on-resistance (RDS(on): 20 ) and small physical size, the DG9232, 9233 is ideal for portable and battery powered applications requiring high performance and efficient use of board space. The DG9232, 9233 is built on Vishay Siliconix’s low voltage BCD-15 process. Minimum ESD protection, per method 3015.7 is 2000 V. An epitaxial layer prevents latchup. Break-before -make is guaranteed for DG9232. 9233. Each switch conducts equally well in both directions when on, and blocks up to the power supply level when off. BENEFITS • • • • Reduced power consumption Simple logic interface High accuracy Reduce board space FEATURES • Low voltage operation (+ 2.7 V to + 5 V) Low on-resistance - RDS(on): 20 Fast switching - tON: 35 ns, tOFF: 20 ns Low leakage - ICOM(on): 200 pA max. Low charge injection - QINJ: 1 pC Low power consumption TTL/CMOS compatible ESD protection > 2000 V (method 3015.7) Available in MSOP-8 and SOIC-8 • Compliant to RoHS Directive 2002/95/EC • • • • • • • • APPLICATIONS • • • • • • • Battery operated systems Portable test equipment Sample and hold circuits Cellular phones Communication systems Military radio PBX, PABX guidance and control systems FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION NC1 1 8 V+ COM1 2 7 IN1 IN2 3 6 COM2 GND 4 5 NC2 TRUTH TABLE - DG9232 Logic 0 1 Logic "0" 0.8 V Logic "1" 2.4 V Top View NO1 1 8 V+ COM1 2 7 IN1 IN2 3 6 COM2 GND 4 5 NO2 Switch On Off TRUTH TABLE - DG9233 Logic 0 1 Logic "0" 0.8 V Logic "1" 2.4 V Top View Switch Off On ORDERING INFORMATION Temp Range Package SOIC-8 - 40 °C to 85 °C MSOP-8 Part Number DG9232DY DG9232DY-E3 DG9232DY-T1 DG9232DY-T1-E3 DG9233DY DG9233DY-E3 DG9233DY-T1 DG9233DY-T1-E3 DG9232DQ-T1-E3 DG9233DQ-T1-E3 * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 70837 S11-0984–Rev. F, 23-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG9232, DG9233 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Parameter Limit Reference V+ to GND Unit - 0.3 to + 13 IN, COM, NC, NOa V - 0.3 to (V+ + 0.3) Continuous Current (Any terminal) ± 20 Peak Current (Pulsed at 1 ms, 10 % duty cycle) ± 40 ESD (Method 3015.7) Storage Temperature D suffix Power Dissipation (Packages)b 8-pin narrow body SOICc mA > 2000 V - 65 to 125 °C 400 mW Notes: a. Signals on NC, NO, or COM or IN exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC board. c. Derate 6.5 mW/°C above 70 °C. SPECIFICATIONS (V+ = 3 V) Test Conditions Otherwise Unless Specified D Suffix - 40 °C to 85 °C V+ = 3 V, ± 10 %, VIN = 0.8 V or 2.4 Ve Temp.a Min.c Full 0 RDS(on) VNO or VNC = 1.5 V, V+ = 2.7 V ICOM = 5 mA RDS(on) Matchd RDS(on) RDS(on) Flatnessd NO or NC Off Leakage Currentg Typ.b Max.c Unit 3 V Room Full 30 50 80 VNO or VNC = 1.5 V Room 0.4 2 RDS(on) Flatness VNO or VNC = 1 and 2 V Room 4 8 INO/NC(off) VNO or VNC = 1 V/2 V, VCOM = 2 V/1 V COM Off Leakage Currentg ICOM(off) VCOM = 1 V/2 V, VNO or VNC = 2 V/1 V Channel-On Leakage Currentg ICOM(on) VCOM = VNO or VNC = 1 V/2 V Parameter Analog Switch Symbol Analog Signal Ranged VANALOG Drain-Source On-Resistance Digital Control Input Current Dynamic Characteristics IINL or IINH Turn-On Time tON Turn-Off Time tOFF VNO or VNC = 1.5 V Charge Injectiond Off-Isolation Crosstalk NC and NO Capacitance Channel-On Capacitance COM-Off Capacitance Power Supply Positive Supply Range Power Supply Current QINJ OIRR XTALK CS(off) CCOM(on) CCOM(off) V+ I+ CL = 1 nF, VGEN = 0 V, RGEN = 0 RL = 50 , CL = 5 pF, f = 1 MHz f = 1 MHz Room Full Room Full Room Full - 100 - 5000 - 100 - 5000 - 200 - 10000 5 10 Full 1 Room Full Room Full Room Room Room Room Room Room 50 20 1 - 74 - 90 7 20 13 2.7 V+ = 3.3 V, VIN = 0 or 3.3 V 5 100 5000 100 5000 200 10000 pA µA 120 200 50 120 5 ns pC dB pF 12 1 V µA Notes: a. Room = 25 °C, Full = as determined by the operating suffix. b. Typical values are for design aid only, not guaranteed nor subject to production testing. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet. d. Guarantee by design, nor subjected to production test. e. VIN = input voltage to perform proper function. f. Difference of min and max values. g. Guaranteed by 5 V leakage tests, not production tested. www.vishay.com 2 Document Number: 70837 S11-0984–Rev. F, 23-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG9232, DG9233 Vishay Siliconix SPECIFICATIONS (V+ = 5 V) Test Conditions Otherwise Unless Specified D Suffix - 40 °C to 85°C V+ = 5 V, ± 10 %, VIN = 0.8 V or 2.4 Ve Temp.a Min.c Full 0 RDS(on) VNO or VNC = 3.5 V, V+ = 4.5 V ICOM = 5 mA RDS(on) Matchd RDS(on) RDS(on) Flatnessd NO or NC Off Leakage Currentg Typ.b Max.c Unit 5 V Room Full 20 30 50 VNO or VNC = 3.5 V Room 0.4 2 RDS(on) Flatness VNO or VNC = 1, 2 and 3 V Room 2 6 INO/NC(off) VNO or VNC = 1 V/4 V, VCOM = 4 V/1 V COM Off Leakage Current ICOM(off) VCOM = 1 V/4 V, VNO or VNC = 4 V/1 V Channel-On Leakage Current ICOM(on) VCOM = VNO or VNC = 1 V/4 V Parameter Analog Switch Symbol Analog Signal Ranged VANALOG Drain-Source On-Resistance Room Full Room Full Room Full - 100 - 5000 - 100 - 5000 - 200 - 10000 10 10 100 5000 100 5000 200 10000 pA Digital Control Input Current IINL or IINH Full 1 Room Full Room Full 35 µA Dynamic Characteristics Turn-On Time tON Turn-Off Time tOFF VNO or VNC = 3.0 V Charge Injectiond Off-Isolation Crosstalk QINJ OIRR XTALK NC and NO Capacitance C(off) Channel-On Capacitance CD(on) COM-Off Capacitance CD(off) CL = 1 nF, VGEN = 0 V, RGEN = 0 RL = 50 , CL = 5 pF, f = 1 MHz f = 1 MHz 20 Room 2 Room - 74 Room - 90 Room 7 Room 20 Room 13 75 150 50 100 ns 5 pC dB pF Power Supply Positive Supply Range V+ Power Supply Current I+ 2.7 V+ = 5.5 V, VIN = 0 or 5.5 V 12 V 1 µA Notes: a. Room = 25 °C, Full = as determined by the operating suffix. b. Typical values are for design aid only, not guaranteed nor subject to production testing. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet. d. Guarantee by design, nor subjected to production test. e. VIN = input voltage to perform proper function. f. Difference of min and max values. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 70837 S11-0984–Rev. F, 23-May-11 www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG9232, DG9233 Vishay Siliconix TYPICAL CHARACTERISTICS TA = 25 °C, unless otherwise noted 2.0 3000 V+ = 3 V 1.5 2500 1.0 2000 I SUPPLY (A) Q INJ (pC) 0.5 0.0 - 0.5 1500 V+ = 5 V 1000 500 - 1.0 0 - 1.5 V+ = 3 V - 2.0 0.0 - 500 0.5 1.0 1.5 2.0 2.5 3.0 0 1 2 VCOM 5 Supply Current vs. VIN - 40 10 nA - 60 OFF-Isolation (dB) 1 nA I COM(off) (A) 4 VIN Charge Injection 100 pA ICOM(off) 10 pA ICOM(on) - 80 - 100 - 120 1 pA - 140 0.1 pA 25 45 65 85 105 0.001 M 125 0.01 M 0.1 M 1M Temperature (°C) Frequency (Hz) Leakage Current vs. Temperature Off-Isolation vs. Frequency 2.5 10 M 30 2.0 V+ = 5 V 27 1.5 1.0 0.0 ñ0.5 V+ = 3 V 24 ICOM 0.5 R DS(on) (W ) I OFF (pA) 3 INO/NC 21 18 ñ1.0 ñ1.5 V+ = 5 V 15 ñ2.0 ñ2.5 12 0 www.vishay.com 4 1 2 3 4 5 0 1 2 3 VCOM VCOM Off-Leakage vs. Voltage at 25 °C RDS vs. VCOM 4 5 Document Number: 70837 S11-0984–Rev. F, 23-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG9232, DG9233 Vishay Siliconix TYPICAL CHARACTERISTICS TA = 25 °C, unless otherwise noted 35 70 85 C tON 25 C 50 t ON / t OFF (ns) RDS(on) () 28 V+ = 3 V 60 40 C 21 14 40 30 tOFF 20 7 10 0 0.0 0.5 1.0 1.5 2.0 2.5 0 - 60 3.0 - 30 0 30 60 90 VCOM Temperature (°C) RDS vs. VCOM Switching Time vs. Temperature 120 2.25 120 2.00 100 1.75 V IN (sw) t (ns) 80 60 1.50 1.25 tON 40 1.00 tOFF 20 0 1.5 0.75 0.50 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2 3 4 5 6 V+ V+ tON/tOFF vs. Power Supply Voltage Input Switching Point vs. Power Supply Voltage Document Number: 70837 S11-0984–Rev. F, 23-May-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG9232, DG9233 Vishay Siliconix TEST CIRCUITS V+ Logic Input V+ NO or NC Switch +3V tr < 20 ns tf < 20 ns 50 % 0V Switch Output COM VOUT 0.9 x V OUT Input Switch Output IN Logic RL 300 W GND CL 35 pF 0V tON Input tOFF 0V Logic "1" = Switch On Logic input waveforms inverted for switches that have the opposite logic sense. CL (includes fixture and stray capacitance) V OUT = V COM RL R L + R ON Figure 1. Switching Time V+ Logic Input V+ V1 NO or NC COM1 NO or NC COM2 V2 tr < 5 ns tf < 5 ns 3V 0V RL 300 W CL 35 pF GND VNC = V NO VO Switch Output 90 % 0V tD tD CL (includes fixture and stray capacitance) Figure 2. Break-Before-Make Interval V+ Rgen V OUT V+ NC or NO COM VOUT VOUT + IN Vgen CL 3V IN On Off On GND Q = VOUT x CL IN depends on switch configuration: input polarity determined by sense of switch. Figure 3. Charge Injection www.vishay.com 6 Document Number: 70837 S11-0984–Rev. F, 23-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG9232, DG9233 Vishay Siliconix TEST CIRCUITS V+ 10 nF V+ COM IN COM 0 V, 2.4 V NC or NO V NC NO Off Isolation = 20 log RL V COM GND Analyzer Figure 4. Off-Isolation V+ 10 nF V+ COM Meter IN 0 V, 2.4 V NC or NO GND HP4192A Impedance Analyzer or Equivalent f = 1 MHz Figure 5. Channel Off/On Capacitance Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70837. Document Number: 70837 S11-0984–Rev. F, 23-May-11 www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix SOIC (NARROW): 8-LEAD JEDEC Part Number: MS-012 8 6 7 5 E 1 3 2 H 4 S h x 45 D C 0.25 mm (Gage Plane) A e B All Leads q A1 L 0.004" MILLIMETERS INCHES DIM Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.20 0.004 0.008 B 0.35 0.51 0.014 0.020 C 0.19 0.25 0.0075 0.010 D 4.80 5.00 0.189 0.196 E 3.80 4.00 0.150 e 0.101 mm 1.27 BSC 0.157 0.050 BSC H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.50 0.93 0.020 0.037 q 0° 8° 0° 8° S 0.44 0.64 0.018 0.026 ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498 Document Number: 71192 11-Sep-06 www.vishay.com 1 Package Information Vishay Siliconix MSOP: 8−LEADS JEDEC Part Number: MO-187, (Variation AA and BA) (N/2) Tips) 2X 5 A B C 0.20 N N-1 0.60 0.48 Max Detail “B” (Scale: 30/1) Dambar Protrusion E 1 2 0.50 N/2 0.60 0.08 M C B S b A S 7 Top View b1 e1 With Plating e A See Detail “B” c1 0.10 C -H- A1 D 6 Seating Plane c Section “C-C” Scale: 100/1 (See Note 8) Base Metal -A- 3 See Detail “A” Side View 0.25 BSC C Parting Line 0.07 R. Min 2 Places Seating Plane ς A2 0.05 S C E1 -B- L 4 T -C- 3 0.95 End View Detail “A” (Scale: 30/1) N = 8L NOTES: 1. Die thickness allowable is 0.203"0.0127. 2. Dimensioning and tolerances per ANSI.Y14.5M-1994. 3. Dimensions “D” and “E1” do not include mold flash or protrusions, and are measured at Datum plane -H- , mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimension is the length of terminal for soldering to a substrate. 5. Terminal positions are shown for reference only. 6. Formed leads shall be planar with respect to one another within 0.10 mm at seating plane. 7. The lead width dimension does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the lead width dimension at maximum material condition. Dambar cannot be located on the lower radius or the lead foot. Minimum space between protrusions and an adjacent lead to be 0.14 mm. See detail “B” and Section “C-C”. 8. Section “C-C” to be determined at 0.10 mm to 0.25 mm from the lead tip. 9. Controlling dimension: millimeters. 10. This part is compliant with JEDEC registration MO-187, variation AA and BA. 11. Datums -A- and -B- to be determined Datum plane -H- . MILLIMETERS Dim Min Nom Max A A1 A2 b b1 c c1 D E E1 e e1 L N T - - 1.10 0.05 0.10 0.15 0.75 0.85 0.95 0.25 - 0.38 8 0.25 0.30 0.33 8 0.13 - 0.23 0.15 0.18 0.13 3.00 BSC Note 3 4.90 BSC 2.90 3.00 3.10 3 0.70 4 0.65 BSC 1.95 BSC 0.40 0.55 8 0_ 4_ 5 6_ ECN: T-02080—Rev. C, 15-Jul-02 DWG: 5867 12. Exposed pad area in bottom side is the same as teh leadframe pad size. Document Number: 71244 12-Jul-02 www.vishay.com 1 VISHAY SILICONIX TrenchFET® Power MOSFETs Application Note 808 Mounting LITTLE FOOT®, SO-8 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/ppg?72286), for the basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. 0.288 7.3 0.050 1.27 0.196 5.0 0.027 0.69 0.078 1.98 0.2 5.07 Figure 1. Single MOSFET SO-8 Pad Pattern With Copper Spreading Document Number: 70740 Revision: 18-Jun-07 0.050 1.27 0.088 2.25 0.088 2.25 0.027 0.69 0.078 1.98 0.2 5.07 Figure 2. Dual MOSFET SO-8 Pad Pattern With Copper Spreading The minimum recommended pad patterns for the single-MOSFET SO-8 with copper spreading (Figure 1) and dual-MOSFET SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose. Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. www.vishay.com 1 APPLICATION NOTE In the case of the SO-8 package, the thermal connections are very simple. Pins 5, 6, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. 0.288 7.3 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SO-8 0.172 (4.369) 0.028 0.022 0.050 (0.559) (1.270) 0.152 (3.861) 0.047 (1.194) 0.246 (6.248) (0.711) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 22 Document Number: 72606 Revision: 21-Jan-08 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1