NCP5217A Single Synchronous Step-Down Controller The NCP5217A is a synchronous step−down controller for high performance systems battery−power systems. The NCP5217A includes a high efficiency PWM controller. A pin is provided to enable or disable forced PWM mode of operation. An internal power good voltage monitor tracks the SMPS output. NCP5217A also features soft−start sequence, UVLO for VCC and switcher, overvoltage protection, overcurrent protection, undervoltage protection and thermal shutdown. The IC is packaged in QFN14. http://onsemi.com MARKING DIAGRAM Features • • • • • • • • • • • • • • • • 0.8% accuracy 0.8 V Reference 4.5 V to 27 V Battery/Adaptor Voltage Range Adjustable Output Voltage Range: 0.8 V to 3.3 V Selectable Power Saving Mode / Force PWM Mode Lossless Inductor Current Sensing Programmable Transient−Response−Enhancement (TRE) Control Programmable Adaptive Voltage Positioning (AVP) Input Supply Feedforward Control Internal Soft−Start Integrated Output Discharge (Soft−Stop) Build−in Adaptive Gate Drivers PGOOD Indication Overvoltage, Undervoltage and Overcurrent Protections Thermal Shutdown QFN14 Package These Devices are Pb−Free and are RoHS Compliant N5217 ALYWG G QFN14 CASE 485AL A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) EN_SKIP BST 1 14 CS+ 2 13 DH CS−/Vo 3 12 SWN COMP 4 11 IDRP/OCP FB 5 10 VCC PGOOD 6 9 Typical Applications 7 • Notebook Application • System Power AGND DL/TRESET 8 PGND QFN14 (Top View) ORDERING INFORMATION Device Package Shipping† NCP5217AMNTXG QFN16 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2009 August, 2009 − Rev. 1 1 Publication Order Number: NCP5217A/D NCP5217A EN_SKIP Level Control 1 Thermal Shutdown IDRP/OCP Detection ENABLE FPWM SKIP 14 BST Over Current Detector CS+ CS−/Vo AVP Control 2 + CDIFF − Current Sense Amplifier 3 VREF+10% PGH + 13 DH NCP5217A 12 SWN − DISCH PGL + Control Logic, OSC Protection, COMP 4 + − FB − VREF−10% VREF VREF−20% + Error Amplifier − 5 Generator and PWM Logic IDRP/OCP UVLO Control VCC OVP + VREF+15% 11 RAMP UVP 10 VCC − OC & TRE Detection PGOOD 6 AGND 7 PGOOD 9 DL/TRESET 8 PGND Figure 1. Block Diagram +5V EN_SKIP QFN14 VIN 1 14 EN_SKIP PGOOD CS+ 3 CS−/Vo 4 COMP 5 FB 6 PGOOD BST DH 13 SWN 12 NCP5217A 2 VOUT IDRP/OCP 11 VCC 10 DL/TRESET AGND PGND 7 8 9 Figure 2. Typical Application Circuit http://onsemi.com 2 PGND NCP5217A PIN FUNCTION DESCRIPTION Pin No. Symbol Description 1 EN_SKIP This pin serves as two functions. Enable: Logic control for enabling the switcher. SKIP: Power saving mode (Skip and Force PWM) programmable pin. 2 CS+ 3 CS−/Vo Inductor current differential sense non−inverting input. Inductor current differential sense inverting input. 4 COMP Output of the error amplifier. 5 FB 6 PGOOD 7 AGND Analog ground. 8 PGND Ground reference and high−current return path for the bottom gate driver. 9 DL/TRESET 10 VCC Output voltage feed back. Power good indicator of the output voltage. High impendence (open drain) if power good (in regulation). Low impendence if power not good. Gate driver output of bottom N−channel MOSFET. It also has the function for TRESET. Supply for analog circuit and bottom gate driver. 11 IDRP/OCP Over current protection and Droop Voltage programmable pin. 12 SWN Switch node between the top MOSFET and bottom MOSFET. 13 DH Gate driver output of the top N−channel MOSFET. 14 BST Top gate driver input supply, a bootstrap capacitor connection between SWN and this pin. ABSOLUTE MAXIMUM RATINGS Rating VCC Power Supply Voltage to AGND Symbol Value Unit VCC −0.3, 6.0 V VBST−VSWN, VDH−VSWN, VCC−VPGND, VDL−VPGND, −0.3, 6.0 V VIO −0.3, 6.0 V VSWN −5 V (< 100 ns) 30 V V High−Side Gate Drive/Low−Side Gate Drive Outputs DH, DL −3(DC) V PGND VPGND −0.3, 0.3 V 48 °C/W High−side Gate Drive Supply: BST to SWN High−side Gate Drive Voltage: DH to SWN Low−side Gate Drive Supply: VCC to PGND Low−side Gate Drive Voltage: DL to PGND Input / Output Pins to AGND Switch Node SWN Thermal Characteristics Thermal Resistance Junction−to−Ambient (QFN14 Package) RqJA_QFN14 Operating Junction Temperature Range (Note 1) TJ −40 to + 150 °C Operating Ambient Temperature Range TA − 40 to + 85 °C Storage Temperature Range Tstg − 55 to +150 °C Moisture Sensitivity Level MSL 1 − Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. 1. Internally limited by thermal shutdown, 150°C min. http://onsemi.com 3 NCP5217A ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 5 V, TA = −40°C to 85°C, unless other noted) Characteristics Symbol Test Conditions Min Typ Max Unit SUPPLY VOLTAGE Input Voltage VIN 4.5 − 27 V VCC Operating Voltage VCC 4.5 5.0 5.5 V SUPPLY CURRENT VCC Quiescent Supply Current in FPWM operation IVCC_FPWM EN_SKIP = 2.0 V, VFB forced above regulation point. DH, DL are open 1.5 2.5 mA VCC Quiescent Supply Current in Power Saving Operation IVCC_PS EN_SKIP = 5 V, VFB forced above regulation point, DH, DL are open 1.5 2.5 mA VCC Shutdown Current IVCC_SD EN_SKIP = L, VCC = 5 V, true shutdown 1 uA BST Quiescent Supply Current in FPWM operation IBST_FPWM EN_SKIP = 1.5 V, VFB forced above regulation point, DH and DL are open, No boost trap diode 0.3 mA BST Quiescent Supply Current in power−saving operation IBST_PS EN_SKIP = 5 V, VFB forced above regulation point, DH and DL are open No boost trap diode 0.3 mA BST Shutdown Current IBST_SD EN_SKIP = 0 V 1 mA dV/dt on VCC dVCC/dt (Note 2) −10 10 V/ms Rising VCC Threshold VCCth+ Wake Up 4.05 4.25 4.48 V VCC UVLO Hysteresis VCCHYS 200 275 400 mV 105 110 115 % VOLTAGE−MONITOR Power Good High Threshold VPGH PGOOD in from higher Vo (PGOOD goes high) Power Good High Hysteresis VPGH_HYS PGOOD high hysteresis (PGOOD goes low) Power Good Low Threshold VPGL PGOOD in from lower Vo (PGOOD goes high) Power Good Low Hysteresis VPGL_HYS PGOOD low hysteresis (PGOOD goes low) 5 80 85 % 90 % −5 % Power Good High Delay Td_PGH 150 us Power Good Low Delay Td_PGL 1.5 us Output Overvoltage Rising Threshold OVPth+ With respect to Error Comparator Threshold of 0.8 V Overvoltage Fault Propagation Delay OVPTblk FB forced 2% above trip threshold UVPth With respect to Error Comparator Threshold of 0.8 V Output Undervoltage Trip Threshold Output Undervoltage Protection Blanking Time 110 115 120 1.5 % us 75 80 85 % UVPTblk − 8/fSW − s VREF 0.7936 0.8 0.8064 V FSW 270 300 330 kHz 1.92 2.21 ms 1.47 ms REFERENCE OUTPUT Internal Reference Voltage OSCILLATOR Operation Frequency OVERCURRENT THRESHOLD DETECTION Total Detection Time OCSET Detection Time TDETECT A short period before SS 1.26 T_OCDET (Note 2) 1.09 2. Guaranteed by design, not tested in production. http://onsemi.com 4 NCP5217A ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 5 V, TA = −40°C to 85°C, unless other noted) Characteristics Symbol Test Conditions Min Typ Max Unit 0.9 1.1 1.3 ms INTERNAL SOFT−START Soft−Start Time TSS VOLTAGE ERROR AMPLIFIER GAIN_VEA (Note 2) 88 dB Unity Gain Bandwidth BW_VEA (Note 2) 15 MHz Slew Rate SR_VEA COMP PIN TO GND = 100 pF (Note 2) 2.5 FB Bias Current Ibias_FB Output Voltage Swing Vmax_EA Isource_EA = 2 mA Vmin_EA Isink_EA = 2 mA DC Gain V/ms 0.1 3.3 V 3.5 0.15 mA 0.3 DIFFERENTIAL CURRENT SENSE AMPLIFIER CS+ and CS− Common−mode Input Signal Range VCSCOM_MAX Refer to AGND 3.5 V Input Bias Current CS_IIB −100 100 nA Input Signal Range CS_range −70 70 mV −1.0 1.0 mA 0.575 mA/mV Offset Current at IDRP [(CS+) − (CS−)] to IDRP Gain IDRP_offset IDRP_GAIN (IDRP/((CS+) − (CS−))) (CS+) − (CS−) = 0 V (CS+) − (CS−) = 10 mV, V(IDRP) = 0.8 V TA = 25°C 0.475 TA=−40°C to 85°C 0.425 BW_CS At −3dB to DC Gain (Note 2) Maximum IDRP Output Voltage IDRP_Max (CS+) − (CS−) = 70 mV, Isource drops to 95% of the value when V(IDRP) = 0.8 V Minimum IDRP Output Voltage IDRP_Min Current−Sense Bandwidth IDRP Output current 0.525 0.625 20 MHz 2.5 V 0 I_IDRP −1.0 V 35 mA 26.4 mA OVERCURRENT PROTECTION SETTING Overcurrent Threshold (OCTH) Detection Current I_OCSET Sourced from OCP before soft−start, Rocp = 16.7 kW is connected from OCP to AGND or FB 21.6 24 Ratio of OC Threshold over OCSET Voltage K_OCSET V((CS+) − (CS−)) / V_OCSET (Note 2) OCSET Voltage for Default Fixed OC Threshold VOCSET_DFT Rocp v 2 kW is connected from OCP to AGND or FB OCSET Voltage for Adjustable OC Threshold VOCSET_ADJ Rocp = 8.3 ~ 25 kW is connected from OCP to AGND or FB 200 OCSET Voltage for OC Disable VOCSET_DIS Rocp w 35 kW is connected from OCP to AGND or FB 720 Default Fixed OC Threshold V_OCTH_DFT (CS+) – (CS−), Pin IDRP/OCP is shorted to AGND or FB 35 40 45 mV Adjustable OC Threshold V_OCTH ((CS+) − (CS−)) (CS+) – (CS−), During OC threshold, set a voltage at pin OCP VOCSET = 200 mV 15 20 25 mV VOCSET = 600 mV 52 60 68 0.1 − 100 mV 600 mV mV GATE DRIVERS DH Pull−HIGH Resistance RH_DH 200 mA Source current 2.5 W DH Pull−LOW Resistance DL Pull−HIGH Resistance RL_DH 200 mA Sink current 1.5 W RH_DL 200 mA Source current 2 W DL Pull−LOW Resistance RL_DL 200 mA Sink current 0.75 W 2. Guaranteed by design, not tested in production. http://onsemi.com 5 NCP5217A ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 5 V, TA = −40°C to 85°C, unless other noted) Characteristics Symbol Test Conditions Min Typ Max Unit Isource_DH (Note 2) 1 A Isink_DH (Note 2) 1.7 A Isource_DL (Note 2) 1.3 A Isink_DL (Note 2) 3.3 A TD_LH DL−off to DH−on (Note 2) 20 ns TD_HL DH−off to DL−on (Note 2) 20 NCD_TH SWN−PGND, at EN_SKIP = 5 V −1 GATE DRIVERS DH Source Current DH Sink Current DL Source Current DL Sink Current Dead Time Negative Current Detection Threshold SWN source leakage mV ISWN_SD EN_SKIP = 0 V R_DH_SWN (Note 2) EN_SKIP Logic Input Voltage for Disable VEN_Disable Set as Disable 0.7 1.0 1.3 V Hysteresis 150 200 250 mV EN_SKIP Logic Input Voltage for FPWM VEN_FPWM Set as FCCM mode 1.7 1.95 2.25 V EN_SKIP Logic Input Voltage for Skip Mode VEN_SKIP Set as SKIP Mode 2.35 2.6 2.85 V Hysteresis 100 175 250 mV Internal Resistor from DH to SWN 1 100 uA kW CONTROL SECTION EN_SKIP Source Current IEN_SOURCE VEN_SKIP = 0 V 0.1 mA EN_SKIP Sink Current IEN_SINK VEN_SKIP = 5 V 0.1 mA PGOOD Pin ON Resistance PGOOD_R I_PGOOD = 5 mA PGOOD Pin OFF Current PGOOD_LK 100 W 1 mA 20 35 W 0.2 0.3 0.4 V 7.2 8 8.8 mA 600 700 mV OUTPUT DISCHARGE MODE Output Discharge On−Resistance Rdischarge Threshold for Discharge Off Vth_DisOff EN = 0 V TRE SETTING TRE Threshold Detection Current I_TRESET Source from DL in the short period before soft−start. (Rtre = 47 kW is connected from DL to GND Detection Voltage for TRE Threshold Selection VDL_TRE_1 (Default) Internal TRE_TH is set to 300 mV Rtre w 75 kW (Note 2) 500 VDL_TRE_2 Internal TRE_TH is set to 500 mV Rtre = 44 ~ 50 kW (Note 2) 300 450 VDL_TRE_3 TRE is Disabled Rtre v 25 kW (Note 2) 0 250 TRE Comparator Offset TRE_OS (Note 2) 10 mV Propagation Delay of TRE Comparator TD_PWM (Note 2) 20 ns Tsd (Note 2) 150 °C Tsdhys (Note 2) 25 °C THERMAL SHUTDOWN Thermal Shutdown Thermal Shutdown Hysteresis 2. Guaranteed by design, not tested in production. http://onsemi.com 6 NCP5217A TYPICAL OPERATING CHARACTERISTICS VCC PIN SHUTDOWN CURRENT (nA) 0.83 VFB Vref VOLTAGE (V) 0.82 0.81 0.8 0.79 0.78 −15 10 35 60 85 100 50 0 −50 −100 −40 −15 10 35 60 AMBIENT TEMPERATURE (°C) Figure 3. Vref Voltage vs Ambient Temperature Figure 4. VCC Shutdown Current vs Ambient Temperature 315 0.8 310 0.7 305 300 295 85 0.6 0.5 0.4 0.3 290 285 −40 −15 10 35 60 0.2 −40 85 −15 10 35 60 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) Figure 5. Switching Frequency vs Ambient Temperature Figure 6. IDRP Gain vs Ambient Temperature 85 43 30 20 10 0 −10 −20 −40 −15 10 35 60 85 DEFAULT FIX OC THRESHOLD (mV) 40 BST PIN SHUTDOWN CURRENT (nA) 150 AMBIENT TEMPERATURE (°C) IDRP_Gain (mA/mV) FSW SWITCHING FREQUENCY (kHz) 0.77 −40 200 42 41 40 39 38 37 −40 −15 10 35 60 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) Figure 7. BST Shutdown Current vs Ambient Temperature Figure 8. Default Fix OC Threshold vs Ambient Temperature http://onsemi.com 7 85 NCP5217A TYPICAL OPERATING CHARACTERISTICS Top to Bottom: EN, SWN, Vo, PGOOD Top to Bottom: EN, SWN, Vo, PGOOD Figure 9. Powerup Sequence Figure 10. Powerdown Sequence Top to Bottom: SWN_Slave, SWM, Vo Top to Bottom: EN, SWM, Vo Figure 11. On Line Mode Change (CCM " DCM) Figure 12. On Line Mode Change (DCM " CCM) Top to Bottom: SWN, Vo, Output Current Figure 13. Typical Transient http://onsemi.com 8 NCP5217A DETAILED OPERATING DESCRIPTION General further improve transient response in CCM, a transient response enhancement circuitry is implemented inside the NCP5217A. In CCM operation, the controller is continuously monitoring the COMP pin output voltage of the error amplifier to detect the load transient events. The functional block diagram of TRE is shown below. The NCP5217A synchronous step−down power controller contains a PWM controller for wide battery/adaptor voltage range applications The NCP5217A includes power good voltage monitor, soft−start, over current protection, under−voltage protection, overvoltage protection and thermal shutdown. The NCP5217A features power saving function which can increase the efficiency at light load. It is ideal for battery operated systems. The IC is packaged in QFN14. COMP + R Control Logic TRE + C The internal control logic is powered by VCC. The device is controlled by an EN_SKIP pin. The EN_SKIP serves two functions. When voltage of EN_SKIP is below VEN_Disable, it shuts down the device. When the voltage of EN_SKIP is between VEN_FPWM and VEN_SKIP, the device is operating as force PWM mode. When voltage level of EN_SKIP is above VEN_SKIP, the device is operating as power saving mode. When EN_SKIP is above VEN_Disable, the internal Vref is activated and power−on reset occurs which resets all the protection faults. Once Vref reaches its regulation voltage, an internal signal will wake up the supply under−voltage monitor which will assert a “GOOD” condition. In addition, the NCP5217A continuously monitors VCC level with an undervoltage lockout (UVLO) function. internal TRE_TH Figure 14. Block Diagram of TRE Circuit Once the large transient occurs, the COMP signal may be large enough to exceed the threshold and then TRE “flag” signal will be asserted in a short period which is typically around one normal switching cycle. In this short period, the controller will be running at high frequency and hence has faster response. After that the controller comes back to normal switching frequency operation. We can program the internal TRE threshold (TRE_TH). For detail please see the electrical table of “TRE Setting” section. Basically, the recommend internal TRE threshold value is around 1.5 times of peak−to−peak value of the COMP signal at CCM operation. The higher the internal TRE_TH, the lower sensitivity to load transient. The TRE function can be disable by setting the Rtre which is connecting to DL/TRE pin to less than 25 kW. For system component saving, it is usually set as default value, that is, Rtre is open (w75 kW) and internal TRE_TH is 300 mV typical. Forced PWM Operation (FPWM Mode) The device is operating as force PWM mode if EN_SKIP voltage keeps at between VEN_FPWM and VEN_SKIP. Under this mode, the low−side gate driver signal is forced to be the complement of the high−side gate driver signal. This mode allows reverse inductor current, in such a way that it provides more accurate voltage regulation and better (fast) transient response. During the soft−start operation, the NCP5217A automatically runs as FPWM mode regardless of the EN_SKIP setting at either FPWM or SKIP mode to make sure to have smooth power up. Pulse Skipping Operation (Skip Mode) The device is operating as skip mode if EN_SKIP voltage keeps above VEN_SKIP. However, in medium and high load range, the controller still runs in continuous−conduction−mode (CCM) of which it behaves exactly same as FPWM mode. In light load range, the controller will go to skip mode which is similar to conventional constant on−time scheme. Top to Bottom SWN, Vo, Transient Signal Figure 15. Transient Response with TRE Disable Transient Response Enhancement (TRE) For the conventional PWM controller in CCM, the fastest response time is one switching cycle in the worst case. To http://onsemi.com 9 NCP5217A The Figure 18 shows how to realize the AVP function. A current path is connecting to the FB pin via Rocp resistor. Rocp is not actually for AVP function, indeed, Rocp is used for OCP threshold value programming. The IDRP/OCP pin has dual functions: OCP programming and AVP. At the IDRP/OCP pin, conceptually there is a current source which is modulated by current sensing amplifier. The output voltage Vo with AVP is: V O + V O0 * I O * R LL (eq. 1) Where Io is the load current, no load output voltage Vo0 is set by the external divider that is ǒ V O0 + 1 ) Top to Bottom SWN, Vo, Transient Signal Figure 16. Transient Response with TRE Enable Rt Ǔ*V Rb (eq. 2) ref The load line impendence RLL is given by: R LL + DCR * Gain_CS * Rt * Adaptive Voltage Positioning (AVP) For applications with fast transient currents, adaptive voltage positioning can reduce peak−to−peak output voltage deviations due to load transients. With the use of AVP, the output voltage allows to have some controlled sag when load current is applied. Upon removal of the load, the output voltage returns no higher than the original level, just allowing one output transient peak to be cancelled over a load step up and release cycle. The amount of AVP is adjustable. The behaviors of the Vo waveforms with or without AVP are depicted at Figure 17. Rs2 Rs1 ) Rs2 (eq. 3) Where DCR is inductor DC resistance. Gain_CS is a gain from [(CS+) − (CS−)] to IDRP Gain (At electrical table, the symbol is IDRP_GAIN), the typical value is 0.525 mA/mV. The AVP function can be easily disable by shorting the Rocp resistor into ground. From the equation we can see that the value of “top” resistor Rt can affect the RLL, so it is recommended to define the amount of RLL FRIST before defining the compensation component value. And if the user wants to fine tune the compensation network for optimizing the transient performance, it is NOT recommend to adjust the value of Rt. Otherwise, both transient performance and AVP amount will be affected. The following diagram shows the typical waveform of AVP. Note that the Rt typical value should be above 1 kW. Vo With AVP Vo Without AVP Figure 17. Adaptive Voltage Positioning Vo Rt FB + COMP Rb Rocp + − Vref IDRP IDRP/OCP L Rs1 CS+ DCR Cs Rs2 CS− Top to Bottom: SWN, Vo, Transient Signal (0.5−10−0.5A) + Figure 19. Typical waveform of AVP Gi Figure 18. Configuration for AVP function http://onsemi.com 10 NCP5217A Overcurrent Protection (OCP) It should be noted that there are two configurations for Rocp resistor. If Adaptor Voltage Position (AVP) is used, the Rocp should be connected to FB pin. If AVP is not used, the Rocp should be connected to ground. At the IDRP/OCP pin, there is a constant current(24 mA typ.) flowing out during the programming stage at system start up. This is used to sense the voltage level which is developed by a resistor Rocp so as to program the overcurrent detection threshold voltage. For typical application, the Vocth is set as default value (40 mV typ) by setting Rocp = 0 W, or directly short the IDRP/OCP pin to ground. It has the benefit of saving one component at application board. For other programming values of Vocth, please refer to the electrical table of “Overcurrent Protection Setting” section. The NCP5217A protects power system if over current event occurs. The current is continuously monitored by the differential current sensing circuit. The current limit threshold voltage VOCSET can be programmed by resistor Rocset connecting at the IDRP/OCP pin. However, fixed default VOCSET can be achieved if Rocset is less than 2 kW. If the inductor current exceeds the current threshold continuously, the top gate driver will be turned off cycle by cycle. If it happens over consecutive 16 clock cycles time (16 x 1/fSW), the device is latched off such that top and bottom gate drivers are off. EN resets or power recycle the device can exit the fault. The following diagram shows the typical behavior of OCP. Guidelines for selecting OCP Trip Component 1. Choose the value of Rocp for Vocth selection. (typical is 0 W for Vocth = 40 mV typical) 2. Define the DC value of OCP trip point (IOCP_DC) that you want. The typical value is 1.5 to 1.8 times of maximum loading current. For example, if maximum loading is 10 A, then set OCP trip point at 15 A to 18 A. 3. Calculate the inductor peak current (Ipk)which is estimated by the equation: I pk + I OCP_DC ) Figure 20. Overcurrent Protection The NCP5217A uses lossless inductor current sensing for acquiring current information. In addition, the threshold OCP voltage can be programmed to some desired value by setting the programming resistor Rocp. Rt FB + IDRP/OCP Rs1 L DCR Cs k+ + − Vref Rs1 + Rs2 Rt + CS− FB + IDRP Rs1 DCR Cs CS+ Rs2 CS− + (eq. 6) k * Rs1 1*k (eq. 7) V OCth DCR (eq. 8) Overvoltage Protection (OVP) IDRP/OCP L L k * DCR * Cs I pk + COMP + − Vref (eq. 5) 8. Hence, all the current sense components Rs1, Rs2, Cs have been found for target IOCP_DC. 9. If Rs2 is not used (open), set k = 1, at that moment, the Ipk will be restricted by: Gi Rb Rocp I pk * DCR Rs2 + Without AVP Vo V OCth 7. Calculate Rs2 value by the equation: IDRP Rocp CS+ (eq. 4) 5. Select Cs value between 100 nF to 200 nF. Typically, 100 nF will be used. 6. Calculate Rs1 value by the equation: COMP Rb 2 * V IN * f SW * L O 4. Check with inductor datasheet to find out the value of inductor DC resistance DCR, then calculate the RS1, RS2 dividing factor k based on the equation: Top to Bottom : SWN, Vo, PGOOD, Io Vo V O * (V IN * V O) When VFB voltage is above 115% (typical) of the nominal VFB voltage for over 1.5 ms blanking time, an OV fault is set. At that moment, the top gate drive is turned off and the bottom gate drive is turned on until the VFB below lower under voltage (UV) threshold and bottom gate drive is Gi With AVP Figure 21. OCP Configurations http://onsemi.com 11 NCP5217A turned on again whenever VFB goes above upper UV threshold. EN resets or power recycle the device can exit the fault. The following diagram shows the typical waveform when OVP event occurs. consecutive 8 clock cycles, an UV fault is set and the device is latched off such that both top and bottom gate drives are off. EN resets or power recycle the device can exit the fault. Top to Bottom : SWN, DL, Vo, PGOOD Figure 23. Undervoltage Protection Top to Bottom : SWN, Vo, PGOOD Figure 22. Overvoltage Protection Thermal Shutdown The IC will shutdown if the die temperature exceeds 150°C. The IC restarts operation only after the junction temperature drops below 125°C. Undervoltage Protection (UVP) An UVP circuit monitors the VFB voltage to detect under voltage event. The undervoltage limit is 80% of the nominal VFB voltage. If the VFB voltage is below this threshold over +5V V5 PGND R1 R11 1 R2 OFF = Skip Mode 1−2 = FCCM Mode EN_SKIP 3−2 = Disable LED1 R4 R5 LED2 EN_SKIP 2 CS+ R6 C3 PGOOD M5 4 COMP 5 FB 6 PGOOD C4 R7 BST DH 13 3 CS−/Vo C2 AGND 7 R9 R8 VIN R10 14 VIN_GND M2 C14 L1 J2 R15 1 2 3 1−2 = OCP Only 3−2 = OCP + AVP VCC 10 PGND 8 M1 R14 IDRP/OCP 11 DL/TRESET 9 R13 C20 SWN 12 NCP5217A R3 C1 J100 Default = Open C7 C8 C9 C11 U1 3 SW1 J100 COMP D1 R12 2 1 +5V J1 Default = Close J1 C5 R19 M4 C10 R20 C15 C17 C18 D3 VOUT PGND BNC1 C6 R17 R18 M3 R16 PGND R21 AGND AGND PGND Figure 24. Demo Board Schematic http://onsemi.com 12 D2 NCP5217A DEMO BOARD BILL OF MATERIAL BOM (See next tables for compensation network and power stage) Designator Qty Description Value Footprint Manufacturer Manufacturer P/N U1 1 R1 1 Single Synchronous Stepdown Controller − QFN14 (Special) ON Semiconductor NCP5217MNR2G Chip Resistor, $5% 75k 0603 Panasonic R2 ERJ3GEYJ753V 1 Chip Resistor, $5% 10k 0603 Panasonic ERJ3GEYJ103V R3, R4 2 Chip Resistor, $5% 1k 0603 Panasonic ERJ3GEYJ102V R5 1 Chip Resistor, $5% 100k 0603 Panasonic ERJ3GEYJ104V R10 1 Chip Resistor, $5% 5.6 0603 Panasonic ERJ3GEYJ5R6V R11 1 Chip Resistor, $5% 20k 0603 Panasonic ERJ3GEYJ203V R12 1 Chip Resistor, $5% 5.6 0603 Panasonic ERJ3GEYJ5R6V R13, R14, R15, R17 4 Chip Resistor, $5% 0 0603 Panasonic ERJ3GEYJR00V R16, R18, R21, 3 − DNP − − − C1 1 MLCC Chip Capacitor, $10% Temp Char: X7R, Rate V = 50 V 100 nF 0603 Panasonic ECJ1VB1E104K C5, C6 2 MLCC Chip Capacitor, $20% Temp Char: X5R, Rate V=25V 1 mF 0805 Panasonic ECJ2FB1E105M C7,C8,C9, C11 4 MLCC Chip Capacitor, $20% Temp Char: X5R, Rate V = 25 V 4.7 mF 0805 Panasonic ECJ2FB1E475M C10, C13, C17, C18 4 − DNP − − − C20 1 MLCC Chip Capacitor, $20% Temp Char: X7R, Rate V = 50 V 0.1 mF 0603 Panasonic ECJ1VB1E104M D1 1 30V Schottky Diode Vf=0.35V @ 10mA − SOT−23 ON Semiconductor BAT54LT1 D2, D3 1 − DNP − − − M5 1 Power MOSFET 50 V, 200 mA Single N−Channel − SOT−23 ON Semiconductor BSS138L LED1 1 Surface Mount LED (Green) − 0805 LUMEX SML−LX0805GC−TR LED2 1 Surface Mount LED (Red) − 0805 LUMEX SML−LX0805IC−TR J1, J100, COMP, EN_SKIP, PGOOD, AGND 6 Pin Header Single Row − Pitch=2.54 mm Betamax 2211S−40G−F1 V5, VIN, VIN_GND, PGND, PGND, PGND, VOUT 7 Terminal Pin − f = 1.74 mm HARWIN H2121−01 BNC1 1 SMB SMT Straight Socket − 5.1 x 5.1 mm Tyco Electronics RS Stock# 420−5401 SW1 1 2P ON−OFF−ON toggle switch − 3 pins, 2.54 mm pitch C&K RS Stock# 249−2984 Manufacturer # 7203SYCQE http://onsemi.com 13 NCP5217A DEMO BOARD BILL OF MATERIAL (Vo = 1.1 V, Io = 15 A) Item Compensation Network Power Stage & Current Sense Component Value Tol Footprint Manufacturer Manufacturer P/N R6 100k 1% 0603 Panasonic ERJ3EKF1003V R7 560 1% 0603 Panasonic ERJ3EKF5600V R8 3k 1% 0603 Panasonic ERJ3EKF3001V R9 8k 1% 0603 Panasonic ERJ3EKF8001V C2 470 pF 10% 0603 Panasonic ECJ1VC1H471K C3 15 pF 10% 0603 Panasonic ECJ1VC1H150K C4 1.2 nF 10% 0603 Panasonic ECJ1VB1H122K M1, M2 − − SOIC8−FL ON Semiconductor NTMFS4821N M3, M4 − − SOIC8−FL ON Semiconductor NTMFS4847N L1 1 mH 20% 10x11.5mm Cyntec PCMC104T−1R0MN R19 6.2k 1% 0603 Panasonic ERJ3EKF6201V R20 9.1k 1% 0603 Panasonic ERJ3EKF9101V C14, C15 330 mF 6 mW 20% 7343 Panasonic EEFSX0D331XR Sanyo 2TPLF330M6 DEMO BOARD BILL OF MATERIAL (Vo = 1.5 V, Io = 8 A) Item Compensation Network Power Stage & Current Sense Component Value Tol Footprint Manufacturer Manufacturer P/N R6 82k 1% 0603 Panasonic ERJ3EKF8202V R7 1k 1% 0603 Panasonic ERJ3EKF1001V R8 5k 1% 0603 Panasonic ERJ3EKF5001V R9 5.71k 1% 0603 Panasonic ERJ3EKF5711V C2 270 pF 10% 0603 Panasonic ECJ1VC1H271K C3 15 pF 10% 0603 Panasonic ECJ1VC1H150K C4 560 pF 10% 0603 Panasonic ECJ1VB1H561K M1, M3 − − SO8 ON Semiconductor NTMS4705N M2, M4 DNP − L1 Power Stage & Current Sense − − − 10x11.5mm Cyntec PCMC104T−1R0MN 13x14x4.9mm WE 744315120 ERJ3EKF4301V 1 mH 20% R19 4.3k 1% 0603 Panasonic R20 DNP − − − − C14, C15 220 mF 12 mW 20% 7343 Panasonic EEFUD0D221XR Sanyo 2R5TPL220MC http://onsemi.com 14 NCP5217A DEMO BOARD BILL OF MATERIAL (Vo = 1.8 V, Io = 8 A) Item Compensation Network Power Stage & Current Sense Component Value Tol Footprint Manufacturer Manufacturer P/N R6 150k 1% 0603 Panasonic ERJ3EKF1503V R7 1k 1% 0603 Panasonic ERJ3EKF1001V R8 5k 1% 0603 Panasonic ERJ3EKF5001V R9 4K 1% 0603 Panasonic ERJ3EKF4001V C2 220pF 10% 0603 Panasonic ECJ1VC1H221K C3 18pF 10% 0603 Panasonic ECJ1VC1H180K C4 560pF 10% 0603 Panasonic ECJ1VB1H561K M1, M3 − − SO8 ON Semi NTMS4705N M2, M4 DNP − − − − L1 1.2uH 20% 10x11.5mm TOKO FDA1254−1R2M=P3 R19 4.3K 1% 0603 Panasonic ERJ3EKF4301V R20 DNP − − − − C14, C15 220uF 20% 7343 Panasonic EEFUD0D221XR Sanyo 2R5TPL220MC 12mW http://onsemi.com 15 NCP5217A PACKAGE DIMENSIONS QFN14 3.5x3.5, 0.5P CASE 485AL−01 ISSUE O D ÇÇÇ ÇÇÇ ÇÇÇ PIN 1 LOCATION 2X 2X L DETAIL A DETAIL A OPTIONAL PIN CONSTRUCTION E EXPOSED Cu TOP VIEW (A3) 0.10 C L L1 0.15 C 0.15 C OPTIONAL PIN CONSTRUCTION ÉÉÉ ÉÉÉ MOLD CMPD DETAIL B 0.08 C A1 SIDE VIEW SOLDERING FOOTPRINT* SEATING PLANE 2X 14X 14X K 0.36 9 L 2X E2 e MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.50 BSC 1.90 2.15 3.50 BSC 1.90 2.15 0.50 BSC 1.50 BSC 0.20 −−− 0.30 0.50 0.00 0.03 3.80 14X 0.63 7 14X C D2 DETAIL A DIM A A1 A3 b D D2 E E2 e e2 K L L1 OPTIONAL PIN CONSTRUCTION A NOTE 4 DETAIL B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. EDGE OF PACKAGE A B 2.12 0.50 PITCH 2 1 14 14X b e2 1.50 PITCH DIMENSIONS: MILLIMETERS 0.10 C A B BOTTOM VIEW 0.05 C NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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