CCD Delay Line Series MN38664S NTSC-Compatible CCD Video Signal Delay Element Overview The MN38664S is a CCD signal delay element for video signal processing applications. It contains such components as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 679, 680.5, and 605 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits. When the switch input is "L" level, the MN38664S samples the input using the supplied clock signal with a frequency three times the NTSC color signal subcarrier frequency (3.579545 MHz) and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. When the switch input is "H" level, the MN38664S disables the threefold-frequency circuit and samples the input with the image sensor drive frequency (9.545454 MHz) for the camera's 510 horizontal pixels and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Pin Assignment XIC 1 20 XIV VSS3 2 19 PCOUT & VCOIN VDD3 3 18 –VBB VINC1 4 17 VSS2 N.C. 5 16 VDD2 VINVC 6 15 VINVY VGC1 7 14 SW VO1C 8 13 VINC2 VDD1 9 12 VGC2 VSS1 10 11 VO2Y ( TOP VIEW ) SOP020-P-0300 Features Single 4.4-V power supply Choice of camera and VCR modes, so that both the camera and VCR portions of a video camera with 510 horizontal pixels can use the same MN38664S for signal processing Applications Video cameras 1 MN38664S CCD Delay Line Series L 6 H 4 Charge input block L VGC2 7 Mode switch 78.5-stage analog shift register 12 VGC1 SW VSS3 2 14 VDD3 Charge input block H VINC1 3 Clamp circuit Bias circuit VINVC 17 V SS2 16 V DD2 9 10 VSS1 VDD1 Block Diagram Booster circuit Voltage generator Voltage generator L H 602-stage analog shift register 3-stage analog shift register Charge detector Resampling output amplifier 8 VO1C L H VINVY L 15 Charge input block H VINC2 H 13 Charge input block L XIV 20 L L 77-stage analog shift register H 3-stage analog shift register L 602-stage analog shift register Charge detector H Resampling output amplifier øS driver H H 1/3rd frequency divider L Waveform adjustment block ø1 driver øR driver øSH driver VCO H Phase comparator Timing adjustment ø2 driver Substrate bias generator 18 19 L H PCOUT & VCOIN 2 L –VBB XIC 1 Waveform amplifier adjustment block 11 VO2Y CCD Delay Line Series MN38664S Package Dimensions (Unit:mm) SOP020-P-0300 12.60±0.20 20 11 +0.10 0.15 -0.05 7.70±0.30 5.50±0.20 1.10±0.20 0 to 10° 0.30min. 1.27 0.40±0.10 SEATING PLANE 0.10±0.10 (0.6) 1.90max. 10 1.50±0.20 1 3