19-1855 Rev 0; 11/00 +3.3V, 2.5Gbps Quad Transimpedance Amplifier for System Interconnects Features ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Single +3.3V Supply 93mW per Channel Power Dissipation 460nARMS Input-Referred Noise 20ps Deterministic Jitter 2.4GHz Small-Signal Bandwidth No External Compensation 40dB Power-Supply Rejection Ratio Compact Die with 250µm Channel Pitch 100Ω Differential Output Impedance Ordering Information PART TEMP. RANGE MAX3825U/D 0°C to +85°C PIN-PACKAGE Dice* *Dice are designed to operate with a 0°C to +120°C junction temperature, but are tested and guaranteed only at TA = +25°C. Applications System Interconnects SDH/SONET Backplanes Dense Digital CrossConnects Typical Operating Circuit appears at end of data sheet. ATM Switching Networks High-Speed Parallel Optical Links Chip Topography/Pad Configuration VCCO1 OUT1+ OUT1- VCCO1 VCCO2 OUT2+ OUT2- VCCO2 VCCO3 OUT3+ OUT3- VCCO3 VCCO4 OUT4+ OUT4-VCCO4 N.C. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GNDO1 37 20 GNDO4 GNDO2 38 19 GNDO3 GNDF 39 18 ENABLE GNDI2 40 17 GNDI3 VCCI2 41 16 VCCI3 VCCI1 42 15 VCCI4 GNDI1 43 14 GNDI4 VCCFILT 44 1 N.C. 2 3 N.C. FILTER 4 IN1 5 6 7 8 9 10 11 FILT1 IN2 FILT2 IN3 FILT3 IN4 FILT4 12 13 N.C. N.C. ________________________________________________________________ Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX3825 General Description The MAX3825 is a quad transimpedance amplifier (TIA) intended for 2.5Gbps system interconnect applications. Each of the four channels converts a small photodiode current to a measurable differential voltage with a transimpedance gain of 3.7kΩ. The circuit features 460nARMS of input-referred noise per channel corresponding to an optical input sensitivity of -22.3dBm (BER ≤ 1 × 10-14). The quad transimpedance amplifier has 20ps of deterministic jitter and a 2.4GHz small-signal bandwidth. The MAX3825 is optimized for use with a quad PIN photodetector array with a standard fiber pitch of 250µm. The MAX3825 operates from a single +3.3V supply over a 0°C to +85°C temperature range. With a +3.3V supply, each channel dissipates 93mW of power. A DC cancellation circuit on each channel provides a true differential output swing over a wide range of input currents. Each channel has an independent supply and ground to allow all or any combination of channels to be connected. This device is available in dice only. MAX3825 +3.3V, 2.5Gbps Quad Transimpedance Amplifier for System Interconnects ABSOLUTE MAXIMUM RATINGS Output Voltage OUT1±, OUT2±, OUT3±, OUT4±............................(VCC - 1.5V) to (VCC + 0.5V) ENABLE Voltage.........................................-0.5V to (VCC + 0.5V) Operating Temperature Range (TA)........................0°C to +85°C Storage Temperature Range .............................-55°C to +150°C Operating Junction Temperature (TJ)................-55°C to +150°C Processing Temperature..................................................+400°C Supply Voltage VCCO1, VCCO2, VCCO3, VCCO4, VCCI1, VCCI2, VCCI3, VCCI4, VCCFILT ...............-0.5V to +6.0V Input Current: IN1, IN2, IN3, IN4...........................-4mA to +4mA FILTER Current..................................................-24mA to +24mA Filter Current: FILT1, FILT2, FILT3, FILT4 .............-6mA to +6mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.14V to +3.6V, TA = 0°C to +85°C. Typical values are at +3.3V, TA = +25°C, unless otherwise noted.) MIN TYP PARAMETER SYMBOL CONDITIONS MAX Single channel 28 40 Dual channel 56 80 Quad channel 112 0.89 160 0.99 Supply Current ICC Input Bias Voltage IIN = 0 DC Input Overload Transimpedance Filter Resistor RFILTER Filter Resistors RFILT1–4 Single-Ended Output Impedance 1.7 Z21 10µAp-p, 100 Ω differential load 3.0 RFILT_ 720 RO (Note 1) 50 Maximum Differential Output Range IIN = 2mAp-p 230 IIN = 10µAp-p -5 Output Offset Voltage 3.7 180 Transimpedance Linear Range Voffset Output Common Mode Voltage 50 4.5 V kΩ Ω Ω 57 Ω µAp-p 340 480 mVp-p +5 mV VCC - 0.09 50Ω loads to VCC mA mA RFILTER 43 UNITS V Note 1: Gain at 50µAp-p is within 10% of the small signal gain. AC ELECTRICAL CHARACTERISTICS (VCC = +3.14V to +3.6V, TA = 0°C to +85°C. Typical values are at +3.3V, TA = +25°C, unless otherwise noted. Total source capacitance = 0.7pF.) (Note 2) PARAMETER AC Input Overload Input Referred Noise Power-Supply Rejection Ratio Small-Signal Bandwidth Maximum Skew (Note 7) 2 MAX 460 600 nArms (Note 4) 60 100 kHz IIN > 100µAp-p 20 45 (Note 6) 40 CONDITIONS (Note 3) IN Low-Frequency Cutoff Deterministic Jitter (Note 5) TYP SYMBOL DJ PSRR MIN 2 mAp-p Any two channels within a chip _______________________________________________________________________________________ ps dB 2.4 BW UNITS GHz 50 ps +3.3V, 2.5Gbps Quad Transimpedance Amplifier for System Interconnects (VCC = +3.14V to +3.6V, TA = 0°C to +85°C. Typical values are at +3.3V, TA = +25°C, unless otherwise noted. Total source capacitance = 0.7pF.) (Note 2) AC characteristics are guaranteed by design and characterization. The maximum input current is specified with output deterministic jitter ≤ 45ps. No external compensation capacitors are used. Measured with IIN = 30µAavg. Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse width distortion. Measured with a 213 -1 PRBS with 100 consecutive 0s and 100 consecutive 1s applied to a single channel. See Typical Operating Characteristics. Note 6: PSRR = -20log(∆VOUT / Vnoise(on VCC)), f ≤ 2MHz. Measured by applying DC current = 30µA, and applying 100mVp-p signal at power supply. Note 7: Measured by applying the same input signal to all channels. Skew measurements are made at the 50% point of the transition. Note 2: Note 3: Note 4: Note 5: Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) 65 60 55 35 30 25 20 15 10 10 100 1000 10,000 0 400 FREQUENCY (MHz) 800 1200 1600 CIN = 0.7pF 600 400 10 100 370 350 VCC = +3.14V 330 310 290 270 250 MAX3825 toc05 VCC = +3.6V DC TRANSFER FUNCTION 200 DIFFERENTIAL OUTPUT VOLTAGE (mVp-p) INPUT = 2mAp-p 390 1000 DC INPUT CURRENT (µA) INPUT CURRENT AMPLITUDE (µAp-p) MAX3825 toc04 DIFFERENTIAL OUTPUT AMPLITUDE (mpVp-p) 800 2000 DIFFERENTIAL OUTPUT AMPLITUDE vs. TEMPERATURE 410 1000 0 0 1 1200 200 5 50 MAX3825 toc03 40 1400 INPUT-REFERRED NOISE (nARMS) 45 PEAK-TO-PEAK JITTER (ps) 70 MAX3825 toc02 50 MAX3825 toc01 75 TRANSIMPEDANCE (dB) INPUT-REFERRED RMS NOISE CURRENT vs. DC INPUT CURRENT DETERMINISTIC JITTER vs. INPUT AMPLITUDE FREQUENCY RESPONSE 100 0 -100 -200 -15 10 35 60 AMBIENT TEMPERATURE (°C) 85 -100 -50 0 50 100 INPUT CURRENT (µA) _______________________________________________________________________________________ 3 MAX3825 AC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) ELECTRICAL EYE DIAGRAM INPUT = 20µAp-p, 2.5Gbps, 213 - 1 PRBS 10mV/div MAX3825 toc07 ELECTRICAL EYE DIAGRAM INPUT = 2mAp-p, 2.5Gbps, 213 - 1 PRBS MAX3825 toc06 MAX3825 +3.3V, 2.5Gbps Quad Transimpedance Amplifier for System Interconnects 10mV/div RL = 100Ω DIFFERENTIAL RL = 100Ω DIFFERENTIAL 50ps/div 50ps/div Pad Description 4 PAD NAME FUNCTION 1, 2, 12, 13 N.C. 3 FILTER 4, 6, 8, 10 IN1 to IN4 5, 7, 9, 11 FILT1 to FILT4 14, 17, 40, 43 GNDI4 to GNDI1 15, 16, 41, 42 VCCI4 to VCCI1 18 ENABLE 20, 19, 38, 37 GNDO4 to GNDO1 21, 24 VCCO4 22, 26, 30, 34 OUT4- to OUT1- 23, 27, 31, 35 OUT4+ to OUT1+ 25, 28 VCCO3 Channel 3 Output Stage Positive Supply 29, 32 VCCO2 Channel 2 Output Stage Positive Supply 33, 36 VCCO1 Channel 1 Output Stage Positive Supply 39 GNDF Ground Connection for the Filters. Filter grounds. 44 VCCFILT No Connection. Leave open and unconnected. Connection to internal 180Ω Filter Resistor to VCCFILT for Photodiode Array Cathode Bias Signal Inputs. Channel 1 to channel 4 signal inputs. Filter Connections. Channel 1 to channel 4 connection to internal filter resistors (720Ω to VCCFILT). Input Stage Ground Connections. Channel 4 to channel 1 input stage ground. Input Stage Supply Connections. Channel 4 to channel 1 input stage positive supply. DC Feedback Disable. Disables DC feedback of all four channels when connected to the positive supply (VCC). Left unconnected for normal operation. Output Stage Ground Connections. Channel 4 to channel 1 output stage ground. Channel 4 Output Stage Positive Supply Inverting Outputs. Channel 4 to channel 1 negative outputs. Noninverting Outputs. Channel 4 to channel 1 positive outputs. Power Supply Connection for Filter Resistor _______________________________________________________________________________________ +3.3V, 2.5Gbps Quad Transimpedance Amplifier for System Interconnects VCC FILT 720Ω FILT_ D2 VCCO_ D1 R1 50Ω RF = 1.3kΩ VCCI_ OUT_+ Q2 VCCO_ IN_ Q1 C1 GNDI_ R2 50Ω PARAPHASE AMP OUT_- R5 Q3 VCCI_ Q5 REFERENCE AMP Q4 GNDI_ R3 R4 GNDI_ DC CANCELLATION AMP MAX3825 ENABLE GNDO_ Figure 1. Functional Diagram for One Channel of the MAX3825 Detailed Description The MAX3825 quad TIA circuit is designed for 2.5Gbps SONET/SDH applications. It comprises a transimpedance amplifier, a paraphase amplifier with CML outputs, and a DC cancellation loop to reduce pulse-width distortion (Figure 1). Transimpedance Amplifier The signal current at IN_ flows into the summing node of a high-gain amplifier. Shunt feedback through RF converts this current to a voltage with a gain of 1300Ω. Diodes D1 and D2 clamp the output voltage for large input currents. GNDI_ is a direct connection to the emitter of the input transistor and must be connected directly to the photodetector AC ground return for best performance. DC Cancellation Loop The DC cancellation loop removes the DC component of the input signal by using low-frequency feedback. This feature centers the signal within the MAX3825’s dynamic range, reducing pulse-width distortion. The output of the paraphrase amplifier is sensed through resistors R3 and R4 and then filtered, amplified, and fed back to the base of transistor Q4. The transistor draws the DC component of the input signal away from the transimpedance amplifier’s summing node. The MAX3825 DC cancellation loop is internally compensated and does not require external capacitors in most 2.5Gbps applications. The DC cancellation loop for all channels can be disabled by connecting ENABLE to the positive supply (VCC). ENABLE is inter- _______________________________________________________________________________________ 5 MAX3825 Functional Diagram MAX3825 +3.3V, 2.5Gbps Quad Transimpedance Amplifier for System Interconnects nally pulled low, so it does not need to be bonded out for the DC cancellation loop to function. The MAX3825 minimizes pulse-width distortion for data sequences exhibiting a 50% duty cycle and mark density. An input signal with a duty cycle and mark density significantly different from 50% will cause the MAX3825 to operate improperly. DC cancellation current drawn from the input creates noise. This is not a problem for a low-level signal with little or no DC component. Preamplifier noise increases for a signal with significant DC component (see Typical Operating Characteristics). Paraphase Amplifier and Output Stage The paraphase amplifier converts single-ended inputs to differential outputs, and introduces a voltage gain of 2.8. This signal drives an internally biased emitter coupled pair, Q2 and Q3, which forms the output stage (Figure 1). Resistors R1 and R2 provide back-termination at the outputs, absorbing reflections between the MAX3825 and its load. The differential outputs are designed to drive a 100Ω load between OUT_+ and OUT_-. The MAX3825 can also drive higher output impedances, resulting in increased gain and output voltage swing. Table 1. Optical Power Relations PARAMETER Average Power SYMBOL PAVG RELATION PAVG = (P0 + P1)/2 Extinction Ratio re re = P1/P0 Optical Power of a “1” P1 P1 = 2PAVG(re)/(re + 1) Optical Power of a “0” P0 P0 = 2PAVG/(re + 1) Signal Amplitude PIN PIN = P1 - P0 = 2PAVG (re - 1)/(re + 1) Note: Assuming a 50% input duty cycle and mark density POWER PI PIN PAVG PO Applications Information The MAX3825 is a quad TIA that is ideal for 2.5Gbps SONET/SDH receivers. Its features allow easy design into a fiberoptic module. Optical Power Relations Many of the MAX3825 specifications relate to the input signal amplitude. When working with fiberoptic receivers, the input is usually expressed in terms of average optical power and extinction ratio. Table 1 shows relations that are helpful for converting optical power to an input signal when designing with the MAX3825 (Figure 2). The definitions are true if the mark density and duty cycle of the input data are 50%. Optical Sensitivity Calculation The input-referred RMS noise current (I N ) of the MAX3825 generally determines the receiver sensitivity. To obtain a system bit error rate (BER) of 1 × 10-14, the signal-to-noise ratio must always exceed 15.3. The input sensitivity, expressed in average power, can be estimated as: 15.3IN (re + 1) Sensitivity = 10log10 2ρ(re − 1) × 1000 6 TIME Figure 2. Optical Power Definitions where ρ is the photodiode responsivity in A/W and IN is in µA. Input Optical Overload The overload is the largest input that the MAX3825 accepts while meeting specifications. The optical overload can be estimated in terms of average power with the following equation: I Overload = 10log10 MAX dBm 2ρ where ρ is the photodiode responsivity in A/W and IMAX is in mA. Optical Linear Range The MAX3825’s outputs limit when the input signal exceeds 50µAp-p. The MAX3825 operates in a linear range for inputs not exceeding: _______________________________________________________________________________________ +3.3V, 2.5Gbps Quad Transimpedance Amplifier for System Interconnects where ρ is the photodiode responsivity in A/W. 500Ω Ground Connect all input ground connections as close as possible to the AC ground of the photodetector diode. The photodetector AC ground is usually the ground of the filter capacitor from the photodetector cathode. The total loop (from GNDI_, through the bypass capacitor and the diode, and back to IN_) should be as short as possible. Photodiode Filter Supply voltage noise at the cathode of the photodiode produces a current I = CPD ∆V/∆t, which reduces the receiver sensitivity (C PD is the photodiode capacitance). The filter resistor of the MAX3825, combined with an external capacitor, can be used to reduce this noise (see the Typical Application Circuit). Current generated by the supply noise voltage is divided between CFILTER and CPD. The input noise current due to supply noise is (assuming the filter capacitor is much larger than the photodiode capacitance): INOISE = MAX3825 VCCI_ 50µA(re + 1) Linear Range = 10log10 dBm 2ρ(re − 1) × 1000 VCCI_ 1.3kΩ IN_ 0.1pF 200Ω GNDI_ Figure 3. Equivalent Input Circuit VCCO_ 50Ω 50Ω (VNOISE )(CPD ) (RFILTER )(CFILTER ) OUT+ OUT- Another important parameter is the inductance at the photodiode array’s common cathode. It is important to keep this inductance to a minimum to reduce the coupling between the photodiodes. To keep this inductance small, keep all bond wires as short as possible. Wire Bonding For high current density and reliable operation, the MAX3825 uses gold metalization. Connections to the die should be made with gold wire only, using ball bonding techniques. Wedge bonding is not recommended. Die thickness is typically 14 mils (mm). Interface Models Refer to Figures 3 and 4 for the equivalent input and output circuits of the MAX3825. Chip Information TRANSISTOR COUNT: 1469 PROCESS: BIPOLAR (SILICON GERMANIUM) DIE SIZE: 65 ✕ 99mils/(1651 ✕ 2515 microns) GNDO_ Figure 4. Equivalent Output Circuit _______________________________________________________________________________________ 7 MAX3825 +3.3V, 2.5Gbps Quad Transimpedance Amplifier for System Interconnects Typical Application Circuit VCC PIN ARRAY FILTER FILT1 RFILTER = 180Ω VCC RFILT1 = 720Ω OUT1+ IN1 OUT1FILT2 OUT2+ OUT2- OUT3+ OUT3- IN1OUT1- 50Ω 50Ω IN2+ OUT2+ IN2OUT2- 50Ω 50Ω IN3+ OUT3+ IN3OUT3- RFILT4 = 720Ω OUT4+ IN4 OUT4- CFILTER OUT1+ RFILT3 = 720Ω IN3 FILT4 50Ω IN1+ RFILT2 = 720Ω IN2 FILT3 50Ω MAX3825 QUAD TIA 50Ω 50Ω IN4+ OUT4+ IN4OUT4- MAX3822 QUAD LIMITING AMP LOP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.