CY2213 High Frequency Programmable PECL Clock Generator High Frequency Programmable PECL Clock Generator Features Benefits ■ Jitter peak-peak (Typical) = 35 ps ■ High accuracy clock generation ■ LVPECL output ■ One pair of differential output drivers ■ Default Select option ■ Phase-locked loop (PLL) multiplier select ■ Serially configurable multiply ratios ■ ■ Output edge rate control 8-bit feedback counter and 6-bit reference counter for high accuracy ■ 16-pin TSSOP ■ Minimize electromagnetic interference (EMI) ■ High frequency ■ Industry standard, low cost package saves on board space ■ 3.3 V operation Logic Block Diagram XIN XOUT Xtal Oscillator OE PLL CLK xM CLKB S SER CLK SER DATA Cypress Semiconductor Corporation Document Number: 38-07263 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 10, 2012 CY2213 Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Frequency Table ............................................................... 3 CY2213 Two-Wire Serial Interface ................................... 4 Introduction .................................................................. 4 Serial Interface Specifications ..................................... 4 Serial Interface Format ................................................ 4 Serial Interface Transfer Format ................................. 4 Absolute Maximum Conditions ....................................... 6 Crystal Requirements ...................................................... 6 Electrical Characteristics ................................................. 6 DC Electrical Specifications ........................................ 6 3.3 V DC Device Characteristics ................................. 6 AC Electrical Specifications ......................................... 7 AC Device Characteristics ........................................... 7 State Transition Characteristics .................................. 8 Document Number: 38-07263 Rev. *H Functional Specifications ................................................ 8 Crystal Input ................................................................ 8 Select Input ................................................................. 8 PECL Clock Output Driver ........................................... 8 Signal Waveforms ....................................................... 9 Jitter ........................................................................... 10 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC Solutions ......................................................... 16 Page 2 of 16 CY2213 Pinouts Figure 1. 16-pin TSSOP pinout CY2213 VDDX 1 16 S VSSX 2 15 VDD XOUT 3 14 VSS XIN 4 13 CLK VDD 5 12 CLKB OE 6 11 VSS VSS 7 10 VDD 8 9 SER CLK SER DATA Pin Definitions Pin Name Pin Number Pin Description VDDX 1 3.3 V Power Supply for Crystal Driver VSSX 2 Ground for Crystal Driver XOUT 3 Reference Crystal Feedback XIN 4 Reference Crystal Input VDD 5 3.3 V Power Supply (all VDD pins must be tied directly on board) OE 6 Output Enable, 0 = output disable, 1 = output enable (no internal pull up) VSS 7 Ground SER CLK 8 Serial Interface Clock SER DATA 9 Serial Interface Data VDD 10 3.3 V Power Supply (all VDD pins must be tied directly on board) VSS 11 Ground CLKB 12 LVPECL Output Clock (complement) CLK 13 LVPECL Output Clock VSS 14 Ground VDD 15 3.3 V Power Supply (all VDD pins must be tied directly on board) S 16 PLL Multiplier Select Input, Pull up Resistor Internal Frequency Table S M (PLL Multiplier) 0 × 16 25 MHz 400 MHz 1 ×8 15.625 MHz 125 MHz Document Number: 38-07263 Rev. *H Example Input Crystal Frequency CLK, CLKB Page 3 of 16 CY2213 CY2213 Two-Wire Serial Interface HIGH period of clock. To acknowledge, drive the Sdata LOW before the Sclk rising edge and hold it LOW until the Sclk falling edge. Introduction The CY2213 has a two-wire serial interface designed for data transfer operations, and is used for programming the P and Q values for frequency generation. Sclk is the serial clock line controlled by the master device. Sdata is a serial bidirectional data line. The CY2213 is a slave device and can either read or write information on the dataline upon request from the master device. Figure 2 shows the basic bus connections between master and slave device. The buses are shared by a number of devices and are pulled high by a pull up resistor. Serial Interface Specifications Figure 3 shows the Basic Transmission Specification. To begin and end a transmission, the master device generates a start signal (S) and a stop signal (P). Start (S) is defined as switching the Sdata from HIGH to LOW while the Sclk is at HIGH. Similarly, stop (P) is defined as switching the Sdata from LOW to HIGH while holding the Sclk HIGH. Between these two signals, data on Sdata is synchronous with the clock on the Sclk. Data is allowed to change only at LOW period of clock, and must be stable at the Serial Interface Format Each slave carries an address. The data transfer is initiated by a start signal (S). Each transfer segment is 1 byte in length. The slave address and the read/write bit are first sent from the master device after the start signal. The addressed slave device must acknowledge (Ack) the master device. Depending on the Read/Write bit, the master device either writes data into (logic 0) or reads data (logic 1) from the slave device. Each time a byte of data is successfully transferred, the receiving device must acknowledge. At the end of the transfer, the master device generates a stop signal (P). Serial Interface Transfer Format Figure 3 shows the serial interface transfer format used with the CY2213. Two dummy bytes must be transferred before the first data byte. The CY2213 has only three bytes of latches to store information, and the third byte of data is reserved. Extra data is ignored. Figure 2. Device Connections Rp S d a ta S clk Rp V DD S d a ta _ C S d a ta _ C S clk _ C S d a ta _ in S clk _ in S d ata _ in S c lk _ in M a ste r D e vic e S lav e D ev ice Figure 3. Serial Interface Specifications S clk S data Start (S) Document Number: 38-07263 Rev. *H valid data Acknowledge Stop (P) Page 4 of 16 CY2213 Figure 4. CY2213 Transfer Format 1 bit 7 bits S Slave Address Data 1 1 bit Ack 8 bits 1 bit R/W 8 bits 1 bit 1 bit Ack Dummy Byte 1 Ack Dummy Byte 0 Ack 8 bits 8 bits 1 bit Data 0 Ack P 1 bit Table 1. Serial Interface Address for the CY2213 A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 0 1 0 1 0 Table 2. Serial Interface Programming for the CY2213 b7 b6 b5 b4 b3 b2 b1 QCNTBYP SELPQ Q<5> Q<4> Q<3> Q<2> Data1 P<7> P<6> P<5> P<4> P<3> P<2> P<1> P<0> Data2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved To program the CY2213 using the two-wire serial interface, set the SELPQ bit HIGH. The default setting of this bit is LOW. The P and Q values are determined by the following formulas: Pfinal = (P7..0 + 3) × 2 Qfinal = Q5..0 + 2. Q<1> b0 Data0 Q<0> If the QCNTBYP bit is set HIGH, then Qfinal defaults to a value of 1. The default setting of this bit is LOW. If the SELPQ bit is set LOW, the PLL multipliers are set using the values in the Select Function Table. CyberClocks™ has been developed to generate P and Q values for stable PLL operation. This software is downloadable from www.cypress.com PLL Frequency = Reference x P/Q = Output Figure 5. PLL Block Diagram Reference Q Output VCO P PLL Document Number: 38-07263 Rev. *H Page 5 of 16 CY2213 Absolute Maximum Conditions The following table reflects stress ratings only, and functional operation at the maximums are not guaranteed. Parameter Description Min Max Unit VDD, ABS Maximum voltage on VDD, or VDDX with respect to ground –0.5 4.0 V VI, ABS Maximum voltage on any pin with respect to ground –0.5 VDD + 0.5 V Crystal Requirements Requirements to use parallel mode fundamental xtal. External capacitors are required in the crystal oscillator circuit. Please refer to the application note entitled Crystal Oscillator Topics for details. Parameter XF Description Crystal fundamental frequency Min Max Unit 10 31.25 MHz Min Max Unit 3.00 3.60 V 0 70 °C Electrical Characteristics DC Electrical Specifications Parameter Description VDD Supply voltage TA Ambient operating temperature VIL Input signal low voltage at pin S – 0.35 VDD VIH Input signal high voltage at pin S 0.65 – VDD RPUP Internal pull up resistance 10 100 k tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms 3.3 V DC Device Characteristics (Driving load, Figure 6) Min Typ Max Unit VOH Parameter Output high voltage, referenced to VDD Description –1.02 –0.95 –0.88 V VOL Output low voltage, referenced to VDD –1.81 –1.70 –1.62 V Min Typ Max Unit (Driving load, Figure 7) Parameter Description VOH Output high voltage 1.1 1.2 1.3 V VOL Output low voltage 0 0 0 V Document Number: 38-07263 Rev. *H Page 6 of 16 CY2213 AC Electrical Specifications Parameter Description Min Max Unit fIN Input frequency with driven reference 1 133 MHz fXTAL,IN Input frequency with crystal input 10 31.25 MHz CIN,CMOS Input capacitance at S pin [1] – 10 pF AC Device Characteristics Parameter Description Min Max Unit tCYCLE Clock cycle time 2.50 (400 MHz) 8.00 (125 MHz) ns tJCRMS Cycle-to-cycle RMS jitter – 0.25% % tCYCLE At 125 MHz frequency – 20 ps At 400 MHz frequency – 6.25 ps Cycle-to-cycle jitter (pk-pk) – 1.75% % tCYCLE At 125 MHz frequency – 140 ps tJCPK tJPRMS tJPPK tJLT tJLT tJLT At 200 MHz frequency, XF = 25 MHz – 55 ps At 400 MHz frequency – 43.75 ps Period jitter RMS – 0.25% % tCYCLE At 125 MHz frequency – 20 ps At 400 MHz frequency – 6.25 ps Period jitter (pk-pk) – 2.0% % tCYCLE At 125 MHz frequency – 160 ps At 200 MHz frequency, XF = 25 MHz – 65 ps At 400 MHz frequency – 50 ps Long term RMS Jitter (P < 20) – 1.75% % tCYCLE At 125 MHz frequency – 140 ps At 400 MHz frequency – 43.75 ps Long term RMS Jitter (20 < P < 40) – 2.5% % tCYCLE At 125 MHz frequency – 200 ps At 400 MHz frequency – 62.5 ps Long term RMS Jitter (40 < P < 60) – 3.5% % tCYCLE At 125 MHz frequency – 280 ps At 400 MHz frequency – 87.5 ps –107 –92 dBc 45 55 % Phase Noise Phase Noise at 10 kHz (x8 mode) at 125 MHz DC Long term average output duty cycle tDC,ERR Cycle-cycle duty cycle error at x8 with 15.625 MHz input tCR, tCF Output rise and fall times (measured at 20% – 80% of VOHmin and VOLmax) BWLOOP PLL Loop Bandwidth – 70 ps 100 400 ps 50 kHz (–3 dB) 8 MHz (–20 dB) Note 1. Capacitance measured at frequency = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV Document Number: 38-07263 Rev. *H Page 7 of 16 CY2213 State Transition Characteristics Specifies the maximum settling time of the CLK and CLKB outputs from device power up. For VDD and VDDX any sequences are allowed to power up and power down the CY2213. From VDD/VDDX On To Transition Latency Description 3 ms Time from VDD/VDDX is applied and settled to CLK/CLKB outputs settled. CLK/CLKB Normal Functional Specifications Select Input Crystal Input The CY2213 receives its reference from an external crystal. Pin XIN is the reference crystal input, and pin XOUT is the reference crystal feedback. The parameters for the crystal are illustrated in AC Device Characteristics on page 7. The oscillator circuit requires external capacitors. Please refer to the application note entitled Crystal Oscillator Topics for details. There is only one select input, pin S. This pin selects the frequency multiplier in the PLL, and is a standard LVCMOS input. The S pin has an internal pull up resistor. The multiplier selection is illustrated in Frequency Table on page 3. PECL Clock Output Driver Figure 6 and Figure 7 show the Clock Output Driver. Figure 6. Output Driving Load (-1) VDD 82 130 Measurement Point 82 50 PECL Differential Driver 50 130 130 130 Measurement Point Figure 7. Output Driving Load (-2) Measurement Point 62 45 PECL Differential Driver 45 62 45 45 Measurement Point Document Number: 38-07263 Rev. *H Page 8 of 16 CY2213 An alternative termination scheme can be used to drive a standard PECL fanout buffer. Figure 8. Output Driving Load (-3) VDD 135 135 79 Measurement Point 50 PECL Differential Driver 50 79 79 79 Measurement Point The PECL differential driver is designed for low voltage, high frequency operation. It significantly reduces the transient switching noise and power dissipation when compared to conventional CMOS drivers. The nominal value of the channel impedance is 50. The pull up and pull down resistors provide matching channel termination. The combination of the differential driver and the output network determines the voltage swing on the channel. The output clock is specified at the measurement point indicated in Figure 6 on page 8 and Figure 7 on page 8. Signal Waveforms A physical signal that appears at the pins of the device is deemed valid or invalid depending on its voltage and timing relations with other signals. This section defines the voltage and timing waveforms for the input and output pins of the CY2213. The Device Characteristics tables list the specifications for the device parameters that are defined here. Input and Output voltage waveforms are defined as shown in Figure 9. Rise and fall times are defined as the 20% and 80% measurement points of VOHmin – VOLmax. The device parameters are defined in Table 3. Figure 10 on page 10 shows the definition of long term duty cycle, which is simply the CLK waveform high time divided by the cycle time (defined at the crossing point). Long term duty cycle is the average over many (>10,000) cycles. DC is defined as the Output Clock Long Term Duty Cycle. Table 3. Definition of Device Parameters Parameter Definition VOH, VOL Clock output high and low voltages VIH, VIL VDD LVCMOS input high and low voltages tCR, tCF Clock output rise and fall times Figure 9. Voltage Waveforms VOHmin 80% V(t) 20% tCF Document Number: 38-07263 Rev. *H tCR VOLmax Page 9 of 16 CY2213 Figure 10. Duty Cycle Jitter CLK CLKB tPW+ tCYCLE DC = tPW+/tCYCLE Jitter This section defines the specifications that relate to timing uncertainty (or jitter) of the input and output waveforms. Figure 11 shows the definition of period jitter with respect to the falling edge of the CLK signal. Period jitter is the difference between the minimum and maximum cycle times over many cycles (typically 12,800 cycles at 400 MHz). Equal requirements apply for rising edges of the CLK signal. tJP is defined as the output period jitter. apply for rising edges of the CLK signal. tJC is defined as the Clock Output Cycle-to-cycle Jitter. Figure 12 shows the definition of cycle-to-cycle jitter with respect to the falling edge of the CLK signal. Cycle-to-cycle jitter is the difference between cycle times of adjacent cycles over many cycles (typically 12,800 cycles at 400 MHz). Equal requirements Figure 14 on page 11 shows the definition of long-term jitter error. Long term jitter is defined as the accumulated timing error over many cycles (typically 12,800 cycles at 400 MHz). It applies to both rising and falling edges. tJLT is defined as the long term jitter. Figure 13 on page 11 shows the definition of cycle-to-cycle duty cycle error. Cycle-to-cycle duty cycle error is defined as the difference between high-times of adjacent cycles over many cycles (typically 12,800 cycles at 400 MHz). Equal requirements apply to the low-times. tDC,ERR is defined as the Clock Output Cycle-to-cycle Duty Cycle Error. Figure 11. Period Jitter CLK CLKB tCYCLE tJP = tCYCLE,max – tCYCLE, min. over many cycles Figure 12. Cycle-to-cycle Jitter CLK CLKB tCYCLE,i tCYCLE, i+1 tJC = tCYLCE,i – tCYCLE,i+1 over many consecutive cycles Document Number: 38-07263 Rev. *H Page 10 of 16 CY2213 Figure 13. Cycle-to-cycle Duty Cycle Error Cycle i CLK Cycle i+1 CLKB tPW+,i+1 tCYCLE,i+1 tPW+,i tCYCLE, i+1 tDC,ERR = tPW+,i – tPW+,i+1 over many consecutive cycles Figure 14. Long-term Jitter CLK CLKB tmin tmax tJLT = tmax – tmin over many cycles Document Number: 38-07263 Rev. *H Page 11 of 16 CY2213 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY2213ZXC-1 16-pin TSSOP Commercial, to 400 MHz 3.3 V CY2213ZXC-1T 16-pin TSSOP – Tape and Reel Commercial, to 400 MHz 3.3 V Ordering Code Definitions CY 2213 Z X C - 1 X X = blank or T blank = Tube; T = Tape and Reel Fixed Temperature Range: C = Commercial Pb-free Package Type: Z = 16-pin TSSOP Part Identifier Company ID: CY = Cypress Document Number: 38-07263 Rev. *H Page 12 of 16 CY2213 Package Diagrams Figure 15. 16-pin TSSOP (4.40 mm Body) Z16.173/ZZ16.173 Package Outline, 51-85091 51-85091 *D Document Number: 38-07263 Rev. *H Page 13 of 16 CY2213 Acronyms Acronym Document Conventions Description Units of Measure CMOS complementary metal-oxide semiconductor DC duty cycle C degree Celsius EMI electromagnetic interference k kilohm LVCMOS low voltage complementary metal-oxide semiconductor MHz megahertz LVPECL low voltage pseudo (positive) emitter coupled logic ms millisecond OE output enable ns nanosecond PECL pseudo (positive) emitter coupled logic ohm PLL phase locked loop % percent TSSOP thin-shrink small outline package Document Number: 38-07263 Rev. *H Symbol Unit of Measure pF picofarad ps picosecond V volt Page 14 of 16 CY2213 Document History Page Document Title: CY2213, High Frequency Programmable PECL Clock Generator Document Number: 38-07263 Rev. ECN Submission Date Orig. of Change ** 113090 02/06/02 DSG Description of Change Change from Spec number: 38-01100 to 38-07263 *A 113512 05/24/02 CKN Added PLL Block Diagram (Figure 5) and PLL frequency equation *B 121882 12/14/02 RBI Power up requirements added to Operating Conditions *C 123215 12/19/02 LJN Previous revision was released with incorrect *A numbering in footer; *A should have been *B (and was changed accordingly) *D 124012 03/05/03 CKN Added -2 to data sheet; edited line 3 of Benefits *E 126557 05/27/03 RGL Added 200 MHz Jitter Spec. Added optional output termination *F 2738056 07/14/09 CXQ Obsolete document. *G 2742301 07/22/09 CXQ Undo obsolete document. Removed all references to obsolete -2 option. Changed Ordering Information entry to Pb-free CY2213ZXC-1 and -1T. Revised the version of Package Drawing from 51-85091 ** to 51-85091 *A. *H 3709157 08/10/2012 PURU Added Ordering Code Definitions. Updated Package Diagrams (spec 51-85091 (Changed revision from *A to *D)). Added Acronyms and Units of Measure. Updated in new template. Document Number: 38-07263 Rev. *H Page 15 of 16 CY2213 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2002-2012. The information contained herein is subject to change without notice. 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Document Number: 38-07263 Rev. *H Revised August 10, 2012 Page 16 of 16 CyberClocks™ is a trademark of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.