CY8C20336H, CY8C20446H ® Haptics Enabled CapSense Controller Features ■ 1.71-V to 5.5-V operating range Low power CapSense® block ❐ Configurable capacitive sensing elements ❐ Supports combination of CapSense buttons, sliders, touchpads, touchscreens, and proximity sensors ■ Powerful Harvard-architecture processor ❐ M8C CPU speed can be up to 24 MHz or sourced by an external crystal, resonator, or clock signal ❐ Low power at high speed ❐ Interrupt controller ❐ Temperature range: –40 °C to +85 °C ■ Flexible on-chip memory ❐ Two program/data storage size options: • CY8C20336H: 8 KB flash / 1 KB SRAM • CY8C20446H: 16 KB flash / 2 KB SRAM ❐ 50,000 flash erase/write cycles ❐ Partial flash updates ❐ Flexible protection modes ❐ In-System Serial Programming (ISSP) ■ Integrates Immersion TS2000 Haptics technology for ERM drive control ■ Versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of I/O ❐ High Power supply rejection ratio (PSRR) comparator ❐ Low dropout voltage regulator for all analog resources ■ Additional system resources ❐ I2C slave: • Selectable to 50 kHz, 100 kHz, or 400 kHz • No clock stretching (under most conditions) • Implementation during sleep modes with less than 100 µA • Hardware address validation ❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz ❐ Three 16-bit timers ❐ Watchdog and sleep timers ❐ Internal voltage reference ❐ Integrated supervisory circuit ❐ 8- to 10-bit incremental analog-to-digital converter (ADC) ❐ Two general-purpose high-speed, low-power analog comparators ■ Complete development tools ❐ Free development tool (PSoC Designer™) ❐ Full featured, In-Circuit Emulator (ICE) and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128 KB trace memory ■ Package options ❐ CY8C20336H: • 24-pin 4 × 4 × 0.6 mm QFN ❐ CY8C20446H: • 32-pin 5 × 5 × 0.6 mm QFN ■ ■ Precision, programmable clocking ❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5% ❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog and sleep timers ❐ Precision 32-kHz oscillator for optional external crystal ■ Programmable pin configurations ❐ Up to 28 general-purpose I/Os (GPIOs) (depending on the package) ❐ Dual-mode GPIO: All GPIOs support digital I/O and analog inputs ❐ 25-mA sink current on each GPIO • 120-mA total sink current on all GPIOs ❐ Pull-up, high Z, open drain modes on all GPIOs ❐ CMOS drive mode: 5-mA source current on ports 0 and 1 and 1 mA on ports 2, 3, and 4 • 20-mA total source current on all GPIOs ❐ Selectable, regulated digital I/O on port 1 ❐ Configurable input threshold on port 1 ❐ Hot swap capability on all port 1 GPIOs Cypress Semiconductor Corporation Document Number: 001-56223 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 •408-943-2600 Revised June 15, 2012 CY8C20336H, CY8C20446H Logic Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 1.8/2.5/3V LDO PWRSYS  (Regulator) PSoC CORE SYSTEM BUS Global Analog Interconnect 1K/2K SRAM Supervisory ROM (SROM) Interrupt Controller 8K/16K Flash Nonvolatile Memory Sleep and Watchdog CPU Core (M8C) 6/12/24 MHz Internal Main Oscillator (IMO) Internal Low Speed Oscillator (ILO) Multiple Clock Sources CAPSENSE SYSTEM Analog Reference CapSense Module Two Comparators Analog Mux SYSTEM BUS I2C Slave Internal Voltage References System Resets POR and LVD SPI Master/ Slave Three 16-Bit Programmable Timers Digital Clocks SYSTEM RESOURCES Note 1. Internal voltage regulator for internal circuitry Document Number: 001-56223 Rev. *D Page 2 of 35 CY8C20336H, CY8C20446H Contents PSoC® Functional Overview ............................................ 4 PSoC Core .................................................................. 4 CapSense System ....................................................... 4 Haptics TS2000 Controller .......................................... 4 Additional System Resources ..................................... 5 Getting Started .................................................................. 5 Application Notes ........................................................ 5 Development Kits ........................................................ 5 Training ....................................................................... 5 CYPros Consultants .................................................... 5 Solutions Library .......................................................... 5 Technical Support ....................................................... 5 Development Tools .......................................................... 6 PSoC Designer Software Subsystems ........................ 6 Designing with PSoC Designer ....................................... 7 Select User Modules ................................................... 7 Configure User Modules .............................................. 7 Organize and Connect ................................................ 7 Generate, Verify, and Debug ....................................... 7 Pinouts .............................................................................. 8 24-Pin QFN ................................................................ 8 32-Pin QFN ................................................................ 9 48-Pin QFN OCD ...................................................... 10 Electrical Specifications ................................................ 11 Absolute Maximum Ratings ....................................... 11 Operating Temperature ............................................. 11 DC Chip-Level Specifications .................................... 12 DC General Purpose I/O Specifications .................... 13 DC Analog Mux Bus Specifications ........................... 15 DC Low Power Comparator Specifications ............... 15 Comparator User Module Electrical Specifications ... 16 ADC Electrical Specifications ................................... 16 DC POR and LVD Specifications .............................. 17 DC Programming Specifications ............................... 17 Document Number: 001-56223 Rev. *D AC Chip-Level Specifications .................................... 18 AC General Purpose I/O Specifications .................... 19 AC Comparator Specifications .................................. 20 AC External Clock Specifications .............................. 20 AC Programming Specifications ................................ 21 AC I2C Specifications ................................................ 22 Packaging Information ................................................... 26 Thermal Impedances ................................................ 28 Capacitance on Crystal Pins .................................... 28 Solder Reflow Peak Temperature ............................. 28 Development Tool Selection ......................................... 29 Software .................................................................... 29 Development Kits ...................................................... 29 Evaluation Tools ............................................................. 29 Device Programmers ................................................. 30 Accessories (Emulation and Programming) .............. 30 Third Party Tools ....................................................... 30 Build a PSoC Emulator into Your Board .................... 30 Ordering Information ...................................................... 31 Ordering Code Definitions ......................................... 31 Document Conventions ................................................. 32 Acronyms Used ......................................................... 32 Units of Measure ....................................................... 32 Numeric Naming ........................................................ 32 Glossary .......................................................................... 33 Reference Documents .................................................... 33 Document History Page ................................................. 34 Sales, Solutions, and Legal Information ...................... 35 Worldwide Sales and Design Support ....................... 35 Products .................................................................... 35 PSoC Solutions ......................................................... 35 Page 3 of 35 CY8C20336H, CY8C20446H PSoC® Functional Overview Figure 1. CapSense System Block Diagram The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low-cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. CS1 IDAC The core ■ CapSense analog system ■ System resources (including a full-speed USB port). Analog Global Bus CSN Vr The architecture for this device family, as shown in the Logic Block Diagram on page 2, consists of three main areas: ■ CS2 Reference Buffer Cinternal Cexternal (P0 or P0) Comparator Mux A common, versatile bus allows connection between the I/O and the analog system. Mux Each CY8C20336H/446H PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 28 GPIOs are also included. The GPIOs provide access to the MCU and analog mux. Refs Cap Sense Counters CSCLK PSoC Core The PSoC core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvardarchitecture microprocessor. CapSense System The analog system contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. The analog system is composed of the CapSense PSoC block and an internal 1-V or 1.2-V analog reference, which together support capacitive sensing of up to 28 inputs. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins are completed quickly and easily across multiple ports. SmartSense™ SmartSense is an innovative solution from Cypress that removes manual tuning of CapSense applications. This solution is easyto-use and provides a robust noise immunity. It is the only autotuning solution that establishes, monitors, and maintains all required tuning parameters. SmartSense allows engineers to go from prototyping to mass production without re-tuning for manufacturing variations in PCB and/or overlay material properties. IMO CapSense Clock Select Oscillator Analog Multiplexer System The analog mux bus can connect to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch-control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ Complex capacitive sensing interfaces, such as sliders and touchpads. ■ Chip-wide mux that allows analog input from any I/O pin. ■ Crosspoint connection between any I/O pin combinations. Haptics TS2000 Controller The CY8C20336H/CY8C20446H family of devices feature an easy-to-use Haptics controller resource with up to 14 different effects. These effects are available for use with three different, selectable ERM modules. Note 2. 36 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulator capacitor. Document Number: 001-56223 Rev. *D Page 4 of 35 CY8C20336H, CY8C20446H Additional System Resources Getting Started System resources provide additional capability, such as configurable USB and I2C slave, SPI master/slave communication interface, three 16-bit programmable timers, and various system resets supported by the M8C. For in depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. These system resources provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The merits of each system resource are listed here: Application Notes ■ ■ ■ ■ The I2C slave/SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). The I2C hardware address recognition feature reduces the already low power consumption by eliminating the need for CPU intervention until a packet addressed to the target device is received. The I2C enhanced slave interface appears as a 32-byte RAM buffer to the external I2C master. Using a simple predefined protocol, the master controls the read and write pointers into the RAM. When this method is enabled, the slave does not stall the bus when receiving data bytes in active mode. For usage details, refer to the application note I2C Enhanced Slave Operation - AN56007. Low voltage detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced poweron-reset (POR) circuit eliminates the need for a system supervisor. ■ An internal reference provides an absolute reference for capacitive sensing. ■ A register-controlled bypass mode allows the user to disable the LDO regulator. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Document Number: 001-56223 Rev. *D Page 5 of 35 CY8C20336H, CY8C20446H Development Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration ■ Extensive user module catalog ■ Integrated source-code editor (C and assembly) ■ Free C compiler with no size restrictions or time limits ■ Built-in debugger ■ In-circuit emulation ■ Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-toanalog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this lets you to use more than 100 percent of PSoC's resources for an application. Document Number: 001-56223 Rev. *D Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also lets you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Page 6 of 35 CY8C20336H, CY8C20446H Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Document Number: 001-56223 Rev. *D Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment lets you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Page 7 of 35 CY8C20336H, CY8C20446H Pinouts The CY8C20336H/CY8C20446H PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not capable of digital I/O. 24-Pin QFN Table 1. Pin Definitions - CY8C20336H [3, 4] 5 IOHR I P1 I2C SDA, SPI MISO 6 IOHR I P1 SPI CLK P1 ISSP CLK, I2C SCL, SPI MOSI 9 Power NC No connection Vss Ground connection ISSP DATA, I2C SDA, SPI CLK 10 IOHR I P1 11 IOHR I P1 12 IOHR I P1 13 IOHR I P1 14 Input XRES 15 I/O I P2 16 IOH I P0 17 IOH I P0 18 IOH I P0 19 IOH I P0 20 Power VDD Optional external clock input (EXTCLK) Active high external reset with internal pull down IOH I P0 22 IOH I P0 23 IOH I P0 Integrating input 24 IOH I P0 Integrating input VSS Center pad must be connected to ground Power 17 3 QFN 16 4 ( Top View) 15 5 14 6 13 P0 , AI P0 , AI P0 , AI P2 , AI XRES P1 , AI Supply voltage 21 CP 18 2 7 I AI , P2 AI , I2 C SCL, SPI SS, P1 AI , I2 C SDA, SPI MISO, P1 AI , SPI CLK, P1 1 AI, ISSP CLK, I2C SCL, SPI MOSI, P1 NC Vss IOHR 8 AI , XOut, P2 AI , XIn, P2 19 I2C SCL, SPI SS 12 P1 21 P2 I 20 I IOHR 11 I/O 4 22 3 9 Crystal input (XIn) 10 Crystal output (XOut) P2 AI, ISSP DATA, I 2 C SDA, SPI CLK, P1 AI, P1 AI, EXTCLK, P1 P2 I P0, AI P0, AI P0, AI P0, AI VDD P0, AI I I/O 24 I/O 2 23 1 7 Figure 2. CY8C20336H PSoC Device Description 8 Type Pin No. Digital Analog Name LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 3. During power-up or reset event, device P1 and P1 may disturb the I2C bus. Use alternate pins if you encounter any issues. 4. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 5. These are the ISSP pins, which are not High Z at POR (Power On Reset). Document Number: 001-56223 Rev. *D Page 8 of 35 CY8C20336H, CY8C20446H 32-Pin QFN Table 2. Pin Definitions - CY8C20446H PSoC Device [6, 7] I/O I P2 Crystal input (XIn) 5 I/O I P2 6 I/O I P3 I/O I P3 8 IOHR I P1 I2C SCL, SPI SS 9 IOHR I P1 I2C SDA, SPI MISO 10 IOHR I P1 SPI CLK. 11 IOHR I P1 ISSP CLK, I2C SCL, SPI MOSI. 12 Vss Ground connection. 13 IOHR Power I P1 ISSP DATA, I2C SDA., SPI CLK 14 IOHR I P1 15 IOHR I P1 16 IOHR I P1 17 Input XRES 18 I/O I P3 19 I/O I P3 20 I/O I P2 21 I/O I P2 22 I/O I P2 23 I/O I P2 24 IOH I P0 25 IOH I P0 26 IOH I P0 27 IOH I P0 28 Power VDD 29 IOH I P0 30 IOH I P0 31 IOH I 32 31 Optional external clock input (EXTCLK) Active high external reset with internal pull down 1 2 3 4 5 6 7 8 9 7 AI , P0 AI , P2 AI , XOut, P2 AI , XIn, P2 AI , P2 AI , P3 AI , P3 AI , I2 C SCL, SPI SS, P1 P0 , AI P0 , AI Crystal output (XOut) 4 26 25 P2 QFN (Top View) 24 23 22 21 20 19 18 17 15 16 P2 I AI, E XTCLK, P 1 AI, P 1 I I/O P0 , AI VDD P0 , AI I/O 3 28 27 2 Integrating input 13 14 I 30 29 IOH AI, ISSP CLK, I2C SCL, SPI MOSI,P1 VSS AI, ISSP DATA, I 2 C SDA, SPI CLK, P1 AI, P 1 1 P0 Figure 3. CY8C20446H PSoC Device Description VSS P0 , AI P0 , AI Name Analog 10 11 12 Type Digital AI, I2C SDA, SPI MISO, P 1 AI, SPI CLK, P 1 Pin No. P0 , AI P2 , AI P2 , AI P2 , AI P2 , AI P3 , AI P3 , AI XRES Supply voltage P0 Integrating input 32 Power VSS Ground connection CP Power VSS Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 6. During power-up or reset event, device P1 and P1 may disturb the I2C bus. Use alternate pins if you encounter any issues. 7. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 8. These are the ISSP pins, which are not High Z at POR (Power On Reset). Document Number: 001-56223 Rev. *D Page 9 of 35 CY8C20336H, CY8C20446H 48-Pin QFN OCD The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit debugging. Table 3. Pin Definitions - CY8C20066A PSoC Device [10, 11] I P2 3 I/O I P2 Crystal output (XOut) 4 I/O I P2 Crystal input (XIn) 5 I/O I P2 6 I/O I P4 7 I/O I P4 8 I/O I P3 9 I/O I P3 10 I/O I P3 11 I/O I P3 12 IOHR I P1 I2C SCL, SPI SS 13 IOHR I P1 I2C SDA, SPI MISO OCD high speed clock output 16 IOHR I P1 SPI CLK. 17 IOHR I P1 ISSP CLK, I2C SCL, SPI MOSI Vss Ground connection 19 I/O D+ USB D+ 20 I/O D- USB D- VDD Supply voltage ISSP DATA(12), I2C SDA, SPI CLK 21 Power Power 22 IOHR I P1 23 IOHR I P1 37 IOH I P0 38 IOH I P0 39 IOH I P0 IOH I P0 Pin No. 24 IOHR I P1 25 IOHR I P1 26 Input XRES Optional external clock input (EXTCLK) Active high external reset with internal pull down VSS P0, AI P0[5 ], AI P0, AI OCDE 48 47 46 45 44 43 1 2 3 4 5 6 QFN 7 8 9 10 11 12 (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 P2 , AI P2 , AI P2 , AI P2 , AI P4 , AI P4 , AI P3 , AI P3 , AI P3 , AI P3 , AI XRES P1 , AI I 2 C SDA, SPI MISO, AI, P1 CCLK HCLK SPI CLK, A I, P1 AI, ISSP CLK, I 2 C SCL, SPI MOSI, P1 Vss D+ DVDD AI, DATA1, I 2 C SDA, SPI CLK, P1 AI, P 1 AI, EXTCLK, P1 HCLK Analog OCD CPU clock output 15 Digital CCLK OCDOE AI, P2 AI, XOut, P2 AI, XIn , P2 AI , P2 AI , P4 AI , P4 AI , P3 AI , P3 AI , P3 AI , P3 AI, I2 C SCL, SPI SS, P1 13 14 15 16 17 18 19 20 21 22 23 24 OCDOE OCD mode direction pin 14 18 P0, AI Description OCDO VDD P0, AI P0, AI P0, AI P0, AI Analog I/O 1 Name 42 41 40 39 38 37 Digital Figure 4. CY8C20066A PSoC Device 2 Pin No. Name Description 27 I/O I P3 40 28 I/O I P3 41 VDD Supply voltage 29 I/O I P3 42 OCDO OCD even data I/O 30 I/O I P3 43 OCDE OCD odd data output 31 I/O I P4 44 IOH I P0 32 I/O I P4 45 IOH I P0 33 I/O I P2 46 IOH I P0 Integrating input 34 I/O I P2 47 VSS Ground connection 35 I/O I P2 48 36 I/O I P2 CP Power Power IOH Power I P0 VSS Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output. Notes 9. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes. 10. During power-up or reset event, device P1 and P1 may disturb the I2C bus. Use alternate pins if you encounter any issues. 11. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 12. These are the ISSP pins, which are not High Z at power on reset (POR). Document Number: 001-56223 Rev. *D Page 10 of 35 CY8C20336H, CY8C20446H Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20x36H/46H PSoC devices. For the latest electrical specifications, confirm that you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc. Figure 5. Voltage versus CPU Frequency 5.5V Vdd Voltage li d ng Va rati n e io Op Reg 1.71V 750 kHz 3 MHz CPU 24 MHz Frequency Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 4. Absolute Maximum Ratings Symbol Description Conditions Min Typ Max Units Higher storage temperatures reduce data retention time. Recommended Storage Temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 85 °C degrades reliability. –55 +25 +125 °C –0.5 – +6.0 V TSTG Storage temperature VDD Supply voltage relative to VSS VIO DC input voltage VSS – 0.5 – VDD + 0.5 V VIOZ DC voltage applied to tristate VSS –0.5 – VDD + 0.5 V IMIO Maximum current into any port pin ESD Electrostatic discharge voltage Human body model ESD LU Latch up current In accordance with JESD78 standard –25 – +50 mA 2000 – – V – – 200 mA Min Typ Max Units –40 – +85 °C 0 – 70 °C –40 – +100 °C Operating Temperature Table 5. Operating Temperature Symbol Description TA Ambient temperature TC Commercial temperature range TJ Operational die temperature Document Number: 001-56223 Rev. *D Conditions The temperature rise from ambient to junction is package specific. Refer the table Thermal Impedances per Package on page 28. The user must limit the power consumption to comply with this requirement. Page 11 of 35 CY8C20336H, CY8C20446H DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 6. DC Chip-Level Specifications Symbol VDD  Description Conditions Min Typ Max Units 1.71 – 5.50 V Supply voltage Refer the table DC POR and LVD Specifications on page 17 IDD24 Supply current, IMO = 24 MHz Conditions are VDD 3.0 V, TA = 25 °C, CPU = 24 MHz. CapSense running at 12 MHz, no I/O sourcing current – 3.32 4.00 mA IDD12 Supply current, IMO = 12 MHz Conditions are VDD 3.0 V, TA = 25 °C, CPU = 12 MHz. CapSense running at 12 MHz, no I/O sourcing current – 1.86 2.60 mA IDD6 Supply current, IMO = 6 MHz Conditions are VDD 3.0 V, TA = 25 °C, CPU = 6 MHz. CapSense running at 6 MHz, no I/O sourcing current – 1.13 1.80 mA ISB0 Deep sleep current VDD 3.0 V, TA = 25 °C, I/O regulator turned off – 0.10 0.50 A ISB1 Standby current with POR, LVD, and sleep timer VDD 3.0 V, TA = 25 °C, I/O regulator turned off – 1.07 1.50 A Note 13. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µsec, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 usec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. Document Number: 001-56223 Rev. *D Page 12 of 35 CY8C20336H, CY8C20446H DC General Purpose I/O Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and –40 °C TA 85°C, 2.4 V to 3.0 V and –40 °C TA 85 °C, or 1.71 V to 2.4 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 7. 3.0 V to 5.5 V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units RPU Pull-up resistor 4 5.60 8 k VOH1 High output voltage port 2 or 3 pins IOH < 10 A, maximum of 10 mA source current in all I/Os VDD – 0.20 – – V VOH2 High output voltage port 2 or 3 pins IOH = 1 mA, maximum of 20 mA source current in all I/Os VDD – 0.90 – – V VOH3 High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 IOH < 10 A, maximum of 10 mA source current in all I/Os VDD – 0.20 – – V VOH4 High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 IOH = 5 mA, maximum of 20 mA source current in all I/Os VDD – 0.90 – – V VOH5 High output voltage port 1 pins with LDO regulator enabled for 3 V out IOH < 10 A, VDD > 3.1 V, maximum of 4 I/Os all sourcing 5 mA 2.85 3.00 3.30 V VOH6 High output voltage port 1 pins with LDO regulator enabled for 3 V out IOH = 5 mA, VDD > 3.1 V, maximum of 20 mA source current in all I/Os 2.20 – – V VOH7 High output voltage IOH < 10 A, VDD > 2.7 V, maximum of port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os out 2.35 2.50 2.75 V VOH8 IOH = 2 mA, VDD > 2.7 V, maximum of High output voltage port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os out 1.90 – – V VOH9 High output voltage IOH < 10 A, VDD > 2.7 V, maximum of port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out 1.60 1.80 2.10 V VOH10 High output voltage IOH = 1 mA, VDD > 2.7 V, maximum of port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out 1.20 – – V VOL Low output voltage – – 0.75 V IOL = 25 mA, VDD > 3.3 V, maximum of 60 mA sink current on even port pins (for example, P0 and P1) and 60 mA sink current on odd port pins (for example, P0 and P1) VIL Input low voltage – – 0.80 V VIH Input high voltage 2.00 – – V VH Input hysteresis voltage – 80 – mV IIL Input leakage (absolute value) – 0.001 1 A CPIN Pin capacitance 0.50 1.70 7 pF Document Number: 001-56223 Rev. *D Package and pin dependent Temp = 25 °C Page 13 of 35 CY8C20336H, CY8C20446H Table 8. 2.4 V to 3.0 V DC GPIO Specifications Symbol Description Min Typ Max Units 4 5.60 8 k IOH < 10 A, maximum of 10 mA source VDD – 0.20 current in all I/Os – – V High output voltage port 2 or 3 pins IOH = 0.2 mA, maximum of 10 mA source current in all I/Os VDD – 0.40 – – V VOH3 High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 IOH < 10 A, maximum of 10 mA source VDD – 0.20 current in all I/Os – – V VOH4 High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 IOH = 2 mA, maximum of 10 mA source VDD – 0.50 current in all I/Os – – V VOH5A High output voltage IOH < 10 A, VDD > 2.4 V, maximum of port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out 1.50 1.80 2.10 V VOH6A High output voltage IOH = 1 mA, VDD > 2.4 V, maximum of port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out 1.20 – – V VOL Low output voltage – – 0.75 V VIL Input low voltage – – 0.72 V VIH Input high voltage 1.40 – – V VH Input hysteresis voltage – 80 – mV IIL Input leakage (absolute value) CPIN Capacitive load on pins RPU Pull-up resistor VOH1 High output voltage port 2 or 3 pins VOH2 Conditions IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0 and P1) and 30 mA sink current on odd port pins (for example, P0 and P1) Package and pin dependent Temp = 25 °C – 1 1000 nA 0.50 1.70 7 pF Min Typ Max Units 4 Table 9. 1.71 V to 2.4 V DC GPIO Specifications Symbol Description Conditions RPU Pull-up resistor 5.60 8 k VOH1 High output voltage port 2 or 3 pins IOH = 10 A, maximum of 10 mA source VDD – 0.20 current in all I/Os – – V VOH2 High output voltage port 2 or 3 pins IOH = 0.5 mA, maximum of 10 mA source current in all I/Os VDD – 0.50 – – V VOH3 High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 IOH = 100 A, maximum of 10 mA source current in all I/Os VDD – 0.20 – – V VOH4 High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 IOH = 2 mA, maximum of 10 mA source VDD – 0.50 current in all I/Os – – V VOL Low output voltage IOL = 5 mA, maximum of 20 mA sink current on even port pins (for example, P0 and P1) and 30 mA sink current on odd port pins (for example, P0 and P1) – – 0.40 V VIL Input low voltage – – 0.30 × VDD V VIH Input high voltage 0.65 × VDD – – V Document Number: 001-56223 Rev. *D Page 14 of 35 CY8C20336H, CY8C20446H Table 9. 1.71 V to 2.4 V DC GPIO Specifications (continued) Symbol Description Conditions Min Typ Max Units VH Input hysteresis voltage – 80 – mV IIL Input leakage (absolute value) – 1 1000 nA CPIN Capacitive load on pins 0.50 1.70 7 pF Package and pin dependent Temp = 25 °C Table 10.DC Characteristics – USB Interface Symbol Min Typ Max Units USB D+ pull-up resistance With idle bus 900 – 1575 Rusba USB D+ pull-up resistance While receiving traffic 1425 – 3090 Vohusb Static output high 2.8 – 3.6 V Rusbi Description Volusb Static output low Vdi Differential input sensitivity Conditions – – 0.3 V 0.2 – – V Vcm Differential input common mode range 0.8 – 2.5 V Vse Single-ended receiver threshold 0.8 – 2.0 V Cin Transceiver capacitance Iio High-Z state data line leakage Rps2 PS/2 pull-up resistance Rext External USB series resistor On D+ or D- line In series with each USB pin – – 50 pF –10 – +10 A 3000 5000 7000 21.78 22.0 22.22 DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 11. DC Analog Mux Bus Specifications Min Typ Max Units RSW Symbol Switch resistance to common analog bus Description Conditions – – 800 RGND Resistance of initialization switch to VSS – – 800 The maximum pin voltage for measuring RSW and RGND is 1.8 V DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 12. DC Comparator Specifications Symbol Description Conditions Min Typ Max Units 0.0 – 1.8 V LPC supply current – 10 40 A LPC voltage offset – 2.5 30 mV VLPC Low power comparator (LPC) common Maximum voltage limited to VDD mode ILPC VOSLPC Document Number: 001-56223 Rev. *D Page 15 of 35 CY8C20336H, CY8C20446H Comparator User Module Electrical Specifications The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: –40 °C TA 85 °C, 1.71 V VDD 5.5 V. Table 13. Comparator User Module Electrical Specifications Symbol Min Typ Max Units 50-mV overdrive – 70 100 ns Offset Valid from 0.2 V to VDD – 0.2 V – 2.5 30 mV Current Average DC current, 50 mV overdrive – 20 80 µA Supply voltage > 2 V Power supply rejection ratio – 80 – dB Supply voltage < 2 V Power supply rejection ratio – 40 – dB 0 – 1.5 V Min Typ Max Units 0 – VREFADC V TCOMP PSRR Description Comparator response time Conditions Input Range ADC Electrical Specifications Table 14.ADC User Module Electrical Specifications Symbol Description Conditions Input VIN Input voltage range CIIN Input capacitance RIN Input resistance Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution – – 5 pF 1/(500fF × data clock) 1/(400fF × data clock) 1/(300fF × data clock) 1.14 – 1.26 V 2.25 – 6 MHz Reference VREFADC ADC reference voltage Conversion Rate FCLK Data clock Source is chip’s internal main oscillator. See AC Chip-Level Specifications on page 18 for accuracy S8 8-bit sample rate Data clock set to 6 MHz. Sample Rate = 0.001/ (2^Resolution/Data clock) – 23.43 – ksps S10 10-bit sample rate Data clock set to 6 MHz. Sample Rate = 0.001/ (2^Resolution/Data clock) – 5.85 – ksps RES Resolution Can be set to 8-, 9-, or 10-bit 8 – 10 bits DNL Differential nonlinearity –1 – +2 LSB DC Accuracy INL Integral nonlinearity EOFFSET Offset error EGAIN Gain error –2 – +2 LSB 0 3.20 19.20 LSB 10-bit resolution 0 12.80 76.80 LSB For any resolution –5 – +5 %FSR – 2.10 2.60 mA 8-bit resolution Power IADC Operating current PSRR Power supply rejection ratio Document Number: 001-56223 Rev. *D PSRR (VDD > 3.0 V) – 24 – dB PSRR (VDD < 3.0 V) – 30 – dB Page 16 of 35 CY8C20336H, CY8C20446H DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15. DC POR and LVD Specifications Symbol VPOR0 Description Conditions Min Typ Max Units 1.61 – 1.66 1.71 V 2.36 2.41 – 2.60 2.66 – 2.82 2.95 VPOR2 1.66 V selected in PSoC Designer VDD must be greater than or equal to 1.71 V 2.36 V selected in PSoC Designer during startup, reset from the XRES pin, or reset from watchdog. 2.60 V selected in PSoC Designer VPOR3 2.82 V selected in PSoC Designer VLVD0 2.45 V selected in PSoC Designer 2.40 2.45 2.51 VLVD1 2.71 V selected in PSoC Designer 2.64 2.71 2.78 VLVD2 2.92 V selected in PSoC Designer 2.85 2.92 2.99 VLVD3 3.02 V selected in PSoC Designer 2.95 3.02 3.09 VLVD4 3.13 V selected in PSoC Designer 3.06 3.13 3.20 VLVD5 1.90 V selected in PSoC Designer 1.84 1.90 2.32 VLVD6 1.80 V selected in PSoC Designer 1.75 1.80 1.84 VLVD7 4.73 V selected in PSoC Designer 4.62 4.73 4.83 VPOR1 V DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 16. DC Programming Specifications Symbol Description VddIWRITE Supply voltage for flash write operations IDDP Supply current during programming or verify VILP Input low voltage during programming or verify VIHP Input high voltage during programming or verify Conditions See the appropriate DC General Purpose I/O Specifications on page 13 See appropriate DC General Purpose I/O Specifications on page 13 table on pages 15 or 16 IILP Input current when applying VILP Driving internal pull-down resistor to P1 or P1 during programming or verify IIHP Input current when applying VIHP Driving internal pull-down resistor to P1 or P1 during programming or verify VOLP Output low voltage during programming or verify VOHP Output high voltage during See appropriate DC General Purpose I/O programming or verify Specifications on page 13 table on page 16. For VDD > 3 V use VOH4 in Table 5 on page 11. FlashENPB Flash write endurance Erase/write cycles per block FlashDR Flash data retention Following maximum flash write cycles; ambient temperature of 55 °C Min 1.71 Typ – Max 5.25 Units V – 5 25 mA – – VIL V VIH – – V – – 0.2 mA – – 1.5 mA – – VSS + 0.75 V VOH – VDD V 50,000 10 – 20 – – Years Notes 14. Always greater than 50 mV above VPPOR1 voltage for falling supply. 15. Always greater than 50 mV above VPPOR2 voltage for falling supply. 16. Always greater than 50 mV above VPPOR3 voltage for falling supply. 17. Always greater than 50 mV above VPPOR0 voltage for falling supply. Document Number: 001-56223 Rev. *D Page 17 of 35 CY8C20336H, CY8C20446H AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 17. AC Chip-Level Specifications Min Typ Max Units FIMO24 Symbol IMO frequency at 24-MHz setting Description Conditions 22.8 24 25.2 MHz FIMO12 IMO frequency at 12-MHz setting 11.4 12 12.6 MHz FIMO6 IMO frequency at 6-MHz setting 5.7 6.0 6.3 MHz FCPU CPU frequency 0.75 – 25.20 MHz F32K1 ILO frequency 19 32 50 kHz F32K_U ILO untrimmed frequency 13 32 82 kHz DCIMO Duty cycle of IMO 40 50 60 % DCILO ILO duty cycle SRPOWER_UP Power supply slew rate TXRST TXRST2 External reset pulse width at power-up External reset pulse width after power-up 40 50 60 % VDD slew rate during power-up – – 250 V/ms After supply voltage is valid 1 – – ms Applies after part has booted 10 – – s Note 18. The minimum required XRES pulse length is longer when programming the device (see Table 23 on page 21). Document Number: 001-56223 Rev. *D Page 18 of 35 CY8C20336H, CY8C20446H AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. AC GPIO Specifications Symbol FGPIO TRISE23 TRISE23L TRISE01 TRISE01L TFALL TFALLL Description GPIO operating frequency Conditions Normal strong mode port 0, 1 Min 0 Typ – Rise time, strong mode, Cload = 50 pF ports 2 or 3 Rise time, strong mode low supply, Cload = 50 pF, ports 2 or 3 Rise time, strong mode, Cload = 50 pF ports 0 or 1 Rise time, strong mode low supply, Cload = 50 pF, ports 0 or 1 Fall time, strong mode, Cload = 50 pF all ports Fall time, strong mode low supply, Cload = 50 pF, all ports Max Units 6 MHz for MHz 1.71 V <VDD < 2.40 V 12 MHz for 2.40 V < VDD< 5.50 V 80 ns VDD = 3.0 to 3.6 V, 10% – 90% 0 15 – – VDD = 1.71 to 3.0 V, 10% – 90% 15 – 80 ns VDD = 3.0 to 3.6 V, 10% – 90% LDO enabled or disabled VDD = 1.71 to 3.0 V, 10% – 90% LDO enabled or disabled VDD = 3.0 to 3.6 V, 10% – 90% 10 – 50 ns 10 – 80 ns 10 – 50 ns VDD = 1.71 to 3.0 V, 10% – 90% 10 – 70 ns Figure 6. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRise23 TRise01 TRise23L TRise01L Document Number: 001-56223 Rev. *D TFall TFallL Page 19 of 35 CY8C20336H, CY8C20446H Table 19.AC Characteristics – USB Data Timings Min Typ Max Units TDRATE Symbol Full-speed data rate Description Average bit rate Conditions 12 – 0.25% 12 12 + 0.25% MHz TJR1 Receiver jitter tolerance To next transition –18.5 – 18.5 ns TJR2 Receiver jitter tolerance To pair transition –9 – 9 ns TDJ1 FS driver jitter To next transition –3.5 – 3.5 ns TDJ2 FS driver jitter To pair transition –4.0 – 4.0 ns TFDEOP Source jitter for differential transition To SE0 transition –2 – 5 ns 175 TFEOPT Source SE0 interval of EOP 160 – TFEOPR Receiver SE0 interval of EOP 82 – ns TFST Width of SE0 interval during differential transition – – 14 ns Min Typ Max Units 4 – 20 ns ns Table 20. AC Characteristics – USB Driver Symbol Description Conditions TFR Transition rise time 50 pF TFF Transition fall time 50 pF TFRFM Rise/fall time matching Vcrs Output signal crossover voltage 4 – 20 ns 90 – 111 % 1.30 – 2.00 V AC Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 21. AC Low Power Comparator Specifications Symbol TLPC Description Comparator response time, 50 mV overdrive Conditions 50 mV overdrive does not include offset voltage. Min Typ Max Units – – 100 ns AC External Clock Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 22. AC External Clock Specifications Symbol FOSCEXT Min Typ Max Units Frequency (external oscillator frequency) Description 0.75 – 25.20 MHz High period 20.60 – 5300 ns Low period 20.60 – – ns 150 – – s Power-up IMO to switch Conditions Note 19. TFRFM is not met under all conditions. There is a corner case at lower supply voltages, such as those under 3.3 V. This condition does not affect USB communications. Signal integrity tests show an excellent eye diagram at 3.15 V. Document Number: 001-56223 Rev. *D Page 20 of 35 CY8C20336H, CY8C20446H AC Programming Specifications Figure 7. AC Waveform SCLK (P1) T RSCLK T FSCLK SDATA (P1) TSSCLK T HSCLK TDSCLK The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 23. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 TXRST3 Description Rise time of SCLK Fall time of SCLK Data Setup time to falling edge of SCLK Data Hold time from falling edge of SCLK Frequency of SCLK Flash erase time (Block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK External reset pulse width after power-up TXRES TVDDWAIT TVDDXRES TPOLL TACQ XRES Pulse Length VDD stable to wait-and-poll hold off VDD stable to XRES assertion delay SDATA high pulse time “Key window” time after a VDD ramp acquire event, based on 256 ILO clocks. “Key window” time after an XRES event, based on eight ILO clocks TXRESINI Document Number: 001-56223 Rev. *D Conditions 3.6 VDD 3.0 VDD 3.6 1.71 VDD 3.0 Required to enter programming mode when coming out of sleep Min 1 1 40 40 0 – – – – – 300 Typ – – – – – – – – – – – Max 20 20 – – 8 18 25 60 85 130 – Units ns ns ns ns MHz ms ms ns ns ns s 300 0.1 14.27 0.01 3.20 – – – – – – 1 – 200 19.60 s ms ms ms ms 98 – 615 s Page 21 of 35 CY8C20336H, CY8C20446H AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 24. AC Characteristics of the I2C SDA and SCL Pins Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF tSP Description SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus-free time between a STOP and START condition Pulse width of spikes are suppressed by the input filter. Standard Mode Min Max 0 100 4.0 – 4.7 4.0 4.7 0 250 4.0 4.7 – – – – 3.45 – – – – Fast Mode Units Min 0 0.6 Max 400 – kHz s 1.3 0.6 0.6 0 100 0.6 1.3 0 – – – 0.9 – – – 50 s s s s ns s s ns Figure 8. Definition for Timing for Fast/Standard Mode on the I2C Bus Note 20. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-56223 Rev. *D Page 22 of 35 CY8C20336H, CY8C20446H Table 25. SPI Master AC Specifications Symbol FSCLK Description Conditions SCLK clock frequency Min Typ Max Units VDD 2.4 V VDD < 2.4 V – – – – 6 3 MHz – 50 – % VDD 2.4 V VDD < 2.4 V 60 100 – – – – ns 40 – – ns DC SCLK duty cycle TSETUP MISO to SCLK setup time THOLD SCLK to MISO hold time TOUT_VAL SCLK to MOSI valid time – – 40 ns TOUT_H MOSI high time 40 – – ns Figure 9. SPI Master Mode 0 and 2 SPI Master, modes 0 and 2 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TSETUP MISO (input) THOLD LSB MSB TOUT_SU TOUT_H MOSI (output) Document Number: 001-56223 Rev. *D Page 23 of 35 CY8C20336H, CY8C20446H Figure 10. SPI Master Mode 1 and 3 SPI Master, modes 1 and 3 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TSETUP MISO (input) THOLD LSB MSB TOUT_SU MOSI (output) TOUT_H LSB MSB Table 26. SPI Slave AC Specifications Symbol FSCLK TLOW THIGH TSETUP THOLD TSS_MISO TSCLK_MISO TSS_HIGH TSS_CLK TCLK_SS Description SCLK clock frequency SCLK low time SCLK high time MOSI to SCLK setup time SCLK to MOSI hold time SS high to MISO valid SCLK to MISO valid SS high time Time from SS low to first SCLK Time from last SCLK to SS high Document Number: 001-56223 Rev. *D Conditions – – – – – – – – – – Min – 42 42 30 50 – – 50 2/SCLK 2/SCLK Typ – – – – – – – – – – Max 4 – – – – 153 125 – – – Units MHz ns ns ns ns ns ns ns ns ns Page 24 of 35 CY8C20336H, CY8C20446H Figure 11. SPI Slave Mode 0 and 2 SPI Slave, modes 0 and 2 TSS_HIGH TCLK_SS TSS_CLK /SS 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TOUT_H TSS_MISO MISO (output) TSETUP MOSI (input) THOLD LSB MSB Figure 12. SPI Slave Mode 1 and 3 SPI Slave, modes 1 and 3 TSS_CLK TCLK_SS /SS 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TOUT_H TSCLK_MISO TSS_MISO MISO (output) MSB TSETUP MOSI (input) Document Number: 001-56223 Rev. *D LSB THOLD MSB LSB Page 25 of 35 CY8C20336H, CY8C20446H Packaging Information This section illustrates the packaging specifications for the CY8C20336H/CY8C20446H PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Figure 13. 24-Pin (4 × 4 × 0.55 mm) QFN 001-13937 *D Document Number: 001-56223 Rev. *D Page 26 of 35 CY8C20336H, CY8C20446H Figure 14. 32-Pin (5 × 5 × 0.55 mm) QFN 001-42168 *D Figure 15. 48-Pin (7 × 7 × 1.0 mm) QFN 001-13191 *F Important Notes ■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. ■ Pinned vias for thermal conduction are not required for the low power PSoC device. Document Number: 001-56223 Rev. *D Page 27 of 35 CY8C20336H, CY8C20446H Thermal Impedances Table 27. Thermal Impedances per Package Package Typical JA  24-QFN 20.90 °C/W  19.51 °C/W  17.68 °C/W 32-QFN 48-QFN Capacitance on Crystal Pins Table 28. Typical Package Capacitance on Crystal Pins Package Package Capacitance 32-pin QFN 3.2 pF 48-pin QFN 3.3 pF Solder Reflow Peak Temperature This table lists the minimum solder reflow peak temperature to achieve good solderability. Table 29. Solder Reflow Peak Temperature Package Maximum Peak Temperature Time at Maximum Peak Temperature 24-pin QFN 260 °C 30 s 32-pin QFN 260 °C 30 s 48-pin QFN 260 °C 30 s Notes 21. TJ = TA + Power x JA. 22. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane. 23. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-56223 Rev. *D Page 28 of 35 CY8C20336H, CY8C20446H Development Tool Selection Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for over half a decade. PSoC Designer is available free of charge at http:// www.cypress.com. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC Programmer is available free of charge at http://www.cypress.com. Evaluation Tools All evaluation tools are sold at the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit enables the user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ■ MiniProg Programming Unit ■ MiniEval Socket Programming and Evaluation Board ■ 28-pin CY8C29466A-24PXI PDIP PSoC Device Sample ■ 28-pin CY8C27443A-24PXI PDIP PSoC Device Sample Development Kits ■ PSoC Designer Software CD All development kits are sold at the Cypress Online Store. ■ Getting Started Guide CY3215-DK Basic Development Kit ■ USB 2.0 Cable The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC Designer supports the advance emulation features also. The kit includes: CY3210-PSoCEval1 ■ PSoC Designer software CD ■ ICE-Cube In-Circuit Emulator ■ ICE Flex-Pod for CY8C29x66A family ■ Cat-5 adapter ■ Mini-Eval programming board ■ 110 ~ 240-V power supply, Euro-Plug adapter ■ iMAGEcraft C Compiler (Registration required) ■ ISSP cable ■ USB 2.0 cable and Blue Cat-5 cable ■ Two CY8C29466A-24PXI 28-PDIP chip samples The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ Evaluation Board with LCD Module ■ MiniProg Programming Unit ■ 28-pin CY8C29466A-24PXI PDIP PSoC Device Sample (2) ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable CY3280-20x66 Universal CapSense Controller The CY3280-20X66 CapSense Controller Kit is designed for easy prototyping and debug of CY8C20xx6A CapSense Family designs with pre-defined control circuitry and plug-in hardware. Programming hardware and an I2C-to-USB bridge are included for tuning and data acquisition. The kit includes: Document Number: 001-56223 Rev. *D ■ CY3280-20x66 CapSense Controller board ■ CY3240-I2USB bridge ■ CY3210 MiniProg1 Programmer ■ USB 2.0 retractable cable ■ CY3280-20x66 Kit CD Page 29 of 35 CY8C20336H, CY8C20446H Device Programmers ■ Getting Started Guide All device programmers are purchased from the Cypress Online Store. ■ USB 2.0 Cable CY3207ISSP In-System Serial Programmer (ISSP) CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment. Note that CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: ■ Modular Programmer Base ■ CY3207 Programmer Unit ■ Three Programming Module Cards ■ PSoC ISSP Software CD ■ MiniProg Programming Unit ■ 110 ~ 240 V Power Supply, Euro-Plug Adapter ■ PSoC Designer Software CD ■ USB 2.0 Cable Accessories (Emulation and Programming) Table 30. Emulation and Programming Accessories Part Number CY8C20336H-24LQXI CY8C20446H-24LQXI Pin Package 24-pin QFN 32-pin QFN Flex-Pod Kit CY3250-20366QFN CY3250-20466QFN Foot Kit CY3250-24QFN-FK CY3250-32QFN-FK Adapter See note 24 See note 26 Third Party Tools Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards. Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, refer Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at http://www.cypress.com/?rID2748. Notes 24. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 25. Foot kit includes surface mount feet that can be soldered to the target PCB. 26. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. 27. Dual-function digital I/O pins also connect to the common analog mux. 28. This part is available in limited quantities for in-circuit debugging during prototype development. It is not available in production volumes. Document Number: 001-56223 Rev. *D Page 30 of 35 CY8C20336H, CY8C20446H Ordering Information The following table lists the CY8C20336H/CY8C20446H PSoC devices' key package features and ordering codes. Table 31. PSoC Device Key Features and Ordering Information Package Ordering Code Flash (KB) SRAM (KB) CapSense Blocks Digital I/O Pins Analog Inputs XRES Pin USB 24-pin (4 × 4 × 0.6mm) QFN 32 pin (5 × 5 × 0.6 mm) QFN CY8C20336H-24LQXI CY8C20446H-24LQXI 8 16 1 2 1 1 20 28 20 28 Yes Yes No No 48 pin (7 × 7 mm) QFN (OCD) CY8C20066A-24LTXI 32 2 1 36 36 Yes Yes Ordering Code Definitions CY 8 C 20 XX6H- SP XXX I Temperature range: Industrial Package type: LQX/LTX: QFN Pb-free Speed: 24 MHz Part number Family code Technology code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Document Number: 001-56223 Rev. *D Page 31 of 35 CY8C20336H, CY8C20446H Document Conventions Acronyms Used Units of Measure The following table lists the acronyms that are used in this document. Table 32 lists all the abbreviations used to measure the PSoC devices. Acronym AC ADC API CMOS CPU DAC DC EOP FSR GPIO GUI I 2C ICE IDAC ILO IMO I/O ISSP LCD LDO LSB LVD MCU MIPS MISO MOSI MSB OCD POR PPOR PSRR PWRSYS PSoC® SLIMO SRAM SNR QFN SCL SDA SDATA SPI SS SSOP TC USB USB D+ USB DWLCSP XTAL Description alternating current analog-to-digital converter application programming interface complementary metal oxide semiconductor central processing unit digital-to-analog converter direct current end of packet full scale range general purpose input/output graphical user interface inter-integrated circuit in-circuit emulator digital analog converter current internal low speed oscillator internal main oscillator input/output in-system serial programming liquid crystal display low dropout (regulator) least-significant bit low voltage detect micro-controller unit mega instructions per second master in slave out master out slave in most-significant bit on-chip debugger power on reset precision power on reset power supply rejection ratio power system Programmable System-on-Chip slow internal main oscillator static random access memory signal to noise ratio quad flat no-lead serial I2C clock serial I2C data serial ISSP data serial peripheral interface slave select shrink small outline package test controller universal serial bus USB Data + USB Datawafer level chip scale package crystal Document Number: 001-56223 Rev. *D Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal. Table 32. Units of Measure Symbol °C dB fF g Hz KB Kbit KHz Ksps k MHz M A F H s W mA ms mV nA ns nV pA pF pp ppm ps sps s V W Unit of Measure degree Celsius decibels femto farad gram hertz 1024 bytes 1024 bits kilohertz kilo samples per second kilohm megahertz megaohm microampere microfarad microhenry microsecond microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts watt Page 32 of 35 CY8C20336H, CY8C20446H Glossary Crosspoint connection Connection between any GPIO combination via analog multiplexer bus. Differential non-linearity Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. Differential non-linearity is a measure of the worst case deviation from the ideal 1 LSB step. Hold time Hold time is the time following a clock event during which the data input to a latch or flipflop must remain stable in order to guarantee that the latched data is correct. I2C It is a serial multi-master bus used to connect low speed peripherals to MCU. Integral nonlinearity It is a term describing the maximum deviation between the ideal output of a DAC/ADC and the actual output level. Latch up current Current at which the latch up test is conducted according to JESD78 standard (at 125 °C) Power supply rejection ratio (PSRR) The PSRR is defined as the ratio of the change in supply voltage to the corresponding change in output voltage of the device. Scan The conversion of all sensor capacitances to digital values. Setup time Period required to prepare a device, machine, process, or system for it to be ready to function. Signal-to-noise ratio The ratio between a capacitive finger signal and system noise. SPI Serial peripheral interface is a synchronous serial data link standard. Reference Documents ■ Technical reference manual for CY8C20xx6 devices ■ In-system Serial Programming (ISSP) protocol for 20xx6 – AN2026C ■ Host Sourced Serial Programming for 20xx6 devices – AN59389 Document Number: 001-56223 Rev. *D Page 33 of 35 CY8C20336H, CY8C20446H Document History Page Document Title: CY8C20336H/CY8C20446H Haptics Enabled CapSense® Controller Document Number: 001-56223 Origin of Submission Revision ECN Description of Change Change Date ** 2787411 VZD/AESA 10/15/2009 New datasheet. *A 3016550 KEJO/KPOL 08/26/2010 Added CY8C20346H part. Updated 24-pin QFN and 32-pin QFN package diagrams. Content and format updated to match latest template. *B 3089844 JPM 11/18/10 In Table 26, modified TLOW and THIGH min values to 42. Updated TSS_HIGH min value to 50; removed max value. *C 3180479 YVA 02/23/11 Removed CY8C20346H part Changed title from CapSense Applications to Haptics Enabled CapSense Controller Updated Table 29 with Time at Maximum Temperature information *D 3638625 YLIU/BVI 06/06/2012 Updated FSCLK parameter in the SPI Slave AC Specifications table Updated Getting Started and Designing with PSoC Designer sections. Included Development Tools. Updated Software under Development Tool Selection section. Updated FSCLK parameter in the Table 26, “SPI Slave AC Specifications,” on page 24. Changed tOUT_HIGH to tOUT_H in Table 25, “SPI Master AC Specifications,” on page 23 Updated package diagrams: 001-13937 to *D 001-13191 to *F Document Number: 001-56223 Rev. *D Page 34 of 35 CY8C20336H, CY8C20446H Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2012. 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Document Number: 001-56223 Rev. *D Revised June 15, 2012 Page 35 of 35 2 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.