CY62136ESL MoBL® 2-Mbit (128 K × 16) Static RAM 2-Mbit (128 K × 16) Static RAM Features ■ Very high speed: 45 ns ■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 7 A ■ Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz ■ Easy memory expansion with CE and OE features ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Available in Pb-free 44-pin thin small outline package (TSOP) II package Functional Description The CY62136ESL is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 11 for a complete description of read and write modes. Logic Block Diagram 128 K x 16 RAM Array SENSE AMPS ROW DECODER DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0–I/O7 I/O8–I/O15 Cypress Semiconductor Corporation Document #: 001-48147 Rev. *D • BHE WE CE OE BLE A13 A14 A15 A16 A11 A12 COLUMN DECODER 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 15, 2011 [+] Feedback CY62136ESL MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Document #: 001-48147 Rev. *D Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagram ............................................................ 13 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15 Page 2 of 15 [+] Feedback CY62136ESL MoBL® Pin Configuration Figure 1. 44-pin TSOP II (Top View) [1] A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Product Portfolio Power Dissipation Product CY62136ESL Range VCC Range (V) [2] Industrial 2.2 V to 3.6 V and 4.5 V to 5.5 V Speed (ns) 45 Operating ICC, (mA) f = 1MHz f = fmax Standby, ISB2 (A) Typ [3] Max Typ [3] Max Typ [3] Max 2 2.5 15 20 1 7 Notes 1. NC pins are not connected on the die. 2. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C. Document #: 001-48147 Rev. *D Page 3 of 15 [+] Feedback CY62136ESL MoBL® Maximum Ratings Output current into outputs (LOW) ............................. 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Static discharge voltage ........................................... >2001 V (MIL-STD-883, Method 3015) Latch up current ..................................................... > 200 mA Operating Range Device Supply voltage to ground potential ................–0.5 V to 6.0 V DC voltage applied to outputs in High Z State [4, 5] ........................................–0.5 V to 6.0 V CY62136ESL Range Ambient Temperature VCC[6] Industrial –40 °C to +8 5 °C 2.2 V–3.6 V, and 4.5 V–5.5 V DC input voltage[4, 5] ......................................–0.5 V to 6.0 V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Test Conditions 45 ns Min Typ [7] Max 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 – – 2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 – – 4.5 < VCC < 5.5 IOH = –1.0 mA 2.4 – – 2.2 < VCC < 2.7 IOL = 0.1 mA – – 0.4 2.7 < VCC < 3.6 IOL = 2.1 mA – – 0.4 4.5 < VCC < 5.5 IOL = 2.1 mA – – 0.4 2.2 < VCC < 2.7 1.8 – VCC + 0.3 2.7 < VCC < 3.6 2.2 – VCC + 0.3 4.5 < VCC < 5.5 2.2 – VCC + 0.5 2.2 < VCC < 2.7 –0.3 – 0.6 2.7 < VCC < 3.6 –0.3 – 0.8 4.5 < VCC < 5.5 –0.5 – 0.8 Unit V V V V IIX Input leakage current –1 – +1 A IOZ Output leakage current GND < VO < VCC, Output disabled –1 – +1 A ICC VCC Operating supply current – 15 20 mA – 2 2.5 – 1 7 A – 1 7 A ISB1[8] ISB2[8] GND < VI < VCC f = fmax = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA, CMOS levels Automatic CE CE > VCC 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, power-down current — f = fmax (Address and data only), CMOS inputs f = 0 (OE, BHE, BLE and WE), VCC = VCC(max) Automatic CE CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, power-down current — f = 0, VCC = VCC(max) CMOS inputs Notes 4. VIL(min) = –2.0 V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C. 8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 001-48147 Rev. *D Page 4 of 15 [+] Feedback CY62136ESL MoBL® Capacitance Parameter [9] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Thermal Resistance Parameter [9] Description JA Thermal resistance (Junction to ambient) JC Thermal resistance (Junction to case) Test Conditions 44-pin TSOP II Unit Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 77 C/W 13 C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE VCC R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V TH Parameters 2.5 V 3.0 V 5.0 V Unit R1 16667 1103 1800 R2 15385 1554 990 RTH 8000 645 639 VTH 1.20 1.75 1.77 V Note 9. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-48147 Rev. *D Page 5 of 15 [+] Feedback CY62136ESL MoBL® Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ [10] Max Unit 1.0 – – V – 0.8 3 A VDR VCC for data retention ICCDR[11] Data retention current tCDR [12] Chip deselect to data retention time 0 – – ns tR [13] Operation recovery time 45 – – ns CE > VCC – 0.2 V, VCC = 1.0 V VIN > VCC – 0.2 V or VIN < 0.2 V Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.0 V VCC(min) tR CE Notes 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating. 12. Tested initially and after any design or process changes that may affect these parameters. 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document #: 001-48147 Rev. *D Page 6 of 15 [+] Feedback CY62136ESL MoBL® Switching Characteristics Over the Operating Range Parameter [14, 15] Description 45 ns Min Max Unit Read Cycle tRC Read cycle time 45 – ns tAA Address to data valid – 45 ns tOHA Data hold from address change 10 – ns tACE CE LOW to data valid – 45 ns tDOE OE LOW to data valid – 22 ns ns [16] tLZOE OE LOW to Low Z 5 – tHZOE OE HIGH to High Z [16, 17] – 18 ns tLZCE CE LOW to Low Z [16] 10 – ns – 18 ns ns tHZCE CE HIGH to High Z [16, 17] tPU CE LOW to power-up 0 – tPD CE HIGH to ower-down – 45 ns tDBE BLE/BHE LOW to data valid – 22 ns [16] 5 – ns – 18 ns 45 – ns tLZBE tHZBE BLE/BHE LOW to Low Z BLE/BHE HIGH to High Z [16, 17] Write Cycle [18] tWC Write cycle time tSCE CE LOW to write end 35 – ns tAW Address setup to write end 35 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 35 – ns ns tBW BLE/BHE LOW to write end 35 – tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns – 18 ns 10 – ns tHZWE tLZWE WE LOW to High Z [16, 17] WE HIGH to Low Z [16] Notes 14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3 V, and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5. 15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 001-48147 Rev. *D Page 7 of 15 [+] Feedback CY62136ESL MoBL® Switching Waveforms Figure 4. Read Cycle No.1: Address Transition Controlled [19, 20] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2: OE Controlled [20, 21] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB Notes 19. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 20. WE is HIGH for read cycle. 21. Address valid before or similar to CE, BHE, BLE transition LOW. Document #: 001-48147 Rev. *D Page 8 of 15 [+] Feedback CY62136ESL MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No 1: WE Controlled [22, 23, 24] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA I/O tSD tHD DATAIN NOTE 25 tHZOE Figure 7. Write Cycle 2: CE Controlled [22, 23, 24] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN NOTE 25 tHZOE Notes 22. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write. 23. Data I/O is high impedance if OE = VIH. 24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 25. During this period, the I/Os are in output state. Do not apply input signals. Document #: 001-48147 Rev. *D Page 9 of 15 [+] Feedback CY62136ESL MoBL® Switching Waveforms (continued) Figure 8. Write Cycle 3: WE Controlled, OE LOW [26] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA WE tPWE tSD DATA I/O NOTE 27 tHD DATAIN tLZWE tHZWE Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW [26] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA I/O NOTE 27 tSD tHD DATAIN tLZWE Notes 26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 27. During this period, the I/Os are in output state. Do not apply input signals. Document #: 001-48147 Rev. *D Page 10 of 15 [+] Feedback CY62136ESL MoBL® Truth Table CE [28] H WE OE X X BHE BLE [28] [28] X X Inputs/Outputs High Z Mode Deselect/power-down Power Standby (ISB) L X X H H High Z Output disabled Active (ICC) L H L L L Data out (I/O0–I/O15) Read Active (ICC) L H L H L Data out (I/O0–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data out (I/O8–I/O15); I/O0–I/O7 in High Z Read Active (ICC) L H H L L High Z Output disabled Active (ICC) L H H H L High Z Output disabled Active (ICC) L H H L H High Z Output disabled Active (ICC) L L X L L Data in (I/O0–I/O15) Write Active (ICC) L L X H L Data in (I/O0–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data in (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) Note 28. The ‘X’ (Don’t care) state for the Chip enable (CE) and Byte enables (BHE and BLE) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document #: 001-48147 Rev. *D Page 11 of 15 [+] Feedback CY62136ESL MoBL® Ordering Information Speed (ns) 45 Package Diagram Ordering Code CY62136ESL-45ZSXI Package Type 51-85087 44-pin TSOP Type II (Pb-free) Operating Range Industrial Ordering Code Definitions CY 621 3 6 E SL - 45 ZS X I Temperature Grade: I = Industrial Pb-free Package Type: ZS = 44-pin TSOP II Speed Grade: 45 ns Wide Voltage Range (3 V and 5 V) Process Technology: 90 nm Bus width = × 16 Density = 2-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document #: 001-48147 Rev. *D Page 12 of 15 [+] Feedback CY62136ESL MoBL® Package Diagram Figure 10. 44-pin TSOP Z44-II, 51-85087 PIN 1 I.D. 11.938 (0.470) 11.735 (0.462) 10.262 (0.404) 10.058 (0.396) 1 22 Z Z Z Z X Z AA 44 23 BOTTOM VIEW TOP VIEW 0.400(0.016) 0.300 (0.012) 0.800 BSC (0.0315) EJECTOR MARK (OPTIONAL) CAN BE LOCATED ANYWHERE IN THE BOTTOM PKG BASE PLANE 10.262 (0.404) 10.058 (0.396) 0.10 (.004) 18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) 0.210 (0.0083) 0.120 (0.0047) 0°-5° SEATING PLANE 0.597 (0.0235) 0.406 (0.0160) DIMENSION IN MM (INCH) MAX MIN. Acronyms Acronym 51-85087 *C Document Conventions Description Units of Measure BLE byte low enable BHE byte high enable °C degree Celsius CE chip enable MHz Mega Hertz CMOS complementary metal oxide semiconductor A micro Amperes I/O input/output s micro seconds OE output enable mA milli Amperes SRAM static random access memory mm milli meter TSOP thin small outline package ns nano seconds WE write enable % percent pF pico Farads ohms V Volts W Watts Document #: 001-48147 Rev. *D Symbol Unit of Measure Page 13 of 15 [+] Feedback CY62136ESL MoBL® Document History Page Document Title: CY62136ESL MoBL®, 2-Mbit (128 K × 16) Static RAM Document Number: 001-48147 Rev. ECN No. Orig. of Change Submission Date ** 2615537 VKN/PYRS 12/03/08 Description of Change New Data Sheet *A 2718906 VKN 06/15/2009 Post to external web *B 2944332 VKN 06/04/2010 Added Contents Added footnote for ISB2 parameter in Electrical Characteristics Added Footnote 2 in Switching Characteristics Added footnote related to Chip enable and Byte enables in Truth Table Updated Package Diagram Updated links in Sales, Solutions, and Legal Information *C 3126445 RAME 01/03/2011 Updated datasheet as per new template Added Acronyms and Units of Measure. Added Ordering Code Definitions Converted all table note to footnote. *D 3283711 RAME 06/15/2011 Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Updated in new template. Document #: 001-48147 Rev. *D Page 14 of 15 [+] Feedback CY62136ESL MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-48147 Rev. *D Revised June 15, 2011 Page 15 of 15 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback