AEC Q100 Grade 1 Compliant FM25040B – Automotive Temp. 4Kb Serial 5V F-RAM Memory Features 4K bit Ferroelectric Nonvolatile RAM Organized as 512 x 8 bits High Endurance 10 Trillion (1013) Read/Writes NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Sophisticated Write Protection Scheme Hardware Protection Software Protection Low Power Consumption 10 A Standby Current (+85C) Fast Serial Peripheral Interface - SPI Up to 14 MHz maximum Bus Frequency Direct hardware replacement for EEPROM SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Industry Standard Configuration Automotive Temperature -40C to +125C o Qualified to AEC Q100 Specification “Green”/RoHS 8-pin SOIC Description Pin Configuration The FM25040B is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM25040B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte has been transferred to the device. The next bus cycle may commence without the need for data polling. The FM25040B is capable of supporting 1013 read/write cycles, or 10 million times more write cycles than EEPROM. These capabilities make the FM25040B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25040B provides substantial benefits to users of serial EEPROM, in a hardware drop-in replacement. The FM25040B uses the high-speed SPI bus which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over the automotive temperature range of -40°C to +125°C. CS SO WP 1 8 2 7 3 6 VSS 4 5 Pin Names /CS /WP /HOLD SCK SI SO VDD VSS VDD HOLD SCK SI Function Chip Select Write Protect Hold Serial Clock Serial Data Input Serial Data Output Supply Voltage 5V Ground Ordering Information FM25040B-GA “Green”/RoHS 8-pin SOIC, Automotive Grade 1 FM25040B-GATR “Green” /RoHS 8-pin SOIC, Automotive Grade 1, Tape & Reel This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Cypress Semiconductor Corporation • Document Number: 001-86151 Rev. ** 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 25, 2013 FM25040B - Automotive Temp. WP Instruction Decode Clock Generator Control Logic Write Protect CS HOLD SCK 64 x 64 FRAM Array Instruction Register Address Register Counter 9 SI 8 Data I/O Register SO 2 Nonvolatile Status Register Figure 1. Block Diagram Pin Descriptions Pin Name /CS I/O Input SCK Input /HOLD Input /WP Input SI Input SO Output VDD VSS Supply Supply Description Chip Select. This active-low input activates the device. When high, the device enters lowpower standby mode, ignores other inputs, and all outputs are tri-stated. When low, the device internally activates the SCK signal. A falling edge on /CS must occur prior to every op-code. Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, the clock frequency may be any value between 0 and 14 MHz and may be interrupted at any time. Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for another task. When /HOLD is low, the current operation is suspended. The device ignores any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low. Write Protect: This active-low pin prevents all write operations, including those to the Status Register. If high, write access is determined by the other write protection features, as controlled through the Status Register. A complete explanation of write protection is provided on page 6. Serial Input: All input data is driven to this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. * SI may be connected to SO for a single pin data interface. Serial Output: SO is the data output pin. It is driven actively during a read and remains tristate at all other times including when /HOLD is low. Data transitions are driven on the falling edge of the serial clock. * SO can be connected to SI for a single pin data interface since the part communicates in half-duplex fashion. Supply Voltage: 5V Ground Document Number: 001-86151 Rev. ** Page 2 of 14 FM25040B - Automotive Temp. Overview Serial Peripheral Interface – SPI Bus The FM25040B is a serial FRAM memory. The memory array is logically organized as 512 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25040B and a serial EEPROM with the same pin-out relates to its superior write performance. The FM25040B differs from Ramtron’s FM25040 by increasing its performance to 14MHz and adding support for SPI Mode 3. This makes the FM25040B a drop-in replacement for most 4Kb SPI EEPROMs that support Modes 0 & 3. The FM25040B employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 14 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25040B operates in SPI Mode 0 and 3. Memory Architecture When accessing the FM25040B, the user addresses 512 locations each with 8 data bits. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code including the upper address bit, and a word address. The word address consists of the lower 8-address bits. The complete address of 9-bits specifies each byte address uniquely. Most functions of the FM25040B either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation essentially is zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section that follows. Users expect several obvious system benefits from the FM25040B due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25040B contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip enable active. Document Number: 001-86151 Rev. ** The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25040B devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25040B device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off (high) the /HOLD pin. Figure 3 shows a configuration that uses only three pins. Protocol Overview The SPI interface is a synchronous serial interface using clock and data lines. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25040B will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25040B supports Modes 0 and 3. Figure 4 shows the required signal relationships for Modes 0 and 3. For both modes, data is clocked into the FM25040B on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the part. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS must go inactive (high) after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select. Page 3 of 14 FM25040B - Automotive Temp. SCK MOSI MISO SO SPI Microcontroller SI SCK SO SI SCK FM25040B FM25040B CS CS HOLD HOLD SS1 SS2 HOLD1 HOLD2 MOSI: Master Out, Slave In MISO: Master In, Slave Out SS: Slave Select Figure 2. System Configuration with SPI port SO Microcontroller SI SCK FM25040B CS HOLD Figure 3. System Configuration without SPI port SPI Mode 0: CPOL=0, CPHA=0 7 6 5 4 3 2 1 0 SPI Mode 3: CPOL=1, CPHA=1 7 6 5 4 3 2 1 0 Figure 4. SPI Modes 0 & 3 Document Number: 001-86151 Rev. ** Page 4 of 14 FM25040B - Automotive Temp. Data Transfer All data transfers to and from the FM25040B occur in 8-bit groups. They are synchronized to the clock signal (SCK) and they transfer most significant bit (MSB) first. The serial input data is clocked in on the rising edge of SCK. The serial data output is driven from the falling edge of SCK. Command Structure There are six commands called op-codes that can be issued by the bus master to the FM25040B. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent data transfer. They perform a single function, such as, enabling a write operation. Second are commands followed by one byte, either in or out. They operate on the Status Register. Third are commands for memory transactions followed by address and one or more bytes of data. Table 1. Op-code Commands Name Description Set Write Enable Latch WREN Write Disable WRDI Read Status Register RDSR Write Status Register WRSR Read Memory Data READ WRITE Write Memory Data Op-code 0000_0110b 0000_0100b 0000_0101b 0000_0001b 0000_A011b 0000_A010b WREN - Set Write Enable Latch The FM25040B will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the Status Register and writing the memory. Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the Status Register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. A write to the Status Register has no effect on the WEL bit. Completing any write operation will automatically clear the write-enable latch and prevent further writes without another WREN command. Figure 5 below illustrates the WREN command bus configuration. WRDI - Write Disable The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the Status Register and verifying that WEL=0. Figure 6 illustrates the WRDI command bus configuration. Figure 5. WREN Bus Configuration Figure 6. WRDI Bus Configuration Document Number: 001-86151 Rev. ** Page 5 of 14 FM25040B - Automotive Temp. RDSR - Read Status Register The RDSR command allows the bus master to verify the contents of the Status Register. Reading Status provides information about the current state of the write protection features. Following the RDSR opcode, the FM25040B will return one byte with the contents of the Status Register. The Status Register is described in detail in the Status Register & Write Protection section. WRSR – Write Status Register The WRSR command allows the user to select certain write protection features by writing a byte to the Status Register. Prior to issuing a WRSR command, the /WP pin must be high or inactive. Note that on the FM25040B, /WP prevents writing to the Status Register and the memory array. Prior to sending the WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR command is a write operation and therefore clears the Write Enable Latch. The bus timing for RDSR and WRSR are shown below. Figure 7. RDSR Bus Timing Figure 8. WRSR Bus Timing (WREN not shown) Status Register & Write Protection The write protection features of the FM25040B are multi-tiered. First, a WREN op-code must be issued prior to any write operation. Assuming that writes are enabled using WREN, writes to memory are controlled by the /WP pin and the Status Register. When /WP is low, the entire part is write-protected. When /WP is high, the memory protection is subject to the Status register. Writes to the Status Register are performed using the WREN and WRSR commands and subject to the /WP pin. The Status Register is organized as follows. Table 2. Status Register Bit Name 7 0 6 0 5 0 4 0 3 BP1 2 BP0 1 WEL 0 0 Bits 0 and 4-7 are fixed at 0 and cannot be modified. Note that bit 0 (/RDY in EEPROMs) is wired low since FRAM writes have no delay and the memory is never busy. All EEPROMs use Ready to indicate Document Number: 001-86151 Rev. ** whether a write cycle is complete or not. The BP1 and BP0 bits control write protection features. They are nonvolatile (shaded yellow). The WEL flag indicates the state of the Write Enable Latch. This bit is internally set by the WREN command and is cleared by terminating a write cycle (/CS high) or by using the WRDI command. BP1 and BP0 are memory block write protection bits. They specify portions of memory that are writeprotected as shown in the following table. Table 3. Block Memory Write Protection BP1 BP0 Protected Address Range 0 0 1 1 0 1 0 1 None 180h to 1FFh (upper ¼) 100h to 1FFH (upper ½) 000h to 1FFh (all) Page 6 of 14 FM25040B - Automotive Temp. The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits. Table 4. Write Protection WEL /WP Protected Blocks 0 X Protected 1 0 Protected 1 1 Protected The BP1 and BP0 bits allow software to selectively write protect the array. These settings are only used when the /WP pin is inactive and the WREN command has been issued. The following table summarizes the write protection conditions. Unprotected Blocks Protected Protected Unprotected Status Register Protected Protected Unprotected Memory Operation The SPI interface, with its relatively high maximum clock frequency, highlights the fast write capability of the FRAM technology. Unlike SPI-bus EEPROMs, the FM25040B can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code. The bus master then issues a WRITE opcode. Part of this op-code includes the upper bit of the memory address. Bit 3 in the op-code corresponds to A8. The next byte is the lower 8-bits of the address A7-A0. In total, the 9-bits specify the address of the first byte of the write operation. Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFh is reached, the counter will roll over to 000h. Data is written MSB first. Unlike EEPROMs, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8th clock). The rising edge of /CS terminates a WRITE op-code operation. Document Number: 001-86151 Rev. ** Read Operation After the falling edge of /CS, the bus master can issue a READ op-code. Part of this op-code includes the upper bit of the memory address. The next byte is the lower 8-bits of the address. In total, the 9-bits specify the address of the first byte of the read operation. After the op-code is complete, the SI pin is ignored. The bus master then issues 8 clocks, with one bit read out for each. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFh is reached, the counter will roll over to 000h. Data is read MSB first. The rising edge of /CS terminates a READ op-code operation.. The bus configuration for read and write operations is shown below. Hold The /HOLD pin can be used to interrupt a serial operation without aborting it. If the bus master takes the /HOLD pin low while SCK is low, the current operation will pause. Taking the /HOLD pin high while SCK is low will resume an operation. The transitions of /HOLD must occur while SCK is low, but the SCK pin can toggle during a hold state. Page 7 of 14 FM25040B - Automotive Temp. CS 0 1 2 3 4 5 6 7 0 1 0 1 0 7 6 2 3 4 5 6 7 0 1 2 3 4 5 6 Byte Address 5 4 3 2 1 0 7 6 5 Data 4 3 2 1 7 7 0 0 SCK op-code SI 0 0 0 0 A MSB SO LSB MSB LSB Hi-Z Figure 9. Memory Write (WREN not shown) CS 0 1 2 0 0 0 3 4 5 6 7 0 1 0 1 1 7 6 2 3 4 5 6 Byte Address 5 4 3 2 1 7 0 1 2 3 4 5 6 7 7 7 6 MSB 5 Data Out 4 3 2 1 0 LSB 0 LSB SCK op-code SI 0 A MSB SO Hi-Z 0 LSB Figure 10. Memory Read Endurance The FM25040B devices are capable of being accessed at least 1013 times, reads or writes. An FRAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns. Rows are defined by A8-A3 and column addresses by A2-A0. See Block Diagram (pg 2) which shows the array as 64 rows of 64-bits each. The entire row is internally accessed once whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. The table below shows endurance calculations for 64-byte repeating loop, which includes an op-code, a starting address, and a sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop. F-RAM read and write endurance is virtually unlimited even at 10MHz clock rate. Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop SCK Freq Endurance Endurance Years to Reach (MHz) Cycles/sec. Cycles/year Limit 10 18,660 5.88 x 1011 17.0 5 9,330 2.94 x 1011 34.0 1 1,870 5.88 x 1010 170.1 Document Number: 001-86151 Rev. ** Page 8 of 14 FM25040B - Automotive Temp. Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any pin with respect to VSS TSTG TLEAD VESD Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) Package Moisture Sensitivity Level Ratings -1.0V to +7.0V -1.0V to +7.0V and VIN < VDD+1.0V -55C to + 125C 260 C 3.5kV 1.25kV 250V MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to +125 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 4.5 5.0 5.5 V IDD VDD Supply Current 1 @ SCK = 1.0 MHz 0.3 mA @ SCK = 14.0 MHz 3.0 mA ISB Standby Current 2 10 @ +85C A 30 @ +125C A ILI Input Leakage Current 3 1 A ILO Output Leakage Current 3 1 A VIH Input High Voltage 0.75 VDD VDD + 0.3 V VIL Input Low Voltage -0.3 0.25 VDD V VOH Output High Voltage VDD – 0.8 V @ IOH = -1 mA VOL Output Low Voltage 0.4 V @ IOL = 2 mA VHYS Input Hysteresis 0.05 VDD V 4 Notes 1. 2. 3. 4. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. SCK = SI = /CS=VDD. All inputs VSS or VDD. VIN or VOUT = VSS to VDD. Characterized but not 100% tested in production. Applies only to /CS and SCK pins. Document Number: 001-86151 Rev. ** Page 9 of 14 FM25040B - Automotive Temp. AC Parameters Symbol fCK tCH tCL tCSU tCSH tOD tODV tOH tD tR tF tSU tH tHS tHH tHZ tLZ Notes 1. 2. 3. (TA = -40 C to +125 C, VDD = 4.5V to 5.5V unless otherwise specified) Parameter Min Max SCK Clock Frequency 0 14 Clock High Time 30 Clock Low Time 30 Chip Select Setup 10 Chip Select Hold 10 Output Disable 25 Output Data Valid 30 Output Hold 0 Deselect Time 80 Data In Rise Time 50 Data In Fall Time 50 Data Setup Time 5 Data Hold Time 5 /Hold Setup Time 10 /Hold Hold Time 10 /Hold Low to Hi-Z 25 /Hold High to Data Active 25 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 2 2,3 2,3 2 2 tCH + tCL = 1/fCK. This parameter is characterized and not 100% tested. Rise and fall times measured between 10% and 90% of waveform. Capacitance (TA = 25C , f=1.0 MHz, VDD = 5V) Symbol Parameter Max CO Output Capacitance (SO) 8 CI Input Capacitance 6 Notes 1. This parameter is periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels Input rise and fall times 10% and 90% of VDD 5 ns Units pF pF Input and output timing levels Output Load Capacitance Notes 1 1 0.5 VDD 30 pF Power Cycle Timing VDD VDD min tVF tVR tPU tPD CS Power Cycle Timing (TA = -40 C to +125 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units VDD(min) to First Access Start 1 ms tPU Last Access Complete to VDD(min) 0 tPD s VDD Rise Time 30 tVR s/V VDD Fall Time 20 tVF s/V Notes 1. Slope measured at any point on VDD waveform. Document Number: 001-86151 Rev. ** Notes 1 1 Page 10 of 14 FM25040B - Automotive Temp. Serial Data Bus Timing /Hold Timing Data Retention (VDD = 4.5V to 5.5V) Parameter Min Max Units Notes Data Retention 17 Years @ TA = +55C 10,000 Hours @ TA = +105C 1,000 Hours @ TA = +125C Note : Data retention qualification tests are accelerated tests and are performed such that all three conditions have been applied : (1) 17 years at a temperature of +55C, (2) 10,000 hours at +105C, and (3) 1,000 hours at +125C. Typical Grade 1 Operating Profile Typical Grade 1 Storage Profile 1600 25000 1400 20000 1000 Hours Hours 1200 800 600 400 15000 10000 5000 200 0 0 70 75 80 85 90 95 100 105 110 115 120 125 Temperature (°C) Document Number: 001-86151 Rev. ** 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Temperature (°C) Page 11 of 14 FM25040B - Automotive Temp. Mechanical Drawing (8-pin SOIC - JEDEC Standard MS-012, Variation AA) Recommended PCB Footprint 7.70 3.90 ±0.10 3.70 6.00 ±0.20 2.00 0.65 1.27 Pin 1 4.90 ±0.10 1.27 0.33 0.51 0.25 0.50 1.35 1.75 0.10 0.25 0.19 0.25 45 0.10 mm 0-8 0.40 1.27 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme XXXXXXXPT LLLLLLL RICYYWW Legend: XXXXXX= part number, P= package type (G=SOIC), T= temp (A= Automotive, blank=ind.) R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM25040B, “Green” SOIC, Automotive Temperature, Rev A, Lot L3502G1, Year 2011, Work Week 04 FM25040BGA AL3502G1 RIC1104 Document Number: 001-86151 Rev. ** Page 12 of 14 FM25040B - Automotive Temp. Revision History Revision 1.0 3.0 3.1 Date 2/18/2011 10/26/2011 3/31/2012 Summary Initial release. Changed to Production status. Improved tPU and tVF specs. Document History Document Title: FM25040B 4Kb Serial 5V F-RAM Memory (Automotive Temp) Document Number: 001-86151 Revision ECN Orig. of Change Submission Date ** 3912930 GVCH 02/25/2013 Document Number: 001-86151 Rev. ** Description of Change New Spec Page 13 of 14 FM25040B - Automotive Temp. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Automotive cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks Interface cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Cypress Developer Community Memory cypress.com/go/memory Community | Forums | Blogs | Video | Training PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch Technical Support USB Controllers cypress.com/go/usb cypress.com/go/support psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 RAMTRON is a registered trademark and NoDelay™ is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2011-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-86151 Rev. ** Page 14 of 14