W42C31-03 Spread Spectrum Frequency Timing Generator Features • Maximized EMI suppression using Cypress’s Spread Spectrum technology • Generates a spread spectrum copy of the provided input • Integrated loop filter components • Operates with a 5V supply • Low power CMOS design • Available in 8-pin SOIC (Small Outline Integrated Circuit) Overview The W42C31-03 incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation. Table 1. Frequency Spread Selection W42C31-03 FS1 FS0 Oscillator Input Frequency (MHz) 0 0 10 to 20 10 to 20 fIN ±1.875% 0 1 10 to 20 10 to 20 fIN ±1.0% 1 0 20 to 33 20 to 25 fIN ±1.875% 1 1 20 to 33 20 to 25 fIN –2.0% Simplified Block Diagram XTAL Input Frequency (MHz) Output Frequency (MHz) Pin Configuration 5.0V SOIC X2 W42C31-03 X1 X2 GND FS0 Spread Spectrum Output (EMI suppressed) W42C31-03 X1 XTAL Input 1 2 3 4 8 7 6 5 OE# FS1 VDD CLKOUT 5.0V Oscillator or Reference Input W42C31-03 Cypress Semiconductor Corporation Spread Spectrum Output (EMI suppressed) • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 September 28, 1999, rev. ** W42C31-03 Pin Definitions Pin No. Pin Type CLKOUT 5 O Output Modulated Frequency: Frequency modulated copy of the unmodulated input clock X1 1 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. X2 2 I Crystal Connection: If using an external reference, this pin must be left unconnected. OE# 8 I Output Enable (Active LOW): This pin three-states the output when HIGH. It has an internal pull-down resistor. FS0 4 I Frequency Selection Bit 0: This pin selects the frequency spreading characteristics. Refer to Table 1. This pin has a pull-up resistor. FS1 7 I Frequency Selection Bit 1: This pin selects the frequency range. Refer to Table 1. This pin has a pull-up resistor. VDD 6 P Power Connection: Connected to 5V power supply. GND 3 G Ground Connection: This should be connected to the common ground plane. Pin Name Pin Description Functional Description Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed, the modulation percentage may be varied. The W42C31-03 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. An on-chip crystal driver causes the crystal to oscillate at its fundamental. The resulting reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. The unique feature of the Spread Spectrum Clock Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Using frequency select bits (FS1:0 pins), various spreading percentages can be chosen (see Table 1). A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between ±0.5% and ±2.5% are most common. The W42C31 features the ability to select from various spread spectrum characteristics. Selections specific to the W42C31-03 are shown in Table 1. Other spreading characteristics are available (see separate data sheets) or can be created with a custom mask. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. VDD X1 CLKOUT XTAL X2 Freq. Divider Q Phase Detector Charge Pump Σ VCO Modulating Waveform Crystal load capacitors as needed Feedback Divider P PLL GND Figure 1. System Block Diagram 2 Post Dividers W42C31-03 Spread Spectrum Frequency Timing Generation 5dB/div The benefits of using Spread Spectrum Frequency Timing Generation are depicted in Figure 2. An EMI emission profile of a clock harmonic is shown. SSFTG Amplitude (dB) Contrast the typical clock EMI with the Cypress Spread Spectrum Frequency Timing Generation EMI. Notice the spike in the typical clock. This spike can make systems fail quasi-peak EMI testing. The FCC and other regulatory agencies test for peak emissions. With spread spectrum enabled, the peak energy is much lower (at least 8 dB) because the energy is spread out across a wider bandwidth. Typical Clock Modulating Waveform The shape of the modulating waveform is critical to EMI reduction. The modulation scheme used to accomplish the maximum reduction in EMI is shown in Figure 3. The period of the modulation is shown as a percentage of the period length along the X axis. The amount that the frequency is varied is shown along the Y axis, also shown as a percentage of the total frequency spread. Cypress frequency selection tables express the modulation percentage in two ways. The first method displays the spreading frequency band as a percent of the programmed average output frequency, symmetric about the programmed average frequency. This method is always shown using the expression fCenter ± XMOD% in the frequency spread selection table. Figure 2. Typical Clock and SSFTG Comparison OE# Pin Time Figure 3. Modulation Waveform Profile 3 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% An internal pull-down resistor defaults the chip into a mode in which all outputs are active. If OE# goes HIGH, all outputs are three-stated. The chip will not prevent short cycles in a transition from three-state to enabled. 90% 80% 70% 60% 50% 40% 30% 20% 100% 80% 60% 40% 20% 0% –20% –40% –60% –80% –100% 10% Frequency Shift The second approach is to specify the maximum operating frequency and the spreading band as a percentage of this frequency. The output signal is swept from the lower edge of the band to the maximum frequency. The expression for this approach is fMAX – XMOD%. Whenever this expression is used, Cypress has taken care to ensure that fMAX will never be exceeded. This is important in applications where the clock drives components with tight maximum clock speed specifications. W42C31-03 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 0.5 W TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias PD Power Dissipation DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10% Parameter Description Test Condition IDD Supply Current tON Power Up Time VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current Note 1 Min Typ Max Unit 18 32 mA 5 ms 0.15VDD V First locked clock cycle after Power Good 0.7VDD V 0.4 2.5 IIH Input High Current Note 1 Output Low Current IOH Output High Current @ 0.4V, VDD = 5V @ 2.4V, VDD = 5V CI Input Capacitance All pins except X1, X2 CL Load Capacitance (as seen by XTAL) RP ZOUT V –100 IOL V 10 Pins X1, X2 µA 24 mA 24 mA 7  µA pF 17 pF Input Pull-Up Resistor 500 kΩ Clock Output Impedance 20 Ω AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 5V±10% Symbol Parameter Test Condition Min Typ Max Unit 10 33 MHz 10 33 MHz fIN Input Frequency fOUT Output Frequency tR Output Rise Time VDD, 15-pF load 0.8–2.4 2 5 ns tF Output Fall Time VDD, 15-pF load 2.4–0.8 2 5 ns tOD Output Duty Cycle 15-pF load 45 55 % tID Input Duty Cycle 40 60 % tJCYC Jitter, Cycle-to-Cycle 300 ps Input Clock Harmonic Reduction 8 dB Notes: 1. Inputs FS1:0 have a pull-up resistor; Input OE# has a pull-down resistor. 2. Pins X1 and X2 each have a 34-pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 17 pF. If driving X1 with a reference clock signal, the load capacitance will be 34 pF (typical). 4 W42C31-03 The 10-µF decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. Application Information Recommended Circuit Configuration The 6-pF XTAL load capacitors can be used to raise the integrated 17-pF capacitance up to a total load of 20 pF on the crystal. For optimum performance in system applications the power supply decoupling scheme shown in Figure 4 should be used. VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1-µF decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. 2 XTAL1 GND 3 4 W42C31-03 1 C1 6 pF Recommended Board Layout Figure 5 shows a recommended 2-layer board layout. 8 7 6 VDD 5 Output R1 C2 6 pF C3 0.1 µF 5V System Supply FB C4 10 µF Tantalum Figure 4. Recommended Circuit Configuration C1, C2 = Optional Guard Ring for XTAL Oscillator Circuitry G C3 = High frequency supply decoupling capacitor (0.1-µF recommended). C4 = Common supply low frequency decoupling capacitor (10-µF tantalum recommended). R1 = Match value to line impedance FB C1 G G XTAL1 = = Via To GND Plane G G R1 G Clock Output C4 G Power Supply Input (5V) FB Figure 5. Recommended Board Layout (2-Layer Board) Ordering Information W42C31 Ferrite Bead C3 C2 Ordering Code XTAL load capacitors (optional; use is not required for operation). Typical value is 6 pF. Freq. Mask Code Package Name Package Type 03 G 8-pin Plastic SOIC (150-mil) Document #: 38-00802 5 W42C31-03 Package Diagram 8-Pin Small Outline Integrated Circuit (SOIC, 150-mil) © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.