CY7C194BN 256 Kb (64 K × 4) Static RAM 256 Kb (64 K × 4) Static RAM Features General Description ■ Fast access time: 15 ns ■ Wide voltage range: 5.0 V ± 10% (4.5 V to 5.5 V) ■ Complementary metal oxide semiconductor (CMOS) for optimum speed/power ■ Transistor transistor logic (TTL) compatible inputs and outputs ■ CY7C194BN is available in 24-pin DIP, 24-pin SOJ packages. The CY7C194BN is a high-performance CMOS Asynchronous SRAM organized as 64 K × 4 bits that supports an asynchronous memory interface. The device features an automatic power-down feature that significantly reduces power consumption when deselected. See the Truth Table in this data sheet for a complete description of read and write modes. The CY7C194BN is available in 24-pin DIP, 24-pin SOJ package(s). Logic Block Diagram RAM Array Sense Amps Row Decoder Input Buffer I/Ox CE Column Decoder WE Power Down Circuit OE (7C195 only) X Cypress Semiconductor Corporation Document #: 001-06446 Rev. *D • 198 Champion Court • A X San Jose, CA 95134-1709 • 408-943-2600 Revised June 2, 2011 [+] Feedback CY7C194BN Contents Product Portfolio .............................................................. 3 Pin Layout and Specification .......................................... 4 Pin Description ................................................................. 5 CY7C194BN Truth Table .................................................. 5 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 DC Electrical Characteristics .......................................... 6 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads .................................................................. 7 AC Test Conditions .......................................................... 7 AC Electrical Characteristics .......................................... 8 Timing Waveforms ........................................................... 8 Document #: 001-06446 Rev. *D Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15 Page 2 of 15 [+] Feedback CY7C194BN Product Portfolio -15 Unit Maximum access time Description 15 ns Maximum operating current 80 mA Maximum CMOS standby current 10 mA Document #: 001-06446 Rev. *D Page 3 of 15 [+] Feedback CY7C194BN Pin Layout and Specification CY7C194BN 24-pin SOJ (8 × 15 × 3.5 mm) A6 1 24 VCC A7 2 23 A5 A8 3 22 A4 A9 4 21 A3 A10 5 20 A2 A11 6 19 A1 A12 7 18 A0 A13 8 17 I/O3 A14 9 16 I/O2 A15 10 15 I/O1 CE 11 14 I/O0 GND 12 13 WE CY7C194BN 24-pin DIP (6.6 × 31.8 × 3.5 mm) Document #: 001-06446 Rev. *D A6 1 24 VCC A7 2 23 A5 A8 3 22 A4 A9 4 21 A3 A10 5 20 A2 A11 6 19 A1 A12 7 18 A0 A13 8 17 I/O3 A14 9 16 I/O2 A15 10 15 I/O1 CE 11 14 I/O0 GND 12 13 WE Page 4 of 15 [+] Feedback CY7C194BN Pin Description Pin Type CY7C194BN Description AX Input Address inputs CE Control Chip enable I/OX Input or output Data input/outputs NC – VCC WE 24-pin DIP 24-pin SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 18, 19, 20, 21, 22, 23 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 18, 19, 20, 21, 22, 23 11 11 14, 15, 16, 17 14, 15, 16, 17 No connect. pins are not internally connected to the die – – Supply Power (V) 24 24 Control Write enable 13 13 CY7C194BN Truth Table CE WE H X High Z I/Ox Power-down Mode Standby (ISB) Power L H Data out Read Active (ICC) L L Data in Write Active (ICC) Maximum Ratings Above which the useful life may be impaired. For user guidelines, not tested. Parameter Description Value Unit TSTG Storage temperature –65 to +150 °C TAMB Ambient temperature with power applied (i.e. case temperature) –55 to +125 °C VCC Core supply voltage relative to VSS VIN, VOUT DC voltage applied to any pin relative to VSS IOUT Output short-circuit current VESD Static discharge voltage (per MIL-STD-883, Method 3015) ILU Latch-up current > 200 mA –0.5 to +7.0 V –0.5 to VCC + 0.5 V 20 mA > 2001 V Operating Range Range Ambient Temperature (TA) Voltage Range (VCC) Commercial 0 °C to 70 °C 5.0 V ± 10% Document #: 001-06446 Rev. *D Page 5 of 15 [+] Feedback CY7C194BN DC Electrical Characteristics Parameter [1] Description Condition 15 ns Unit Min Max 2.2 VCC + 0.3 V –0.3 0.8 V 2.4 – V VIH Input HIGH voltage VIL Input LOW voltage VOH Output HIGH voltage VCC = Min, lOH = –4.0 mA VOL Output LOW voltage VCC = Min, lOL = 8.0 mA – 0.4 V ICC VCC operating supply current VCC = Max, IOUT = 0 mA, f = FMAX = 1 / tRC – 80 mA ISB1 Automatic CE Power-down current – TTL inputs VCC = Max, CE VIH, VIN VIH or VIN VIL, f = FMAX – 30 mA ISB2 Automatic CE Power-down current – CMOS inputs VCC = Max, CE VCC – 0.3 V, VIN > VCC – 0.3 V or VIN 0.3 V, f = 0, Commercial – 10 mA IOZ Output leakage current GND VI VCC, output disabled –5 +5 A IIX Input load current GND VI VCC –5 +5 A Max Unit 7 pF 10 – Capacitance Parameter [2] Description CIN Input capacitance COUT Output capacitance Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Thermal Resistance Parameter [2, 3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Conditions Still Air, soldered on a 3 x 4.5 square inches, two-layer printed circuit board CY7C194BN 24-pin DIP 24-pin SOJ 75.69 84.15 33.80 37.56 Unit °C/W Notes 1. VIL(min) = –2.0 V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process change that may affect these parameters 3. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. Document #: 001-06446 Rev. *D Page 6 of 15 [+] Feedback CY7C194BN AC Test Loads Output Loads Output Loads for tHZOE for , tHZCE & tHZWE R1 R3 VCC VCC Output C1 R2 C2 (A)* (B)* All Input Pulses Thevenin Equivalent Output R4 VCC VT Rth VSS 90% 90% 10% 10% Rise Time 1 V/ns Fall Time 1 V/ns * including scope and jig capacitance AC Test Conditions Parameter Description Nom Unit 30 pF C1 Capacitor 1 C2 Capacitor 2 5 R1 Resistor 1 480 R2 Resistor 2 255 R3 Resistor 3 480 R4 Resistor 4 255 RTH Resistor Thevenin 167 VTH Voltage Thevenin 1.73 Document #: 001-06446 Rev. *D V Page 7 of 15 [+] Feedback CY7C194BN AC Electrical Characteristics Parameter [4, 5, 6, 7] 15 ns Description Min Max Unit tRC Read cycle time 15 – ns tAA Address to data valid – 15 ns tOHA Data hold from address change 3 – ns tACE CE to data valid – 15 ns tLZCE CE to Low Z 3 – ns tHZCE CE to High Z – 7 ns tPU CE to Power-up 0 – ns tPD CE to Power-down – 15 ns tWC Write cycle time 15 – ns tSCE CE to write end 10 – ns tAW Address set-up to write end 10 – ns tHA Address hold from write end 0 – ns tSA Address set-up to write start 0 – ns tPWE WE pulse width 9 – ns tSD Data set-up to write end 8 – ns tHD Data hold from write end 0 – ns tHZWE WE LOW to High Z – 7 ns tLZWE WE HIGH to Low Z 3 – ns Timing Waveforms Figure 1. Read Cycle No. 1 [8, 9] tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Notes 4. Tested initially and after any design or process change that may affect these parameters 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE for any given device. 6. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 7. tHZCE, tHZWE are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage. 8. Device is continuously selected. CE = VIL. 9. WE is HIGH for Read Cycle. Document #: 001-06446 Rev. *D Page 8 of 15 [+] Feedback CY7C194BN Timing Waveforms (continued) Figure 2. Read Cycle No. 2 [10, 11, 12] tRC Address CE tHZCE tACE OE tDOE tHZOE tLZOE High Z Data Out tLZCE tPU ICC V CC tPD 50% ISB Current High Z Data Valid 50% Figure 3. Write Cycle No. 1 (WE Controlled) [10, 13] t WC Address tSCE CE tAW tHA tPWE tSA WE tSD Data In/Out Undefined tHD Undefined See Footnotes Data-In Valid see footnotes tHZWE tLZWE Notes 10. Tested initially and after any design or process change that may affect these parameters 11. WE is HIGH in read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. The minimum write cycle time is the sum of tHZWE and tSD. Document #: 001-06446 Rev. *D Page 9 of 15 [+] Feedback CY7C194BN Timing Waveforms (continued) Figure 4. Write Cycle No. 2 (CE Controlled) [14, 15] tWC Address tSCE CE tSA tHA tAW WE tSD Data In/Out High Z Data-In Valid tHD High Z Notes 14. This cycle is CE controlled. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 001-06446 Rev. *D Page 10 of 15 [+] Feedback CY7C194BN Ordering Information Speed (ns) Ordering Code Package Diagram 15 CY7C194BN-15PC 51-85013 CY7C194BN-15VC 51-85030 Power Option Operating Range 24-pin DIP (6.6 × 31.8 × 3.5 mm) Standard Commercial 24-pin SOJ (8 × 15 × 3.5 mm) Standard Commercial Package Type Please contact local sales representative regarding availability of these parts. Ordering Code Definitions CY 7 C 1 94 BN - 15 X C Temperature Range: C = Commercial Package Type: X = P or V P = 24-pin DIP V = 24-pin SOJ Speed: 15 ns BN = 0.25 µm Technology 94 = 256 K bit density with datawidth × 4bits 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document #: 001-06446 Rev. *D Page 11 of 15 [+] Feedback CY7C194BN Package Diagrams Figure 5. 24-pin (300-mil) SOJ V24.3/VZ24.3 (Molded SOJ V13), 51-85030 51-85030 *C Figure 6. 24-pin PDIP (1.260 × 0.270 × 0.140 Inches) P24.3, 51-85013 51-85013 *C Document #: 001-06446 Rev. *D Page 12 of 15 [+] Feedback CY7C194BN Acronyms Acronym Document Conventions Description Units of Measure CE CMOS chip enable complementary metal oxide semiconductor °C degree Celsius DIP dual in-line package MHz Mega Hertz ESD electrostatic discharge A micro Amperes I/O input/output mA milli Amperes SOJ small outline J-lead mm milli meter SRAM static random access memory ns nano seconds TTL transistor-transistor logic ohms WE write enable % percent pF pico Farad V Volts W Watts Document #: 001-06446 Rev. *D Symbol Unit of Measure Page 13 of 15 [+] Feedback CY7C194BN Document History Page Document Title: CY7C194BN, 256 Kb (64 K × 4) Static RAM Document Number: 001-06446 REV. ECN No. Issue Date Orig. of Change Description of Change ** 424111 See ECN NXR New Data Sheet *A 2892510 03/18/2010 VKN Removed 25ns speed bin Updated Ordering Information table Updated Package Diagram Added Sales, Solutions, and Legal Information *B 3108898 12/13/2010 AJU Added Ordering Code Definitions. *C 3219087 04/18/2011 PRAS Updated as per template Added TOC Added Acronyms and Units of Measure. *D 3271782 06/02/2011 PRAS Updated General Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Updated in new template. Document #: 001-06446 Rev. *D Page 14 of 15 [+] Feedback CY7C194BN Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06446 Rev. *D Revised June 2, 2011 Page 15 of 15 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback