CY8CMBR2044 ® Four Button CapSense Controller Four Button CapSense® Controller Features Overview ■ Easy to use capacitive button controller ❐ Four-button solution configurable through Hardware straps ❐ No software tools or programming required ❐ Four general-purpose outputs (GPOs) ® ❐ GPOs linked to CapSense buttons ❐ GPOs support direct LED drive ■ Robust noise performance ❐ Specifically designed for superior noise immunity to external radiated and conducted noise ❐ Low radiated noise emission ■ SmartSense™ Auto-Tuning ❐ Saves time and effort in device tuning ❐ CapSense parameters dynamically set in runtime ❐ Maintains optimal button performance even in noisy environment ❐ Wide parasitic capacitance CP range (5 pF–40 pF) ■ System Diagnostics of CapSense buttons - reports any faults at device power up ❐ Button shorted to Ground ❐ Button shorted to VDD ❐ Button to button short ❐ Improper value of modulator capacitor (CMOD) ❐ Parasitic capacitance (CP) out of range ■ Advanced features ❐ Toggle ON/OFF feature on GPOs ❐ Flanking Sensor Suppression (FSS) provides robust sensing even with closely spaced buttons ❐ Configurable LED ON time after button release ❐ Button output reset if touched for excessive time ❐ User-controlled Button Scan Rate ❐ Serial Debug Data output • Simplifies production line testing and system debug ■ Wide operating voltage range ❐ 1.71 V to 5.5 V – ideal for both regulated and unregulated battery applications ■ Low power consumption  per button ❐ Supply current in run mode as low as 15 µA ❐ Deep sleep current: 100 nA ■ Industrial temperature range: –40 °C to + 85 °C ■ 16-pad quad flat no (3 mm × 3 mm × 0.6 mm) leads (QFN) The CY8CMBR2044 incorporates several innovative features to save time and money to quickly enable a capacitive touch sensing user interface in your design. It is a hardware configurable device and does not require any software tools or coding. This device is enabled with Cypress's revolutionary SmartSense™ Auto-Tuning algorithm. SmartSense™ Auto-Tuning ends the need to manually tune the user interface during development and production ramp. This speeds the time to volume and saves valuable engineering time, test time and production yield loss. The CY8CMBR2044 CapSense controller supports up to four capacitive touch sensing buttons and four General Purpose Outputs (GPOs). The GPO is an active low output controlled directly by the CapSense input making it ideal for a wide variety of consumer, industrial, and medical applications. The wide operating range of 1.71 V to 5.5 V enables unregulated battery operation, further saving component cost. Also, the same device can be used in different applications with different power supplies, including low power supplies. This device supports ultra low-power consumption in both run mode and deep sleep mode to stretch battery life. In addition, this device also supports many advanced features which enhance the robustness and user interface of the end solution. Some of the key advanced features include Noise Immunity and FSS. Noise Immunity improves the immunity of the device against radiated and conducted noise, such as audio and radio frequency (RF) noise. FSS provides robust sensing even with closely spaced buttons. FSS is a critical requirement in small form factor applications. Serial Debug Data output gives the critical information about the design, such as button Cp and Signal-to-Noise Ratio (SNR). This further helps in production line testing. package Note 1. Power consumption calculated with 1.7% touch time, 500 ms scan rate, and CP of each sensor < 19 pF. Cypress Semiconductor Corporation Document Number: 001-57451 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 22, 2012 CY8CMBR2044 Contents Pinout ................................................................................ 3 Typical Circuits ................................................................. 4 Schematic 1: 4-Buttons, 4-LEDs with Auto Reset Enabled .................................................... 4 Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and Advanced Features Enabled ..... 5 Configuring the CY8CMBR2044 ...................................... 6 Device Features ................................................................ 6 CapSense Buttons ...................................................... 6 SmartSense Auto Tuning ............................................ 6 General Purpose Outputs ............................................ 6 Toggle ON/OFF ........................................................... 7 Flanking Sensor Suppression (FSS) ........................... 7 LED ON Time .............................................................. 7 Button Auto Reset ....................................................... 8 System Diagnostics ..................................................... 9 Serial Debug Data ..................................................... 10 Power Consumption and Device Operating Modes .................................................. 12 Additional Components to Enable Advanced Features .......................................... 14 Response Time ......................................................... 14 Layout Guidelines and Best Practices ......................... 15 CapSense Button Shapes ......................................... 16 Document Number: 001-57451 Rev. *E Button Layout Design ................................................ 16 Recommended Via Hole Placement ......................... 16 Example PCB Layout Design with Four CapSense Buttons and Four LEDs ................... 17 Electrical Specifications ................................................ 18 Absolute Maximum Ratings ....................................... 18 Operating Temperature ............................................. 18 DC Electrical Characteristics ..................................... 19 AC Electrical Specifications ....................................... 21 CapSense Specifications .......................................... 21 Ordering Information ...................................................... 22 Ordering Code Definitions ......................................... 22 Package Diagram ............................................................ 23 Package Information ................................................. 23 Appendix ......................................................................... 24 Acronyms ........................................................................ 26 Document Conventions ................................................. 26 Units of Measure ....................................................... 26 Document History Page ................................................. 27 Sales, Solutions, and Legal Information ...................... 29 Worldwide Sales and Design Support ....................... 29 Products .................................................................... 29 PSoC Solutions ......................................................... 29 Page 2 of 29 CY8CMBR2044 Pinout Table 1. Pin Diagram and Definitions – CY8CMBR2044 If Unused DO GPO activated by CS1 Leave open 2 GPO0 DO GPO activated by CS0 Leave open 3 Toggle/ FSS AI Controls FSS and Toggle ON/OFF features Ground 4 Delay AI Controls LED ON Time. For Ground details refer to Table 2 on page 6 5 CS0 AIO CapSense input, controls GPO0 Ground or serial debug data out 6 CS1 AIO CapSense input, controls GPO1 Ground or serial debug data out 7 VSS P Ground 8 CS2 AIO CapSense input, controls GPO2 Ground or serial debug data out 9 ARST AIDO Controls Button Auto Reset 10 CS3 AIO CapSense input, controls GPO3 Ground or serial debug data out 11 XRES DI Device reset, active high, with internal pull down Leave open 12 ScanRate AI / Sleep Controls scan rate and deep sleep Ground 13 VDD P Power 14 GPO3 DO GPO activated by CS3 15 CMOD AI External modulator capacitor, connect a 2.2 nF (±10%) to ground 16 GPO2 DO GPO activated by CS2 GPO1 GPO0 Toggle/FSS Delay 14 13 GPO1 GPO2 CMOD GPO3 VDD Description 1 16 15 Type  1 12 QFN 2 11 (Top View) 3 10 9 4 5 6 7 8 Label ScanRate/Sleep XRES CS3 ARST CS0 CS1 VSS CS2 Pin Leave open Leave open Leave open Note 2. AI – Analog Input, AIO – Analog Input / Output, AIDO – Analog Input / Digital Output, DI – Digital Input, DO – Digital Output, P – Power Document Number: 001-57451 Rev. *E Page 3 of 29 CY8CMBR2044 Typical Circuits Schematic 1: 4-Buttons, 4-LEDs with Auto Reset Enabled VDD D4 D3 LED LED VDD VD D GPO0–GPO3 pins: LED and 560- to VDD ❐ CapSense buttons driving 4 LEDs (GPO0–GPO3) ■ CMOD pin: 2.2 nF to ground ❐ Modulator capacitor ■ XRES pin: Floating ❐ For external reset Document Number: 001-57451 Rev. *E R3 560 E VD D VDD 14 6 C S1 R8 1 11 XR ES 10 C S3 R1 1 560E 1 CS3 AR ST CS2 9 5 K(10% ) 5 C S0 R7 1 0E R6 560 E R 12 CS0 ■ 13 C2 L ED 3 15 AR ST 0E In the above schematic, the device is configured to support: CS0–CS3 pins: 560- to CapSense button ❐ Four CapSense buttons (CS0–CS3) C S3 D elay TP1 ■ 2.2n F LED 2 Tog gle /F SS C Y 8C MBR20 44 R9 XR ES U5 C S0 4 G PO0 TP2 C S2 3 G PO3 2 VSS LED 0 12 8 560 E 7 R2 Scanr ate/ Sleep C S2 LED G PO1 560E 1 C3 0. 1uF R 10 LED 1 C1 10uF 1 560 E CM OD R1 CS1 LED 560E D2 C S1 D1 G PO2 VD D 16 560 E R4 VDD ■ Toggle/FSS pin: Ground ❐ Toggle ON/OFF disabled ❐ FSS disabled ■ ARST pin: 5 k to Ground ❐ Button Auto Reset enabled, 20 second time ■ Delay pin: Ground ❐ LED ON Time disabled ScanRate/Sleep pin: Ground ❐ User configured scan rate = 20 ms To enable Serial Debug Data output, connect a 5.6 k resistor on R9 or R12. ■ Page 4 of 29 CY8CMBR2044 Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and Advanced Features Enabled VD D VD D D3 VDD VDD VDD LED C2 GPO 3 VD D 15 14 13 Tog gle/ FSS CS3 D elay ARST 6 C S1 XR ES 560E(1% ) 10 9 TO MASTER TP1 ARST ■ ■ CS0–CS2 pins: 560- to CapSense buttons; CS3 pin: Ground ❐ Three CapSense buttons (CS0–CS2) ❐ CS3 not used in design GPO0–GPO2 pins: LED and 560- to VDD; GPO3 floating; GPO0–GPO1 pins interfaced to Master ❐ CapSense buttons driving 3 LEDs (GPO0–GPO2) ❐ GPO0, GPO1 interfaced to master for direct status read ■ CMOD pin: 2.2 nF to ground ❐ Modulator capacitor ■ XRES pin: Floating ❐ For external reset Document Number: 001-57451 Rev. *E 560E R9 In the above schematic the device is configured to support: C S2 1 560E R8 1 C S1 R7 C S0 1 560E R6 5 CS0 C Y 8CMBR2044 11 R2 0E 4 SCAN R 11 4K(1% ) XRES U5 12 5K( 10%) R5 GPO 0 C S0 3 CS2 2 5.1K( 5%) Scanr ate/ Sleep VSS LED1 R4 GPO 1 8 1 7 LED0 CS1 TO MASTER TO MASTER CM OD 16 LED2 R1 560E G PO2 R3 560E VDD R10 560E LED GPO 3 D1 LED C S2 D2 C3 0. 1uF 2.2nF C1 10uF ■ Toggle/FSS pin: 5.1 k to Ground ❐ Toggle ON/OFF disabled ❐ FSS enabled ■ ARST pin: 5 k to Ground ❐ Button Auto Reset enabled, Auto Reset period = 20 seconds ■ Delay pin: 4 k to Ground ❐ LED ON Time of 1000 ms ScanRate/Sleep pin: 560 to Master ❐ User configured scan rate = 30 ms ❐ Master to control device operating mode To enable Serial Debug Data output, connect a 5.6 k resistor on R11. ■ Page 5 of 29 CY8CMBR2044 Configuring the CY8CMBR2044 ■ The CY8CMBR2044 device features are configured using external resistors. General Purpose Outputs The resistors on the hardware configurable pins are determined by the device upon power-on. The Appendix gives the matrix of features enabled using different external resistor configurations. To know more about the required settings for your design, refer to the CY8CMBR2044 Design Guide. Device Features CapSense Buttons ■ Device supports up to four CapSense buttons ■ Ground the CSx pin to disable CapSense input ■ A 2.2-nF (+10%) capacitor must be connected on the CMOD pin for proper CapSense operation ■ The parasitic Capacitance (CP) of each button must be less than 40 pF for proper CapSense operation Ensures portability of the user interface design ■ The GPOx is controlled by the corresponding CSx ■ GPOx pin outputs are in strong drive mode  ■ Active low output – supports sinking configuration ■ If CSx is disabled (grounded), then the corresponding GPOx must be left floating ■ A 5-ms pulse is sent after 175 ms after device power-up, on a GPOx, if the CSx fails the System Diagnostics. Table 2. Advanced Features supported by CY8CMBR2044 Feature Benefits Toggle ON/OFF Button retains state on touch (ON/OFF) Flanking Sensor Suppression (FSS) Helps in distinguishing closely spaced buttons LED ON Time Gives an LED effect on button release Button Auto Reset Disables false output trigger due to conducting object placed close to button SmartSense Auto Tuning ■ Device supports auto tuning of CapSense parameters System Diagnostics ■ No manual tuning required; all parameters are automatically tuned by the device Support for production testing and debugging Serial Debug Data Support for production testing and validating design ■ Compensates printed circuit board (PCB) variations, device process variations, and PCB vendor changes Low Power Sleep Mode and Deep Sleep Mode Low power consumption Note 3. When a pin in in strong drive mode, it is pulled up to VDD when the output is HIGH and pulled down to Ground when the output is LOW. The output cannot be floating. Document Number: 001-57451 Rev. *E Page 6 of 29 CY8CMBR2044 Toggle ON/OFF LED ON Time ■ Toggles the GPO state at each button touch. ■ ■ Used for mechanical button replacement. For example, wall switch. Provides better visual feedback when a button is released and improves the design’s aesthetic value. ■ The GPOx is driven low for a specified interval after the corresponding CSx button is released. ■ When a button gets reset, LED ON Time is not applied on the corresponding GPO. ■ In Figure 3 on page 7, GPO0 goes high prematurely (prior to LED ON Time) because CS1 button is released. Therefore, the LED ON Time counter is reset. Now, GPO1 remains LOW for LED ON Time after releasing CS1. ■ LED ON Time can range from 0–2000 ms. ■ LED ON Time resolution is 20 ms. Flanking Sensor Suppression (FSS) ■ Helps to distinguish closely spaced buttons. ■ Also used in situations when a button can produce opposite effects. For example, an interface with two buttons for brightness control (UP or DOWN). ■ FSS action can be explained for the following different scenarios: ❐ When only one button is touched, it is reported as ON. ❐ When more than one button is detected as ON and previously one of those buttons was touched, then the previously touched button is reported as ON. Figure 1. Example of Toggle Feature on GP0 Figure 2. Button Status with Respect to Finger Touch when FSS is Enabled Figure 3. Example LED ON timing diagram on GPO0 CS0 GPO0 LED ON Time Document Number: 001-57451 Rev. *E Page 7 of 29 CY8CMBR2044 Figure 4. Example LED ON timing diagram on multiple GPO0 and GPO1 CS0 CS1 GPO0 Start LED ON Time Counter GPO1 Reset LED ON Time Counter LED ON Time Restart LED ON Time Counter Button Auto Reset ■ Prevents button stuck, due to metal object placed close to a button. ■ Useful when GPO output to be kept ON only for a specific time. ■ If enabled, the GPOx is driven for a maximum of Button Auto Reset period when CSx is continuously touched. See Figure 5 on page 8. ■ Button Auto Reset period can be set to 5 or 20 seconds. ■ After the Button Auto Reset has been triggered, the CSx hold time of that button after the button has been released is given in Table 3. The hardware configuration is shown in Table 15 in Appendix. Table 3. Button Hold Time After Auto Reset Button Press Time after Button Auto Reset Button Hold Time (ms) < 2 sec 220 > 2 sec ScanRate + 200 Figure 5. Example of Button Auto Reset on GP0 Button is touched for more than the Auto Reset period Auto Reset period CS0 GPO0 GPO0 is not driven after Auto Reset period Document Number: 001-57451 Rev. *E Page 8 of 29 CY8CMBR2044 System Diagnostics ■ A built-in Power-on Self Test (POST) mechanism performs some tests at Power-on Reset (POR), which can be useful in production testing. ■ If any button fails these tests, a 5 ms pulse is sent out on the corresponding GPO withing 175 ms after POR. ■ Following tests are performed on all the buttons - Figure 7. Button Shorted to VDD Button Shorted to Ground If any button is found to be shorted to ground, it is disabled. See Figure 6. Figure 6. Button Shorted to Ground Button to Button Short If two or more buttons are found to be shorted to each other, all of these buttons are disabled. See Figure 8. Figure 8. Button to Button Short Button Shorted to VDD If any button is found to be shorted to VDD, it is disbled. See Figure 7. Improper Value of CMOD ■ Recommended value of CMOD is 2 nF to 2.4 nF. ■ If the value of CMOD is found to be less than 1 nF or greater than 4 nF, all the buttons are disabled. Button CP > 40 pF If the parasitic capacitance (CP) of any button is found to be more than 40 pF, that button is disabled. Document Number: 001-57451 Rev. *E Page 9 of 29 CY8CMBR2044 Figure 9. Example Showing CS0 and CS1 Passing the POST and CS2 and CS3 Failing 5 ms pulse Max time to get 5 ms pulse is 175 ms after power up In Figure 9, CS0 and CS1 buttons are enabled; CS2 and CS3 buttons are disabled because they failed the Power-on Self Test. A 5 ms pulse is observed on GPO2 and GPO3. ■ Firmware revision, CapSense status, GPO status, raw count, baseline, difference count, and parasitic capacitance of all sensors are sent out Serial Debug Data ■ For designs having a maximum of three CapSense buttons, Cypress recommends to take the debug data on a CapSense button that is not used in design ■ For designs with four CapSense buttons, Cypress recommends taking debug data on two CapSense buttons. For example, pull down CS0 with a 5.6 kresistor and read data of CS1, CS2, and CS3. Next, pull down CS1 with a 5.6 k resistor and read data of CS0, CS2, and CS3 ■ Used to see CapSense data for debug purposes ■ If enabled, debug data is transmitted using UART communication protocol. ■ To enable this feature pull down any one of the CapSense pins with a 5.6 k resistor to ground. Data is sent out on the same CapSense pin ■ If more than one CapSense pin is pulled down, debug data is sent out only on one CapSense pin and the priority is CS0 > CS1 > CS2 > CS3 For more information on Raw Count, Baseline, Difference Count and Parasitic Capacitance, refer to Getting Started with CapSense, section 2. For more information on MultiChart tool, refer to AN2397 CapSense Data Viewing Tools, Method 2. ■ The Cypress MultiChart tool can be used to view the data as a graph. ■ MultiChart tool arranges the data in the format as shown in Table 4. ■ Serial data is sent out with ~115,200 baud rate ■ The Serial Debug Data is sent by the device in the order as per Table 5. Table 4. Serial Debug Data arranged in MultiChart S.No. Raw Count Array Baseline Array Signal Array MSB LSB MSB LSB MSB LSB 0 0x00 FW_Revision CS _Status GPO_Status 0x00 CS2_CP 1 0x00 CS0_ CP 0x00 CS1_CP 0x00 CS3_ CP 2 CS0_RawCount CS0_Baseline CS0_DiffCount 3 CS1_RawCount CS1_Baseline CS1_DiffCount 4 CS2_RawCount CS2_Baseline CS2_DiffCount 5 CS3_RawCount CS3_Baseline CS3_DiffCount Document Number: 001-57451 Rev. *E Page 10 of 29 CY8CMBR2044 Table 5. Serial Data Output sent by CY8CMBR2044 Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Data 0x0D 0x0A 0x00 FW_Revision 0x00 CS0_CP CS0_RawCount_MSB CS0_RawCount_LSB CS1_RawCount_MSB CS1_RawCount_LSB CS2_RawCount_MSB CS2_RawCount_LSB CS3_RawCount_MSB CS3_RawCount_LSB CS _Status GPO_Status 0x00 CS1_CP CS0_ Baseline _MSB CS0_ Baseline _LSB CS1_ Baseline _MSB CS1_ Baseline _LSB CS2_ Baseline _MSB CS2_ Baseline _LSB CS3_ Baseline _MSB CS3_ Baseline _LSB 0x00 CS2_CP 0x00 CS3_CP CS0_ DiffCount _MSB CS0_ DiffCount _LSB CS1_ DiffCount _MSB CS1_ DiffCount _LSB CS2_ DiffCount _MSB CS2_ DiffCount _LSB CS3_ DiffCount _MSB CS3_ DiffCount _LSB 38 39 40 0x00 0xFF 0xFF Document Number: 001-57451 Rev. *E Notes Dummy data for multi chart – – – CS0 parasitic capacitance in Hex Unsigned 16-bit integer – Unsigned 16-bit integer – Unsigned 16-bit integer – Unsigned 16-bit integer – Gives CapSense button status, least significant bit (LSB) contains CS0 status Gives GPO status, LSB contains GPO0 status – CS1 parasitic capacitance in Hex Unsigned 16-bit integer – Unsigned 16-bit integer – Unsigned 16-bit integer – Unsigned 16-bit integer – – CS2 parasitic capacitance in Hex – CS3 parasitic capacitance in Hex Unsigned 16-bit integer – Unsigned 16-bit integer – Unsigned 16-bit integer – Unsigned 16-bit integer – Dummy data for multi chart Page 11 of 29 CY8CMBR2044 Power Consumption and Device Operating Modes The CY8CMBR2044 is designed to meet the low power requirements of battery powered applications. To design for the lowest operating current ■ Ground all unused CapSense inputs ■ Minimize CP using the design guidelines in Getting Started with CapSense, section 3.7.1. ■ Lower the supply voltage. ■ Use a higher Button Scan Rate or Deep Sleep operating mode. To know more about the steps to reduce power consumption, refer to CY8CMBR2044 Design Guide, section 5. There are two device operating modes: ■ Low power sleep mode ■ Deep sleep mode Low Power Sleep Mode The following flow chart describes the low power sleep mode operation. Figure 10. Low Power Sleep Mode Operation Scan all buttons with 20 ms Scan Rate (Scan time + Sleep time) No NO button touched for 2 secs? Yes Yes Scan all buttons with user defined scan rate. No Is any button active? Figure 11. Low Power Sleep Mode Implementation Document Number: 001-57451 Rev. *E Page 12 of 29 CY8CMBR2044 ■ To enable low power sleep mode, the hardware configurable pin ScanRate/Sleep should be pulled down to ground with resistor ‘R’ (1%). The scan rate values for different resistor values are given in Table 15 in Appendix. ■ If the ScanRate/Sleep pin is pulled to ground without any resistor, the Button Scan Rate is set to 20 ms. The device operates in low power sleep mode, unless a button is touched. ■ The range of scan rate is 20 to 530 ms. Figure 12. Average Current vs Scan Rate  Note 4. Number of sensors = 3, Cp < 19 pF, 0% touch time, VDD = 3 V. Document Number: 001-57451 Rev. *E Page 13 of 29 CY8CMBR2044 Deep Sleep Mode Figure 13. ScanRate/Sleep Pin Connection to Enable Deep Sleep Mode External Resis tor R (Controls S can Rate) Digital Output pin ScanRate/Sleep (Controls Deep Sleep) CY 8CMBR 2044 HOST ■ To enable the deep sleep mode, the hardware configuration pin ScanRate/Sleep should be connected to the master device as shown in Figure 13. ■ When device comes out of deep sleep mode, the CapSense system is reinitialized. Typical time for reinitialization is 8 ms. Any button touch within this time is not reported. ■ Host controller should pull the pin to VDD for the device to go into deep sleep. ■ After the device comes out of deep sleep, the device operates in low power sleep mode. ■ The Host controller output pin should be in Strong drive mode, so that the ScanRate/Sleep pin is not left floating. ■ ■ In deep sleep mode, all blocks are turned off and the device current consumption is approximately 0.1 µA. If the ScanRate/Sleep pin is pulled high at power on, then the device does not go to deep sleep immediately. The device goes to deep sleep after initializing all internal blocks and scanning all buttons once. ■ There is no CapSense scanning in deep sleep mode. ■ ■ ScanRate/Sleep pin should be pulled low for the device to wake up from deep sleep. If the ScanRate/Sleep pin is pulled high at power on, then the button scan rate is calculated when the device is taken out of Deep Sleep by the master. Additional Components to Enable Advanced Features S.No. Feature Resistors required 1 1 Low power sleep and deep sleep 2 Toggle/FSS 1 3 4 Delay Off Sensor auto reset 1 1 Notes Deep sleep is controlled by a master device. When the device comes out of deep sleep, it enters into low power sleep mode based on settings. Resistor is not required if both features are not used. To enable both the features only one resistor is required. Resistor is not required if both features are not used. Resistor is not required if the feature is not used. Resistor is not required if the feature is not used. Response Time Response time is the minimum amount of time the button should be touched for the device to detect as valid button press. Condition First button press Consecutive button press after first button press Document Number: 001-57451 Rev. *E Response time (in ms) Button Scan rate value + 20. For button scan rate value, see Table 15 in Appendix. 80 Page 14 of 29 CY8CMBR2044 Layout Guidelines and Best Practices S.No. Category 1 Button shape Min – Max – Recommendations / Remarks Solid round pattern, round with LED hole, rectangle with round corners 5 mm Equal to Button Ground Clearance 0.5 mm 15 mm – Refer Design Toolbox 8 mm (Y dimension in Button Layout Design on page 16) 2 mm Refer Design Toolbox (X dimension in Button Layout Design on page 16) – – – – – 450 mm Hatched ground 7 mil trace and 45 mil grid (15% filling) Hatched ground 7 mil trace and 70 mil grid (10% filling) Refer Design Toolbox 0.17 mm – 0.20 mm – 0.17 mm (7 mil) Traces should be routed on the non button side. If any non CapSense trace crosses CapSense trace, ensure that intersection is orthogonal 2 3 Button size Button-button spacing 4 Button ground clearance 5 6 7 8 9 Ground flood – top layer Ground flood – bottom layer Trace length from button pad to CapSense controller pins Trace width Trace routing 10 Via position for the buttons – – 11 12 13 Via hole size for button traces No. of via on button trace Distance of CapSense series resistor from button pin – 1 – – 2 10 mm Via should be placed near the edge of the button to reduce trace length thereby increasing sensitivity 10 mil 1 Place CapSense series resistors close to the device for noise suppression. CapSense resistors have highest priority; place them first 14 Distance between any CapSense trace to ground flood Device placement 10 mil 20 mil 20 mil – – Mount the device on the layer opposite to button. The CapSense trace length between the device and buttons should be minimum (see trace length above) Placement of components in two layer PCB Placement of components in four layer PCB – – – – Top layer – buttons and bottom layer – device, other components and traces Top layer – buttons, second layer – CapSense traces and VDD (avoid VDD traces below the buttons), third layer – hatched ground, bottom layer – CapSense IC or device, other components, and non CapSense traces 15 16 17 18 19 Overlay thickness Overlay material 0 mm – 5 mm – Refer Design Toolbox Should be non-conductive material. Glass, ABS plastic, formica, wood, and so on. There should be no air gap between PCB and overlay. Use adhesive to stick the PCB and overlay 20 Overlay adhesives – – 21 LED back lighting – – Adhesive should be non conductive and dielectrically homogenous. 467MP and 468MP adhesives made by 3M are recommended Cut a hole in the button pad and use rear mountable LEDs. Refer to Example PCB Layout Design with Four CapSense Buttons and Four LEDs on page 17 22 Board thickness – – Document Number: 001-57451 Rev. *E Standard board thickness for CapSense FR4 based designs is 1.6 mm. Page 15 of 29 CY8CMBR2044 CapSense Button Shapes Figure 14. CapSense Button Shapes Button Layout Design Figure 15. Button Layout Design X: Button to ground clearance (Refer to Layout Guidelines and Best Practices on page 15) Y: Button to button clearance (Refer to Layout Guidelines and Best Practices on page 15) Recommended Via Hole Placement Figure 16. Recommended Via Hole Placement Document Number: 001-57451 Rev. *E Page 16 of 29 CY8CMBR2044 Example PCB Layout Design with Four CapSense Buttons and Four LEDs Figure 17. Top Layer Figure 18. Bottom Layer Document Number: 001-57451 Rev. *E Page 17 of 29 CY8CMBR2044 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CMBR2044 device. Absolute Maximum Ratings Table 6. Absolute Maximum Ratings Parameter Description Min Typ Max Unit Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 85 °C degrades reliability. TSTG Storage temperature –55 25 +125 °C VDD Supply voltage relative to VSS –0.5 – +6.0 V VIO DC voltage on CapSense inputs and VSS – 0.5 digital output pins – VDD + 0.5 V IMIG Maximum current into any GPO output pin –25 – +50 mA ESD Electro static discharge voltage 2000 – – V LU Latch up current – – 200 mA Human body model ESD In accordance with JESD78 standard Operating Temperature Table 7. Operating Temperature Min Typ Max Unit TA Parameter Ambient temperature Description –40 – +85 °C TJ Operational die temperature –40 – +100 °C Document Number: 001-57451 Rev. *E Notes Page 18 of 29 CY8CMBR2044 DC Electrical Characteristics DC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 8. DC Chip Level Specifications Parameter VDD [5, 6, 7] Description Supply voltage Min Typ Max Unit 1.71 – 5.5 V Notes IDD Supply current – 2.88 4.0 mA Conditions are VDD = 3.0 V, TA = 25 °C IDA Active current – 2.88 4.0 mA Conditions are VDD = 3.0 V, TA = 25 °C, continuous sensor scan IDS Deep sleep current – 0.1 0.5 µA Conditions are VDD = 3.0 V, TA = 25 °C IAV1 Average current – 40 – µA Conditions are VDD = 3.0 V, TA = 25 °C, 4 – buttons used, 0% touch time, CP of all sensors < 19 pF and scan rate = 530 ms IAV2 Average current – 63 – µA Conditions are VDD = 3.0 V, TA = 25 °C, 4 – buttons used, 0% touch time, CP of all sensors > 19 pF and scan rate = 530 ms IAV3 Average current – 1 – mA Conditions are VDD = 3.0 V, TA = 25 °C, 4 – buttons used, 100% touch time, CP of all sensors < 19 pF and scan rate = 20 ms IAV4 Average current – 1.6 – mA Conditions are VDD = 3.0 V, TA = 25 °C, 4 – buttons used, 100% touch time, CP of all sensors > 19 pF and < 40 pF, scan rate = 20 ms Notes 5. When VDD remains in the range from 1.75 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.75 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 µs. This helps to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. 6. After power down, ensure that VDD falls below 100 mV before powering backup. 7. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD, the rate at which VDD drops should not exceed 200 mV/s. Base VDD can be between 1.8 V and 5.5 V Document Number: 001-57451 Rev. *E Page 19 of 29 CY8CMBR2044 DC General Purpose I/O Specifications These tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and –40 °C < TA < 85°C, 2.4 V to 3.0 V and –40 °C < TA < 85 °C, or 1.71 V to 2.4 V and –40 °C < TA < 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 9. 3.0 V to 5 V DC General Purpose I/O Specifications Parameter Description Min Typ Max Unit Notes VOH1 High output voltage on GP0, GP1, GP2, GP3 VDD – 0.2 – – V IOH < 10 µA, maximum of 40 µA source current in all I/Os VOH2 High output voltage on GP0, GP1 VDD – 0.9 – – V IOH = 1 mA, maximum of 2 mA source current in all I/Os VOH3 High output voltage on GP2, GP3 VDD – 0.9 – – V IOH = 5 mA, maximum of 10 mA source current in all I/Os VOL Low output voltage – – 0.75 V IOL = 25 mA/pin, VDD > 3.30, maximum of 60 mA sink current on GPO0, GPO1, GPO2, GPO3 Notes Table 10. 2.4 V to 3.0 V DC General Purpose I/O Specifications Parameter Description Min Typ Max Unit VOH1 High output voltage on GP0, GP1, GP2, GP3 VDD – 0.2 – – V IOH < 10 µA, maximum of 40 µA source current in all I/Os VOH2 High output voltage on GP0, GP1 VDD – 0.4 – – V IOH = 0.2 mA, maximum of 0.4 mA source current in all I/Os VOH3 High output voltage on GP2, GP3 VDD – 0.5 – – V IOH = 2 mA, maximum of 4 mA source current in all I/Os VOL Low output voltage – – 0.72 V IOL = 10 mA/pin, maximum of 30 mA sink current on GPO0, GPO1, GPO2, GPO3 Table 11. 1.71V to 2.4V DC General Purpose I/O Specifications Min Typ Max Unit VOH1 Parameter High output voltage on GP0,GP1 Description VDD – 0.2 – – V IOH =10 µA, maximum of 20 µA source current in all I/Os VOH2 High output voltage on GP0,GP1 VDD – 0.5 – – V IOH = 0.5 mA, maximum of 1 mA source current in all I/Os VOH3 High output voltage on GP2,GP3 VDD – 0.2 – – V IOH = 100 µA, maximum of 200 µA source current in all I/Os VOH4 High output voltage on GP2,GP3 VDD – 0.5 – – V IOH = 2 mA, maximum of 4 mA source current in all I/Os VOL Low output voltage – – 0.4 V IOL = 5 mA/pin, maximum of 20 mA sink current on GPO0, GPO1, GPO2, GPO3 Document Number: 001-57451 Rev. *E Notes Page 20 of 29 CY8CMBR2044 AC Electrical Specifications AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Parameter Min Max Unit Power supply slew rate – 250 V/ms TXRST External reset pulse width at power up 1 – ms After supply voltage is valid TXRST2 External reset pulse width after power-up 10 – µs Applies after part has booted Min Typ Max Unit SRPOWER_UP Description Notes VDD slew rate during power up AC General Purpose I/O Specifications Parameter Description Notes TRise1 Rise time on GPO0 and GPO1, Cload = 50 pF 15 – 80 ns VDD = 3.0 to 3.6 V, 10% – 90% TRise2 Rise time on GPO2 and GPO3, Cload = 50 pF 10 – 50 ns VDD = 3.0 to 3.6 V, 10% – 90% TRise3 Rise time on GPO0 and GPO1, Cload = 50 pF 15 – 80 ns VDD = 1.71 to 3.0V, 10% – 90% TRise2 Rise time on GPO2 and GPO3, Cload = 50 pF 10 – 80 ns VDD = 1.71 to 3.0 V, 10% – 90% TRise4 Fall time, Cload=50 pF all GPO outputs 10 – 50 ns VDD = 3.0 to 3.6 V, 90% – 10% TFall2 Fall time, Cload=50 pF all GPO outputs 10 – 70 ns VDD = 1.71 to 3.0 V, 90% – 10% Min Typ Max Unit Notes CapSense Specifications Parameter Description CP Parasitic capacitance 5.0 – (CP+CF)<40 pF CP is the total capacitance seen by the pin when no finger is present. CP is sum of CBUTTON, CTRACE, and Capacitance of the vias and CPIN CF Finger capacitance 0.25 – (CP+CF)<40 pF CF is the capacitance added by the finger touch CPIN Capacitive load on pins as input 0.5 1.7 7 pF CMOD External modulator capacitor 2 2.2 2.4 nF Mandatory for CapSense to work Rs Series resistor between pin and the sensor – 560 616 Reduces the RF noise Document Number: 001-57451 Rev. *E Page 21 of 29 CY8CMBR2044 Ordering Information Ordering Code Package Type Operating CapSense GPOs XRES Pin Temperature Inputs CY8CMBR2044-24LKXI 16-pin QFN (3 × 3 × 0.6 mm) Industrial 4 4 Yes CY8CMBR2044-24LKXIT 16-pin QFN (3 × 3 × 0.6 mm) (Tape and Reel) Industrial 4 4 Yes Ordering Code Definitions CY 8 C MBR 2044 - 24 LK X I X X = blank or T blank = Tube; T = Tape and Reel Temperature Range: I = Industrial Pb-free Package Type: LK = 16-pin QFN Speed Grade: 24 MHz Part Number Mechanical Button Replacement Technology Code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Document Number: 001-57451 Rev. *E Page 22 of 29 CY8CMBR2044 Package Diagram Figure 19. 16-pin Chip On Lead (3 × 3 × 0.6 mm) LG16A/LD16A (Sawn) Package Outline 001-09116 *F Package Information Table 12. Thermal Impedances by Package Package Typical JA 16-pin QFN 32.7 °C/W Table 13. Solder Reflow Peak Temperature Package Minimum Peak Temperature  Maximum Peak Temperature 16-pin QFN 240 °C 260 °C Notes 8. TJ = TA + Power x JA 9. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-57451 Rev. *E Page 23 of 29 CY8CMBR2044 Appendix Table 14. Device Features vs. Resistor Configuration Matrix Features Button Auto Reset Comments Pin Configuration Device Pin Name Enabled, Auto Reset Period = 5 ms Ground / Floating ARST Enabled, Auto Reset Period = 20 ms 5.1 kΩ (±5%) to ground Disabled VDD 0 ms Ground 20 ms 120 Ω (±1%) to ground 40 ms 200 Ω (±1%) to ground LED ON Time 60 ms 280 Ω (±1%) to ground ………… ………… 1980 ms 7060 Ω (±1%) to ground 2000 ms 8040 Ω (±1%) to ground 2000 ms > 8040 Ω (±1%) to ground 2000 ms Toggle ON/OFF / Flanking Sensor Suppression (FSS) VDD / Floating Toggle ON/OFF FSS Disabled Disabled Ground / Floating Enabled Disabled 1.5 kΩ (±5%) to ground Disabled Enabled 5.1 kΩ (±5%) to ground Enabled Enabled VDD Document Number: 001-57451 Rev. *E Delay Toggle/FSS Page 24 of 29 CY8CMBR2044 Table 15. ScanRate/Sleep Pin Hardware Configuration Resistor R (1%) in ohms Approximate ScanRate (in ms) Resistor R (1%) in ohms Approximate ScanRate (in ms) 60 185 310 435 560 685 810 935 1060 1185 1310 1435 1560 1685 1810 1935 2060 2185 2310 2435 2560 2685 2810 2935 3060 3185 3310 3435 3560 3685 3810 3935 20 22 24 27 30 34 38 42 46 51 55 61 66 71 77 83 89 96 102 107 115 122 129 137 144 152 159 167 175 183 192 200 4060 4185 4310 4435 4560 4685 4810 4935 5060 5185 5310 5435 5560 5685 5810 5935 6060 6185 6310 6435 6560 6685 6810 6935 7060 7185 7310 7435 7560 7685 7810 7935 209 217 226 235 244 253 263 272 282 291 301 311 321 331 341 352 362 373 383 394 405 416 427 438 449 461 472 484 495 507 519 531 Document Number: 001-57451 Rev. *E Page 25 of 29 CY8CMBR2044 Acronyms Acronym Document Conventions Description Units of Measure AC alternating current AI analog input AIO analog input/output °C degree Celsius AIDO analog input/digital output k kilohm DO digital output µA microampere P power pins µs microsecond milliampere Symbol Unit of Measure CF finger capacitance mA CP parasitic capacitance ms millisecond CS capsense mV millivolt FSS flanking sensor suppression GPO general purpose output nA nanoampere LSB least significant bit ohm MSB most significant bit PCB printed circuit board POR power on reset Numeric Naming POST power on self test RF radio frequency Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase 'h' (for example, '14h' or '3Ah'). Hexadecimal numbers may also be represented by a '0x' prefix, the C coding convention. Binary numbers have an appended lowercase 'b' (for example, 01010100b' or '01000011b'). Numbers not indicated by an 'h', 'b', or 0x are decimal. Document Number: 001-57451 Rev. *E pF picofarad V volt Page 26 of 29 CY8CMBR2044 Document History Page Document Title: CY8CMBR2044, Four Button CapSense® Controller Document Number: 001-57451 Rev. ECN No. Orig. of Change Submission Date ** 2807997 SLAN 12/03/2009 New data sheet. *A 2949368 SLAN 06/10/2010 Updated Features. Updated Overview. Updated Pinout. Updated Typical Circuits (Updated Schematic 1: 4-Buttons, 4-LEDs with Auto Reset Enabled and Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and Advanced Features Enabled). Updated Device Features (Added Table 2, updated Hardware Configuration (description), updated Flanking Sensor Suppression (FSS) (Added Figure 2), updated System Diagnostics (Added Figure 6, and Figure 8), added Serial Debug Data). Updated Power Consumption and Device Operating Modes (Updated Deep Sleep Mode (description)). Updated Layout Guidelines and Best Practices (Updated CapSense Button Shapes, updated Example PCB Layout Design with Four CapSense Buttons and Four LEDs). Updated Electrical Specifications. Added Ordering Code Definitions. Added Units of Measure. *B 2975370 SLAN 07/09/2010 Updated Features. Updated Pinout. Updated Typical Circuits. Updated Device Features (Updated LED ON Time (Updated Figure 4), updated System Diagnostics (Updated Figure 6, and Figure 8), updated Serial Debug Data (description)). Updated Power Consumption and Device Operating Modes (Updated Deep Sleep Mode (description)). *C 2996393 SLAN 07/29/2010 Updated Features. *D 3036873 ARVM 09/23/2010 Updated Typical Circuits (Updated Schematic 1: 4-Buttons, 4-LEDs with Auto Reset Enabled and Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and Advanced Features Enabled). Updated Layout Guidelines and Best Practices (Updated Example PCB Layout Design with Four CapSense Buttons and Four LEDs (Updated Figure 17)). Document Number: 001-57451 Rev. *E Description of Change Page 27 of 29 CY8CMBR2044 Document History Page (continued) Document Title: CY8CMBR2044, Four Button CapSense® Controller Document Number: 001-57451 Rev. ECN No. Orig. of Change Submission Date Description of Change *E 3624224 UDYG / SLAN 05/22/2012 Updated Title to read as “Four Button CapSense® Controller”. Updated Features. Updated Overview. Updated Pinout (Updated Table 1). Updated Typical Circuits (Updated Schematic 1: 4-Buttons, 4-LEDs with Auto Reset Enabled and Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and Advanced Features Enabled). Updated Device Features (Updated Table 2, updated CapSense Buttons, updated SmartSense Auto Tuning, updated General Purpose Outputs, removed Hardware Configuration, updated Toggle ON/OFF, updated Flanking Sensor Suppression (FSS), removed Delay Off, added LED ON Time, updated Button Auto Reset, renamed Failure Mode Analysis as System Diagnostics and updated the same section, renamed Debug Data as Serial Debug Data and updated the same section, renamed Device Operating Modes as Power Consumption and Device Operating Modes). Updated Layout Guidelines and Best Practices. Updated Electrical Specifications (Updated DC Electrical Characteristics (Updated DC Chip Level Specifications (Updated Note 6)), updated DC General Purpose I/O Specifications). Updated CapSense Specifications. Updated Ordering Information (Removed CapSense Block column). Updated Package Diagram. Added Appendix. Replaced all instances of sensor with button across the document. Updated in new template. Document Number: 001-57451 Rev. *E Page 28 of 29 CY8CMBR2044 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-57451 Rev. *E Revised May 22, 2012 Page 29 of 29 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.