fax id: 5218 51 CY7C09159 CY7C09169 PRELIMINARY 8K/16K x 9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 2 Flow-Through/Pipelined devices — 8K x 9 organization (CY7C09159) — 16K x 9 organization (CY7C09169) • 3 Modes — Flow-Through • High-speed clock to data access 6.5/7.5/12 ns (max.) • Low operating power — Active= 200 mA (typical) — Standby= 0.05 mA (typical) • Fully synchronous interface for easier operation • Burst counters increment addresses internally — Shorten cycle times — Minimize bus noise — Pipelined — Burst • Pipelined output mode on both ports allows fast 100-MHz cycle time • 0.35-micron CMOS for optimum speed/power • • • • — Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP v Logic Block Diagram R/WL R/WR OEL OER CE0L CE1L 1 1 0 0 0/1 1 0/1 FT/PipeL CE0R CE1R 0/1 0 0 1 0/1 9 FT/PipeR 9 I/O0L–I/O8L I/O0R–I/O8R I/O Control  I/O Control 13/14 13/14 A0–A12/13L CLKL ADSL Counter/ Address Register Decode CNTENL CNTRSTL Counter/ Address Register Decode True Dual-Ported RAM Array  A0–A12/13R CLKR ADSR CNTENR CNTRSTR Note: 1. A0–A12 for 8K; A0–A13 for 16K. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 1997 - Revised June 5, 1998 CY7C09159 CY7C09169 PRELIMINARY A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE 0 LOW and CE1 HIGH to reactivate the outputs. Functional Description The CY7C09159 and CY7C09169 are high speed synchronous CMOS 8K and 16K x 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.  Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 15 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s address strobe (ADS). When the port’s count enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transistion of that port’s clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter reset (CNTRST) is used to reset the burst counter. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. Note: 2. When simultaneously writing to the same location, final value cannot be guaranteed. 2 CY7C09159 CY7C09169 PRELIMINARY Pin Configurations NC A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L NC NC 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R [Note 3] A13L 9 67 A13R [Note 3] 66 NC NC 10 NC 11 NC 12 VCC 13 NC 14 62 NC NC 15 61 NC CY7C09169 (16K x 9) CY7C09159 (8K x 9) 65 NC 64 NC 63 GND NC 16 60 NC NC 17 59 NC CE0L 18 58 CE0R CE1L 19 57 CE1R CNTRSTL 20 56 CNTRSTR R/WL 21 55 R/WR OEL 22 54 OER FT/PIPEL 23 53 FT/PIPER NC 24 52 GND NC 25 51 NC Note: 3. This pin is NC for CY7C09159. 3 NC NC I/O8R I/O7R I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/01R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O8L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CY7C09159 CY7C09169 PRELIMINARY Selection Guide fMAX2 (MHz) (Pipelined) CY7C09159 CY7C09169 -6 CY7C09159 CY7C09169 -7 CY7C09159 CY7C09169 -12 100 83 50 Max Access Time (ns) (Clock to Data, Pipelined) 6.5 7.5 12 Typical Operating Current ICC (mA) 250 235 195 Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) 45 40 30 Typical Standby Current for ISB3 (mA) (Both Ports CMOS Level) 0.05 0.05 0.05 Pin Definitions Left Port Right Port Description A0L–A13L A0R–A13R Address Inputs. (A0−A12 for 8K; A0−A13 for 16K devices) ADSL ADSR Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during normal read or write transactions. Asserting this signal LOW also loads the burst address counter with data present on the I/O pins. CE0L,CE1L CE0R,CE1R Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). CLKL CLKR Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. CNTENL CNTENR Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRSTL CNTRSTR Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. I/O0L–I/O 8L I/O0R–I/O8R Data Bus Input/Output (I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices). OEL OER Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. R/WL R/WR Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FT/PIPEL FT/PIPE R Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground Input. NC No Connect. VCC Power Input. Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage ........................................... >2001V (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current..................................................... >200 mA Storage Temperature ................................. –65 °C to +150°C Ambient Temperature with Power Applied ..–55°C to +125°C Operating Range Supply Voltage to Ground Potential ............... –0.3V to +7.0V Range DC Voltage Applied to Outputs in High Z State ................................. –0.5V to +7.0V Commercial DC Input Voltage............................................ –0.5V to +7.0V Industrial 4 Ambient Temperature VCC 0°C to +70°C 5V ± 10% −40°C to +85°C 5V ± 10% CY7C09159 CY7C09169 PRELIMINARY Electrical Characteristics Over the Operating Range CY7C09159 CY7C09169 -6 Symbol Parameter Min VOH Output HIGH Voltage (VCC=Min, IOH=–4.0 mA) VOL Output LOW Voltage (VCC=Min, IOH= +4.0 mA) Input HIGH Voltage Input LOW Voltage IOZ Output Leakage Current ICC Operating Current (V CC=Max, IOUT=0 mA) Outputs Disabled Indust. Standby Current (Both Ports TTL Level) CEL & CER ≥ VIH, f=fMAX Indust. ISB3 Typ 10 250 Com’l. Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f=fMAX Com’l. Indust. Standby Current (Both Ports CMOS Level) CEL & CER ≥ V CC – 0.2V, f=0 Indust. Com’l. Com’l. −10 0.25 160 200 Indust. Units V V 0.8 −10 V 10 µA 235 420 195 300 mA 260 445 225 375 mA 10 235 0.05 0.4 2.2 115 175 Max V 0.8 450 45 Typ 0.4 2.2 −10 Min 2.4 0.8 Com’l. -12 Max 2.4 2.2 Standby Current (One Port CMOS Level) CEL | CER ≥ VIH, f=fMAX ISB4 Min 0.4 VIH ISB2 Max 2.4 VIL ISB1 -7 Typ 40 105 30 85 mA 55 120 45 100 mA 160 220 125 190 mA 175 235 140 205 mA 0.05 0.25 0.05 0.25 mA 0.05 0.25 0.05 0.25 mA 145 185 110 150 mA 160 200 125 165 mA Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF 10 pF AC Test Loads 5V 5V R1 = 893Ω OUTPUT OUTPUT C = 30 pF RTH = 250Ω R1 = 893Ω OUTPUT C = 30 pF R2 = 347Ω C = 5 pF VTH = 1.4V (a) Normal Load (Load 1) (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V GND 10% R2 = 347Ω (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) 90% 10% 90% ≤ 3 ns ≤ 3 ns Note: 4. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). 5 CY7C09159 CY7C09169 PRELIMINARY Switching Characteristics Over the Operating Range CY7C09159 CY7C09169 -6 Symbol fMAX1 fMAX2 tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Parameter fMax Flow-Through fMax Pipelined Clock Cycle Time - Flow-Through Clock Cycle Time - Pipelined Clock HIGH Time - Flow-Through Clock LOW Time - Flow-Through Clock HIGH Time - Pipelined Clock LOW Time - Pipelined Clock Rise Time Clock Fall Time Address Set-up Time Address Hold Time Chip Enable Set-up Time Chip Enable Hold Time R/W Set-up Time R/W Hold Time Input Data Set-up Time Input Data Hold Time ADS Set-up Time ADS Hold Time CNTEN Set-up Time CNTEN Hold Time CNTRST Set-up Time CNTRST Hold Time Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid - Flow-Through Clock to Data Valid - Pipelined Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z Min -7 Max Min 53 100 19 10 6.5 6.5 4 4 22 12 7.5 7.5 5 5 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 9 2 2 2 Units 33 50 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 4 1 4 1 4 1 4 1 4 1 4 1 4 1 9 2 1 Max 30 20 12 12 8 8 4 0 4 0 4 0 4 0 4 0 4 0 4 0 7 15 6.5 Min 3 3 8 2 2 2 Max 45 83 3 3 2 1 -12 7 18 7.5 9 12 2 1 2 2 2 7 25 12 9 Port to Port Delays tCWDD tCCS Write Port Clock HIGH to Read Data Delay Clock to Clock Set-up Time 30 9 6 35 10 40 15 ns ns CY7C09159 CY7C09169 PRELIMINARY Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V IL)[5,6,7,8] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W An ADDRESS An+1 An+2 An+3 tCKHZ tDC tCD1 DATAOUT Qn Qn+1 Qn+2 tDC tCKLZ tOHZ tOLZ OE tOE Read Cycle for Pipelined Operation (FT/PIPE = VIH)[5,6,7,8] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS DATAOUT An An+1 1 Latency An+2 An+3 tDC tCD2 Qn Qn+1 tOHZ tCKLZ Qn+2 tOLZ OE tOE Notes: 5. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 6. ADS = VIL, CNTEN and CNTRST = VIH. 7. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 8. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 7 CY7C09159 CY7C09169 PRELIMINARY Switching Waveforms (continued) Bank Select Pipelined Read[9,10] tCH2 tCYC2 tCL2 CLK L tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE 0(B1) tCD2 tHC tSC tCD2 tHA tSA ADDRESS (B2) tDC A0 A1 tDC tCKLZ A3 A2 tCKHZ D3 D1 D0 DATAOUT(B1) tCD2 tCKHZ A4 A5 tHC tSC CE 0(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 D4 D2 tCKLZ tCKLZ Left Port Write to Flow-Through Right Port Read[11,12,13,14] CLK L tSW tHW tSA tHA R/WL ADDRESS L NO MATCH MATCH tHD tSD DATAINL VALID tCCS CLKR R/WR ADDRESSR tCD1 tSW tSA tHW tHA NO MATCH MATCH tCWDD tCD1 DATAOUTR VALID tDC VALID tDC Notes: 9. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2. Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 10. OE and ADS = VIL ; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 11. The same waveforms apply for a right port write to flow-through left port read. 12. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 13. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 14. It t CCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. t CWDD does not apply in this case. 8 CY7C09159 CY7C09169 PRELIMINARY Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = VIL)[8,12,15,16] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA An+2 An+2 An+3 An+4 tSD tHD tHA DATAIN tCD2 tCKHZ Dn+2 tCD2 tCKLZ Qn DATAOUT READ Qn+3 NO OPERATION WRITE READ Pipelined Read-to-Write-to-Read (OE Controlled)[8,12,15,16] tCH2 tCYC2 tCL2 CLK CE 0 tSC tHC CE 1 R/W tSW tHW tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA tHA tSD tHD Dn+2 DATAOUT Dn+3 tCD2 DATAIN tCKLZ tCD2 Qn Qn+4 tOHZ OE READ WRITE READ Notes: 15. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. 16. During “No operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. 9 CY7C09159 CY7C09169 PRELIMINARY Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read (OE = VIL)[6,8,12,15] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA DATAIN An+2 An+2 tSD tHA An+3 tHD Dn+2 tCD1 tCD1 DATAOUT An+4 tCD1 Qn Qn+1 tDC tCKHZ READ tCD1 Qn+3 tCKLZ NO OPERATION WRITE tDC READ Flow-Through Read-to-Write-to-Read (OE Controlled)[6,8,12,15] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA DATAIN DATAOUT tSD tHA Dn+2 tDC tCD1 tHD Dn+3 tOE tCD1 Qn tCD1 Qn+4 tOHZ tCKLZ tDC OE READ WRITE 10 READ CY7C09159 CY7C09169 PRELIMINARY Switching Waveforms (continued) Pipelined Read with Address Counter Advance tCH2 tCYC2 tCL2 CLK tSA tHA ADDRESS An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx-1 tCD2 Qx READ EXTERNAL ADDRESS Qn Qn+1 tDC READ WITH COUNTER Qn+2 COUNTER HOLD Qn+3 READ WITH COUNTER Flow-Through Read with Address Counter Advance tCH1 tCYC1 tCL1 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATA OUT tHCN tCD1 Qx Qn Qn+1 Qn+2 Qn+3 tDC READ EXTERNAL ADDRESS READ WITH COUNTER Note: 17. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. 11 COUNTER HOLD READ WITH COUNTER CY7C09159 CY7C09169 PRELIMINARY Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[18,19] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD tHD WRITE EXTERNAL ADDRESS Dn+1 Dn+1 WRITE WITH COUNTER Dn+2 WRITE COUNTER HOLD Dn+3 WRITE WITH COUNTER Notes: 18. CE0 and R/W = VIL ; CE1 and CNTRST = VIH. 19. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH. 12 Dn+4 CY7C09159 CY7C09169 PRELIMINARY Switching Waveforms (continued) Counter Reset (Pipelined Outputs)[8,15,20,21] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS AX 0 tSW tHW tSD tHD 1 An+1 An An+1 R/W tSAD tHAD tSCN tHCN tSRST tHRST ADS CNTEN CNTRST DATAIN D0 DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Notes: 20. CE0 = VIL; CE1 = VIH. 21. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 13 Q1 READ ADDRESS n Qn CY7C09159 CY7C09169 PRELIMINARY Read/Write and Enable Operation[22,23,24] Inputs OE CLK Outputs CE0 CE1 R/W I/O 0–I/O8 X H X X High-Z Deselected X X L X High-Z Deselected X L H L DIN L L H H DOUT Read L H X High-Z Outputs Disabled H X Operation Write Address Counter Control Operation[22,26,27,28] Address Previous Address ADS CNTEN CNTRST I/O Mode X X X X L Dout(0) Reset Counter Reset to Address 0 An X L X H Dout(n) Load Address Load into Counter X An H H H Dout(n) Hold External Address Blocked—Counter Disabled X An H L H Dout(n+1) Increment Counter Enabled—Internal Address Generation CLK Notes: 22. “X” = Don’t Care, “H” = VIH, “L” = VIL. 23. ADS, CNTEN, CNTRST = Don’t Care. 24. OE is an asynchronous input signal. 25. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 26. CE0 and OE = VIL; CE1 and R/W = VIH. 27. Data shown for Flow-through mode; pipelined mode output will be delayed by one cycle. 28. Counter operation is independent of CE0 and CE1. 14 Operation CY7C09159 CY7C09169 PRELIMINARY Ordering Information 8K x9 Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5 CY7C09159-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5 CY7C09159-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09159-7AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09159-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09159-12AI A100 100-Pin Thin Quad Flat Pack Industrial 12 16K x9 Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5 CY7C09169-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5 CY7C09169-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09169-7AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09169-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09169-12AI A100 100-Pin Thin Quad Flat Pack Industrial 12 Document #: 38–00671–B Package Diagram 100-Pin Thin Quad Flat Pack A100 © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.