CYPRESS FM28V102

Preliminary
FM28V102
1Mbit (64K×16)F-RAM Memory
FEATURES
1Mbit Ferroelectric Nonvolatile RAM
Organized as 64Kx16
Configurable as 128Kx8 Using /UB, /LB
1014 Read/Write Cycles
NoDelay™ Writes
Page Mode Operation to 33MHz
Advanced High-Reliability Ferroelectric Process
SRAM Compatible
Industry Std. 64Kx16 SRAM Pinout
60 ns Access Time, 90 ns Cycle Time
Superior to Battery-backed SRAM Modules
No Battery Concerns
Monolithic Reliability
True Surface Mount Solution, No Rework Steps
Superior for Moisture, Shock, and Vibration
Low Power Operation
2.0V – 3.6V Power Supply
Standby Current 120 A (typ)
Active Current 7 mA (typ)
Industry Standard Configuration
Industrial Temperature -40 C to +85 C
44-pin “Green”/RoHS TSOP-II package
DESCRIPTION
Pin Configuration
The FM28V102 is a 64Kx16 nonvolatile memory that
reads and writes like a standard SRAM. A
ferroelectric random access memory or F-RAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and high write endurance make the
F-RAM superior to other types of memory.
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VDD
VSS
DQ4
DQ5
DQ6
DQ7
WE
VSS
A15
A14
A13
A12
In-system operation of the FM28V102 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The F-RAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM28V102 ideal
for nonvolatile memory applications requiring
frequent or rapid writes in the form of an SRAM.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
VSS
VDD
DQ11
DQ10
DQ9
DQ8
/ZZ
A8
A9
A10
A11
NC
The device is available in a 400 mil 44-pin TSOP-II
surface mount package. Device specifications are
guaranteed over industrial temperature range –40°C
to +85°C.
This is a product in the pre-production phase of development. Device characterization is complete and Ramtron does not expect to
change the specifications. Ramtron will issue a Product Change Notice if any specification changes are made.
Cypress Semiconductor Corporation
•
Document Number: 001-86601 Rev. **
198 Champion Court
•
San Jose, CA 95134-1709 • 408-943-2600
Revised March 12, 2013
A(15:2)
...
A(15:0)
Block & Row Decoder
Address Latch & Write Protect
FM28V102 - 64Kx16 F-RAM
16K x 64
F-RAM Array
A(1:0)
...
Column Decoder
CE1, CE2
DQ(15:0)
I/O Latch & Bus Driver
WE
UB, LB
Control
Logic
2
OE
ZZ
Figure 1. Block Diagram
PIN DESCRIPTION
Pin Name
A(15:0)
Type
Input
/CE
Input
/WE
Input
/OE
Input
/ZZ
Input
DQ(15:0)
/UB
I/O
Input
/LB
Input
VDD
VSS
Supply
Supply
Pin Description
Address inputs: The 16 address lines select one of 64K words in the F-RAM array. The lowest
two address lines A(1:0) may be used for page mode read and write operations.
Chip Enable inputs: The device is selected and a new memory access begins on the falling
edge of /CE. The entire address is latched internally at this point. Subsequent changes to the
A(1:0) address inputs allow page mode operation.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM28V102 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE
latches a new column address for page mode write cycles.
Output Enable: When /OE is low, the FM28V102 drives the data bus when valid read data is
available. Deasserting /OE high tri-states the DQ pins.
Sleep: When /ZZ is low, the device enters a low power sleep mode for the lowest supply
current condition. Since this input is logically AND’d with /CE, /ZZ must be high for normal
read/write operation. The /ZZ pin is internally pulled up.
Data: 16-bit bi-directional data bus for accessing the F-RAM array.
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z if /UB
is high. If the user does not perform byte writes and the device is not configured as a 128Kx8,
the /UB and /LB pins may be tied to ground.
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z if /LB
is high. If the user does not perform byte writes and the device is not configured as a 128Kx8,
the /UB and /LB pins may be tied to ground.
Supply Voltage
Ground
Document Number: 001-86601 Rev. **
Page 2 of 16
FM28V102 - 64Kx16 F-RAM
Table 1. Functional Truth Table 1,2
/CE
/WE
A(15:2)
A(1:0)
X
X
X
X
H
X
X
X
X
X
X
X
H
V
V
H
V
V
L
L
H
No Change
Change
L
H
Change
V
L
V
V
L
V
V
L
L
V
V
L
No Change
V
X
X
X
X
X
X
L
/ZZ
L
H
Operation
Sleep Mode
Standby/Idle
H
Read
H
H
H
Page Mode Read
Random Read
/CE-Controlled Write 2
H
H
H
/WE-Controlled Write 2, 3
Page Mode Write 4
Starts Precharge
Notes:
1)
2)
3)
4)
H=Logic High, L=Logic Low, V=Valid Data, X=Don’t Care.
For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.
/WE-controlled write cycle begins as a Read cycle and A(15:2) is latched then.
Addresses A(1:0) must remain stable for at least 15 ns during page mode operation.
Table 2. Byte Select Truth Table
/WE
/OE
/LB
/UB
H
H
X
X
X
H
H
H
L
H
L
L
H
L
L
L
X
H
L
L
H
L
L
Operation
Read; Outputs Disabled
Read upper byte; Hi-Z lower byte
Read lower byte; Hi-Z upper byte
Read both bytes
Write upper byte; Mask lower byte
Write lower byte; Mask upper byte
Write both bytes
The /UB and /LB pins may be grounded if 1) the system does not perform byte writes
and 2) the device is not configured as a 128Kx8.
Simplified Sleep/Standby State Diagram
Power
Applied
Initialize
/CE high,
/ZZ high
/CE low,
/ZZ high
Standby
/CE high,
/ZZ high
/ZZ low
Normal
Operation
/ZZ low
Sleep
Document Number: 001-86601 Rev. **
/CE low,
/ZZ high
/ZZ high
Page 3 of 16
FM28V102 - 64Kx16 F-RAM
OVERVIEW
The FM28V102 is a wordwide F-RAM memory
logically organized as 65,536 x 16 and accessed using
an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page requires that
either /CE transitions low or the upper address
A(15:2) changes.
Memory Operation
Users access 65,536 memory locations, each with 16
data bits through a parallel interface. The F-RAM
array is organized as 16,384 rows each having 64
bits. Each row has 4 column locations, which allows
fast access in page mode operation. Once an initial
address has been latched by the falling edge of /CE,
subsequent column locations may be accessed
without the need to toggle /CE. When /CE is
deasserted high, a precharge operation begins. Writes
occur immediately at the end of the access with no
delay. The /WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile
memory array immediately, which is a feature unique
to F-RAM called NoDelayTM writes.
Read Operation
A read operation begins on the falling edge of /CE.
The falling edge of /CE causes the address to be
latched and starts a memory read cycle if /WE is high.
Data becomes available on the bus after the access
time has been satisfied. Once the address has been
latched and the access completed, a new access to a
random location (different row) may begin while /CE
is still low. The minimum cycle time for random
addresses is tRC. Note that unlike SRAMs, the
FM28V102’s /CE-initiated access time is faster than
the address cycle time.
The FM28V102 will drive the data bus when /OE and
at least one of the byte enables (/UB, /LB) is asserted
low. The upper data byte is driven when /UB is low,
and the lower data byte is driven when /LB is low. If
/OE is asserted after the memory access time has been
satisfied, the data bus will be driven with valid data.
If /OE is asserted prior to completion of the memory
access, the data bus will not be driven until valid data
is available. This feature minimizes supply current in
the system by eliminating transients caused by invalid
data being driven onto the bus. When /OE is
deasserted high, the data bus will remain in a high-Z
state.
Write Operation
Document Number: 001-86601 Rev. **
Writes occur in the FM28V102 in the same time
interval as reads. The FM28V102 supports both /CEand /WE-controlled write cycles. In both cases, the
address A(15:2) is latched on the falling edge of /CE.
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the device begins the
memory cycle as a write. The FM28V102 will not
drive the data bus regardless of the state of /OE as
long as /WE is low. Input data must be valid when
/CE is deasserted high. In a /WE-controlled write, the
memory cycle begins on the falling edge of /CE. The
/WE signal falls some time later. Therefore, the
memory cycle begins as a read. The data bus will be
driven if /OE is low, however it will hi-Z once /WE is
asserted low. The /CE- and /WE-controlled write
timing cases are shown in the Electrical
Specifications section.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the rising edge of /WE or /CE,
whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to deasserting /WE or /CE. Data setup time
indicates the interval during which data cannot
change prior to the end of the write access (rising
edge of /WE or /CE).
Unlike other truly nonvolatile memory technologies,
there is no write delay with F-RAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Data polling, a technique used with
EEPROMs to determine if a write is complete, is
unnecessary.
Page Mode Operation
The F-RAM array is organized as 16,384 rows each
having 64 bits. Each row has 4 column address
locations. Address inputs A(1:0) define the column
address to be accessed. An access can start on any
column address, and other column locations may be
accessed without the need to toggle the /CE pin. For
fast access reads, once the first data byte is driven
onto the bus, the column address inputs A(1:0) may
be changed to a new value. A new data byte is then
driven to the DQ pins no later than tAAP, which is less
than half the initial read access time. For fast access
writes, the first write pulse defines the first write
access. While /CE is low, a subsequent write pulse
along with a new column address provides a page
mode write access.
Page 4 of 16
FM28V102 - 64Kx16 F-RAM
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is being prepared for a
new access. Precharge is user-initiated by driving the
/CE signal high. It must remain high for at least the
minimum precharge time tPC.
Precharge is also activated by changing the upper
addess A(15:2). The current row is first closed prior
to accessing the new row. The device automatically
detects an upper order address change which starts a
precharge operation, the new address is latched, and
the new read data is valid within the tAA address
access time. Refer to the Read Cycle Timing 1
diagram. Likewise a similar sequence occurs for write
cycles. Refer to the Write Cycle Timing 3 diagram.
Sleep Mode
The device incorporates a sleep mode of operation
which allows the user to achieve the lowest power
supply current condition. It enters a low power sleep
mode by asserting the /ZZ pin low. Read and write
operations must complete prior to the /ZZ pin going
low. Once /ZZ is low, all pins are ignored except the
/ZZ pin. When /ZZ is deasserted high, there is some
time delay (tZZEX) before the user can access the
device.
If Sleep Mode is not used, the /ZZ pin may be floated
(internal pullup) or tied to VDD.
Figure 2. Use of Pullup Resistor on /WE
SRAM Drop-In Replacement
The FM28V102 has been designed to be a drop-in
replacement for standard asynchronous SRAMs. The
device does not require /CE to toggle for each new
address. /CE may remain low indefinitely. While /CE
is low, the device automatically detects address
changes and a new access is begun. This functionality
allows /CE to be grounded as you might with an
SRAM. It also allows page mode operation at speeds
up to 33MHz. Note that if /CE is tied to ground,
the user must be sure /WE is not low at powerup
or powerdown events. If /CE and /WE are both
low during power cycles, data corruption will
occur. Figure 5 shows a pullup resistor on /WE
which will keep the pin high during power cycles
assuming the MCU/MPU pin tri-states during the
reset condition. The pullup resistor value should
be chosen to ensure the /WE pin tracks VDD yet a
high enough value that the current drawn when
/WE is low is not an issue. A 10Kohm resistor
draws 330uA when /WE is low and VDD=3.3V.
Note that software write-protect is not available to
the user if the chip enable pins are hardwired
active.
VDD
The rate at which random addresses can be issued is
tRC and tWC, respectively.
For applications that require the lowest power
consumption, the /CE signal should be active (low)
only during memory accesses. The FM28V102
draws supply current while /CE is low, even if
addresses and control signals are static. While /CE is
high, the device draws no more than the maximum
standby current ISB.
The FM28V102 is compatible with the 2Mbit
FM28V202 device. There are some differences in the
timing specifications. Please refer to the FM28V202
datasheet.
The /UB and /LB byte select pins are active for both
read and write cycles. They may be used to allow the
device to be wired as a 128Kx8 memory. The upper
and lower data bytes can be tied together and
controlled with the byte selects. Individual byte
enables or the next higher address line A(16) may be
available from the system processor.
FM28V102
R
MCU/
MPU
CE
WE
OE
A(15:0)
DQ
Document Number: 001-86601 Rev. **
Page 5 of 16
FM28V102 - 64Kx16 F-RAM
/CE
/WE
/OE
A(16)
A(15:0)
due to the inductance of the leadframe. It is best to
use a chip capacitor that has a low ESR and has good
high frequency characteristics.
/ZZ
1Mbit FRAM
FM28V102
/UB
/LB
A(15:0)
DQ(15:8)
D(7:0)
DQ(7:0)
Figure 3. FM28V102 Wired as 128Kx8
PCB Layout Recommendations
A 0.1uF decoupling capacitor should be placed close
to pin 11 (VDD) and the ground side of the capacitor
should be connected to either a ground plane or low
impedance path back to pin 12 (VSS). The same
should be done to the other side at pins 33 and 34.
This is especially important for the TSOP-II package
Document Number: 001-86601 Rev. **
If the controller drives the address and chip enable
from the same timing edge, it is best to keep the
address routes short and of equal length. A simple RC
circuit may be inserted in the chip enable path to
provide some delay and timing margin for the
FM28V102’s address setup time tAS.
As a general rule, the layout designer may need to
add series termination resistors to controller outputs
that have fast transitions or routes that are > 15cm in
length. This is only necessary if the edge rate is less
than or equal to the round trip trace delay. Signal
overshoot and ringback may be large enough to cause
erratic device behavior. It is best to add a 50 ohm
resistor (30 – 60 ohms) near the output driver
(controller) to reduce such transmission line effects.
Page 6 of 16
FM28V102 - 64Kx16 F-RAM
ENDURANCE
The FM28V102 is capable of being accessed at least
1014 times – reads or writes. An F-RAM memory
operates with a read and restore mechanism.
Therefore, an endurance cycle is applied on a row
basis. The F-RAM architecture is based on an array
of rows and columns. Rows are defined by A15-A2
and column addresses by A1-A0. The array is
organized as 16K rows of 4-words each. The entire
row is internally accessed once whether a single 16bit word or all four words are read or written. Each
word in the row is counted only once in an endurance
calculation.
The user may choose to write CPU instructions and
run them from a certain address space. The table
below shows endurance calculations for 256-byte
repeating loop, which includes a starting address, 3
page mode accesses, and a CE precharge. The
number of bus clocks needed to complete a 4-word
transaction is 4+1 at lower bus speeds, but 5+2 at
33MHz due to initial read latency and an extra clock
to satisfy the device’s precharge timing constraint tPC.
The entire loop causes each byte to experience only
one endurance cycle.
F-RAM read and write
endurance is virtually unlimited even at 33MHz
system bus clock rate.
Table 3. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop
Bus Freq Bus Cycle
256-byte
Endurance
Endurance
Years to
(MHz)
Time (ns) Transaction Cycles/sec.
Cycles/year
Reach 1014
Cycles
Time ( s)
30
10.56
33
94,690
2.98 x 1012
33.5
40
12.8
40.6
25
78,125
2.46 x 1012
10
100
28.8
34,720
1.09 x 1012
91.7
5
200
57.6
17,360
5.47 x 1011
182.8
Document Number: 001-86601 Rev. **
Page 7 of 16
FM28V102 - 64Kx16 F-RAM
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any signal pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
Package Moisture Sensitivity Level
Ratings
-1.0V to +4.5V
-1.0V to +4.5V and
VIN < VDD+1V
-55 C to +125 C
260 C
TBD
TBD
TBD
MSL-3
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40 C to + 85 C, VDD = 2.0V to 3.6V unless otherwise specified)
Symbol Parameter
Min
Typ
Max
Units Notes
VDD
Power Supply
2.0
3.3
3.6
V
IDD
VDD Supply Current
7
12
mA
1
ISB
Standby Current
2
A
@ TA = 25°C
120
150
A
@ TA = 85°C
250
IZZ
Sleep Mode Current
3
@ TA = 25°C
3
5
A
@ TA = 85°C
8
A
ILI
Input Leakage Current
4
1
A
ILO
Output Leakage Current
4
1
A
VIH1
Input High Voltage (VDD=2.7V to 3.6V)
2.2
VDD + 0.3
V
VIH2
Input High Voltage (VDD=2.0V to 2.7V)
0.7*VDD
V
VIL1
Input Low Voltage (VDD=2.7V to 3.6V)
-0.3
0.8
V
VIL2
Input Low Voltage (VDD=2.0V to 2.7V)
-0.3
0.3*VDD
V
VOH1
Output High Voltage (IOH = -1 mA, VDD>2.7V)
2.4
V
VOH2
Output High Voltage (IOH = -100 A)
VDD-0.2
V
VOL1
Output Low Voltage (IOL = 2 mA, VDD>2.7V)
0.4
V
VOL2
Output Low Voltage (IOL = 150 A)
0.2
V
RIN
Address Input Resistance (/ZZ)
5
For VIN = VIH (min)
40
K
For VIN = VIL (max)
1
M
Notes
1. VDD = 3.6V, /CE cycling at min. cycle time. All inputs toggling at CMOS levels (0.2V or VDD-0.2V), all DQ pins unloaded.
2. VDD = 3.6V, /CE at VDD, All other pins are static and at CMOS levels (0.2V or VDD-0.2V), /ZZ is high.
3. VDD = 3.6V, /ZZ is low, all other inputs at CMOS levels (0.2V or V DD-0.2V).
4. VIN, VOUT between VDD and VSS.
5. The input pull-up circuit is stronger (>40K ) when the input voltage is above VIH and weak (>1M ) when the input
voltage is below VIL.
Document Number: 001-86601 Rev. **
Page 8 of 16
FM28V102 - 64Kx16 F-RAM
Read Cycle AC Parameters (TA = -40 C to + 85 C, unless otherwise specified)
VDD 2.0 to 2.7V
VDD 2.7 to 3.6V
Symbol Parameter
Min
Max
Min
Max
tRC
Read Cycle Time
105
90
tCE
Chip Enable Access Time
70
60
tAA
Address Access Time
105
90
tOH
Output Hold Time
20
20
tAAP
Page Mode Address Access Time
40
30
tOHP
Page Mode Output Hold Time
3
3
tCA
Chip Enable Active Time
70
60
tPC
Precharge Time
35
30
tBA
/UB, /LB Access Time
25
15
tAS
Address Setup Time (to /CE low)
0
0
tAH
Address Hold Time (/CE-controlled)
70
60
tOE
Output Enable Access Time
25
15
tHZ
Chip Enable to Output High-Z
15
10
tOHZ
Output Enable High to Output High-Z
15
10
tBHZ
/UB, /LB High to Output High-Z
15
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write Cycle AC Parameters (TA = -40 C to + 85 C, unless otherwise specified)
VDD 2.0 to 2.7V
VDD 2.7 to 3.6V
Symbol Parameter
Min
Max
Min
Max
tWC
Write Cycle Time
105
90
tCA
Chip Enable Active Time
70
60
tCW
Chip Enable to Write Enable High
70
60
tPC
Precharge Time
35
30
tPWC
Page Mode Write Enable Cycle Time
40
30
tWP
Write Enable Pulse Width
22
18
tWP2
/UB, /LB Pulse Width
22
18
tWP3
/WE Low to /UB, /LB High
22
18
tAS
Address Setup Time (to /CE low)
0
0
tAH
Address Hold Time (/CE-controlled)
70
60
tASP
Page Mode Address Setup Time (to /WE low)
8
5
tAHP
Page Mode Address Hold Time (to /WE low)
20
15
tWLC
Write Enable Low to Chip Disabled
30
25
tBLC
/UB, /LB Low to Chip Disabled
30
25
tWLA
Write Enable Low to A(15:2) Change
30
25
tAWH
A(15:2) Change to Write Enable High
105
90
tDS
Data Input Setup Time
20
15
tDH
Data Input Hold Time
0
0
tWZ
Write Enable Low to Output High Z
10
10
tWX
Write Enable High to Output Driven
8
5
tBDS
Byte Disable Setup Time (to /WE low)
8
5
tBDH
Byte Disable Hold Time (to /WE high)
8
5
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1
1
1
Notes
1. This parameter is characterized but not 100% tested.
Capacitance
Symbol
CI/O
CIN
CZZ
(TA = 25 C , f=1 MHz, VDD = 3.3V)
Parameter
Input/Output Capacitance (DQ)
Input Capacitance
Input Capacitance of /ZZ pin
Document Number: 001-86601 Rev. **
Min
-
Max
8
6
8
Units
pF
pF
pF
Notes
Page 9 of 16
FM28V102 - 64Kx16 F-RAM
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
0 to 3V
3 ns
Input and Output Timing Levels
Output Load Capacitance
1.5V
30pF
Read Cycle Timing 1 (/CE low, /OE low)
tRC
tRC
A(15:0)
tOH
tAA
tAA
tOH
Previous Data
DQ(15:0)
Valid Data
Valid Data
Read Cycle Timing 2 (/CE-controlled)
tCA
tPC
CE
tAH
tAS
A(15:0)
tOE
tHZ
OE
tCE
tOHZ
tOH
DQ(15:0)
tBA
tBHZ
UB / LB
Page Mode Read Cycle Timing
tPC
tCA
CE
tAS
A(15:2)
A(1:0)
Col 0
Col 1
tOE
OE
Col 2
tAAP
tHZ
tCE
DQ(15:0)
tOHZ
tOHP
Data 0
Data 1
Data 2
Although sequential column addressing is shown, it is not required.
Document Number: 001-86601 Rev. **
Page 10 of 16
FM28V102 - 64Kx16 F-RAM
Write Cycle Timing 1 (/WE-Controlled) Note: /OE (not shown) is low only to show effect of /WE on DQ pins
tCA
tPC
tCW
CE
tAS
tWLC
A(15:0)
tWP
tWX
WE
DQ(15:0)
tDH
tDS
tHZ
tWZ
D out
D in
D out
Write Cycle Timing 2 (/CE-Controlled)
tCA
tPC
CE
tBLC
tAS
A(15:0)
WE
tDS
DQ(15:0)
tDH
D in
UB/LB
Write Cycle Timing 3 (/CE low) Note: /OE (not shown) is low only to show effect of /WE on DQ pins
tWC
tAWH
A(15:0)
tWLA
WE
tWX
tWZ
DQ(15:0)
D out
Document Number: 001-86601 Rev. **
tDS
D in
tDH
D out
D in
Page 11 of 16
FM28V102 - 64Kx16 F-RAM
Write Cycle Timing 4 (/CE low) Note: /UB and /LB to show byte enable and byte masking cases.
A(15:0)
tWP3
WE
tBDS
tBDH
tWP2
UB/LB
tDS
DQ(15:0)
tDS
tDH
D in
tDH
D in
Page Mode Write Cycle Timing
tCA
tPC
tCW
CE
tWLC
tAS
A(15:2)
tASP
tAHP
A(1:0)
Col 0
Col 1
Col 2
tPWC
tWP
WE
OE
tDH
tDS
DQ(15:0)
Data 0
Data 1
Data 2
Although sequential column addressing is shown, it is not required.
Document Number: 001-86601 Rev. **
Page 12 of 16
FM28V102 - 64Kx16 F-RAM
Power Cycle and Sleep Mode Enter/Exit Timing
VDD
CE
VDD min.
VDD min.
t ZZEN
t PU
t ZZEX
R/W
Allowed
t ZZEX
R/W
Allowed
R/W
Allowed
t ZZL
ZZ
t WEZZ
t PD
WE
t ZZH
DQ
D out
D in
Power Cycle and Sleep Mode Timing (TA = -40 C to + 85 C, VDD = 2.0V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Max
Units Notes
tPU
Power Up (after VDD min. is reached) to First Access Time
1
ms
tPD
Last Write (/WE high) to Power Down Time
0
s
tVR
VDD Rise Time
50
1,2
s/V
tVF
VDD Fall Time
100
1,2
s/V
tZZH
/ZZ Active to DQ Hi-Z Time
20
ns
tWEZZ
Last Write to Sleep Mode Entry Time
0
s
tZZL
/ZZ Active Low Time
1
s
tZZEN
Sleep Mode Entry Time (/ZZ low to /CE don’t care)
0
s
tZZEX
Sleep Mode Exit Time (/ZZ high to 1st access after wakeup)
450
s
Notes
1. Slope measured at any point on VDD waveform.
Data Retention (TA = -40 C to + 85 C)
Parameter
Data Retention
Document Number: 001-86601 Rev. **
Min
10
Units
Years
Notes
Page 13 of 16
FM28V102 - 64Kx16 F-RAM
MECHANICAL DRAWING
44-pin TSOP-II (Complies with JEDEC Standard MS-024g Var. AC)
Recommended PCB Footprint
Pin 1
0.45
0.30
18.41
BASIC
0.80
BSC
0.8
0.5
1.50
10.16 BSC
11.96
11.56
12.6
1.20 max
0.15
0.05
0.20
0.12
0.10 mm
0°-8°
0.6
0.4
Note: All dimensions in millimeters.
TSOP-II Package Marking Scheme
RAMTRON
XXXXXXX-PT
LLLLLLL
YYWW
Legend:
XXXXXX= part number, P=package, T=temperature (blank=ind., C=comm.)
R=rev code, LLLLLL= lot code, YY=year, WW=work week
Examples: FM28V102, “Green”/RoHS TSOP-II package,
Rev A, Lot 6340282, Year 2012, Work Week 25
RAMTRON
FM28V102-TG
A6340282TG
1225
Document Number: 001-86601 Rev. **
Page 14 of 16
FM28V102 - 64Kx16 F-RAM
REVISION HISTORY
Revision
1.0
Date
6/12/2012
Summary
Initial release.
ORDERING INFORMATION
Part Number
Features
FM28V102-TG
60 ns access, sleep
mode
Operating
Voltage
2.0-3.6V
Operating
Temp.
-40C to +85C
Package
44-pin “Green”/RoHS TSOP-II
Document History
Document Title: FM28V102 1Mbit (64K×16) F-RAM Memory
Document Number: 001-86601
Revision
ECN
Orig. of
Change
Submissio
n Date
**
3930342
GVCH
03/12/2013
Document Number: 001-86601 Rev. **
Description of Change
New Spec
Page 15 of 16
FM28V102 - 64Kx16 F-RAM
Sales, Solutions, and Legal Information
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Document Number: 001-86601 Rev. **
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