TTL
MEMORIES
SERIES 54S/74S
RANDOM-ACCESS READ/WRITE MEMORIES
BULLETIN NO. DL.S 7512257 , MAY 1975
64 BITS (16 WORDS BV 4 BITS)
'S189 , 'S289
ADA
1
CE
2
R/W
U
丁 16
256 BITS (256 WORDS BV 1 BIT)
'S201. 'S301
VCC
ADA
15
AD B
AD B 2
1
U
1024 BITS (1024 WORDS BV 1 BI Tl
SN74S209 , SN74S309
16 VCC
15
AD C
CE
1
ADA 2
U
16
15
VCC
DI
R/W
3
14
ADC
CE1
3
14
AD H
AD B 3
14
DI 1 4
13
AD D
CE2 4
13
DI
AD C 4
13
AD J
D01
5
12
DI4
CE3
12
R/W
AD D 5
12
AD 1
DI2 6
11
D04
DO 6
11
AD G
AD E 6
11
AD H
D02 7
10
DI3
AD D 7
10
AD F
DO 7
10
AD G
GND 8
9
D03
GND
9
AD E
GND 8
9
AD F
5
8
Pin assignments for all of these memories are the same for all packages.
回
•
Schottky-Clamped for High Performance
•
Full On-Chip Decoding and Fast Chip-Enable Simplify System Decoding
•
P-N-P Inputs Reduce Loading on System Buffers/Drivers
•
Choice of 3-State or Open-Collector Outputs
TVPE NUMBER (PACKAGES)
0
。Oc to 70 C
-55 0 C to 1250 C
SN54S189(J , W) SN74S189(J , N)
SN54S289(J , W) SN74S289(J , N)
SN54S201 (J , W) SN74S20 1( J , N)
SN54S301 (J , W) SN74S301 (J , N)
SN74S209(J , N)
SN74S309(J , N)
TVPE OF
BITSIZE
TVPICAL ACCESS TIMES WRITE CVCLE TIME
OUTPUT(S)
(ORGANIZATIONS) CHIP-SELECT ADDRESS SN54S'
SN74S'
3-State
64 Bits
25 ns
25 ns
12 ns
25 ns
Open-Collector
(16Wx4B)
3-State
256 Bits
13 ns
42 ns
100 ns
65 ns
(256W x 1 B)
Open-Collector
3-State
1024 Bits
20 ns
70 ns
150 ns
Open-Collector
(1024W x 1 B)
description
These monolithic TTL memories feature Schottky clamping for high performance , a fast chip-select access time to
enhance decoding at the system level , and the 'S201 and 'S209 RAMs utilize inverted-cell memory elements to achieve
high densities. The memories feature p-n-p input transistors that reduce the low-Ievel input current requirement to a
maximum of -0.25 milliamperes , only one-eighth that of a Series 54S /7 4S standard load factor.
A three-state-output version and an open-collector-output version are offered for each of the three organizations_ A
three-state output offers the convenience of an open-collector output with the speed of a totem-pole output; it can be
bus-connected to other similar outputs , yet it retains the fast rise time characteristic of the TTL totem-pole output_ An
open-collector output offers the capability of direct interface with a data line having a passive pull-up.
write cycle
Information to be stored in the memory is written into the selected address (AD) location when the chip-enable (CE)
and the read/write (R/W) inputs are low. While the read/write input is low , the memory output(s) is(are) off
(three-state = Hi-Z , open-collector = high l. When a number of outputs are bus-connected , this off state neither loads nor
drives the data bus; however , it permits the bus line to be driven by other active outputs or a passivc pull-up_
read cγcle
Information stored in the memory (see function table for input/output phase relationship) is available at the output(s)
when the read/write input is high and the chip-enable input(s) is(are) low_ When one(or more) chip-enable input is(are)
high , the output(s) will be off_
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SERIES 54S/74S
RANDOM-ACCESS READ/WRITE MEMORIES
FUNCTION TABLE
INPUTS
FUNCTION
READ/
'S189
'S289
ENABLEt
WRITE
'S201
'S301
Write
L
L
Read
L
H
H
X
Inhibit
H
~
high level , L
~
OUTPUTS
CHIP
low level , X
~
SN74S209
High Impedance I H
SN74S309
High Impedance I H
Complement of
Complement of
Data Entered
Data Entered
Data Entered
High Impedance IH
Data Entered
High Impedance I H
irrelevant
t For chip-enable of 'S201 and 'S301: L ~ all
CE
inputs low , H ~口 ne or more CE inputs high.
functional block diagrams
'S201
'S189 , 'S289
ADORESS
INPUτs
~
tlm
回
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256-BITMEMORV
MATRIXQ 冈 GANI2ED
16-BY.16
002
003
004
SN74S209
'S301
Same as 'S201 except output is as shown below.
miljx;
SN74S309
Same as SN74S209 except output is as shown below.
1024.BITMEMORY
MATAJX ORGAN1ZED
32-BY.32
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage , VCC (see Note 1)
Input voltage
.•...•.•...••.••.....•.•••••..
..•••••..........••
Off-state output voltage
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
•
.
•
.
.
.
•
•
.
•
.
.
.
.
.
•
.
.
.
.
.
.
.
.
.
.
.
.
.
.
•
.
•
.
.
•
7 V
.
.
5.5 V
•
•
5.5 V
.
.
.
.
0
0
•
.
.
.
.
.
.
.
.
.
.
•
•
•
•
.
•
OOC to 70 C
.
.
•
•
•
•
.
.
•
.
•
.
.
•
.
.
.一65 C to 150 C
0
0
ground termina l.
Nα
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t口 network
.
.
0
SN74S' Circuits
Storage temperature range
.
.
.................一55 C to 125 C
Operating free-air temperature range: SN54S' Circuits
NOTE1: Voltage values are with respect
.
.
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SN74S189
SN54S189
Supply voltage , VCC
MIN
NOM
MAX
MIN
NOM
4.5
5
5.5
4.75
5
一2
High-Ievel output current , 10H
Low-Ievel output current , 10L
Width of write pulse , tw{wrl (see Figure 1)
Setup
Address before write pulse , tsu{ad)
time (see Chip enable before write pulse , tsu{CE)
Figure 1) Data before end of write pulse , tsu{da)
Hold
o
~
•><
5.25
4.5
5
5.5
0•
16
5
SN74S209
MAX
NOM
5.25 4.75
5
0•
o~
0•
o~
10~
25 •
100t
65t
140•
Ot
ot
10 •
ot
0•
0•
10t
Figure 1) Data after write pulse , th{da)
ot
ot
ot
ot
10t
70
O
一 55
125
16
mA
ns
。↓
125
V
mA
10•
25 •
-55
5.25
UNIT
一 10.3
130
ot
Address after write pulse , th{ad)
MAX
16
65
o~
MIN
一 10.3
16
100
0•
4.75
NOM
一2
-6.5
25
MIN
ot
。
70
ns
ns
o
70
。c
•• The arrow indicates the transition of the read/write input used for reference: tfor the low-to-high-transition ,• for the high-to-Iow transition.
rrI
electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
;l>
;32
Z 毛ω
:)叫
15 万
\:f'iC:
VIH
High-Ievel input voltage
VIL
Low-Ievel input voltage
VIK
Input c1 amp voltage
VOH
:Cls;:
3 归
VOL
high-Ievel voltage applied
VIL ='0 .8 V ,
Off-state output current ,
= MAX ,
= 0.8 V ,
Vcc = MAX ,
Vcc = MAX ,
Vcc = MAX ,
Vcc = MAX
Low-Ievel output voltage
叶
10ZH
zω
10ZL
low-Ievel voltage applied
11
Input current at maximum input voltage
IIH
High-Ievel input current
IIL
Low-Ievel input current
10S
Short-circuit output current S
TVP 丰
Supply current
MIN
TVP 丰
Vcc
Vcc
Vcc
V 1L
=+
= 2 V,
10H = MAX
VIH = 2 V ,
10L = 16 mA
VIH = 2 V ,
VO = 2 .4 V
VIH = 2 V ,
VO = 0 .4 V
VI = 5.5 V
VI = 2.7 V
VI = 0.5 V
Series 54S'
2 .4
Series 74S'
2 .4
3.4
Vcc
See Note 2
Series 74S'
2 .4
3.2
V
一 1.2
一1. 5
V
3.3
2 .4
2.9
0.5
0.38
0.5
Series 74S'
0.35
0 .4 5
0.38
0 .4 5
0.38
Full range
75
0 .4 5
50
40
100
一50
一 40
-100
25
25
25
一250
-250
-250
μA
一 100
口、A
一 100
75
0
V
2.9
1
= MAX
= 25 C
TA = MIN
UNIT
V
0.35
TA
MAX
0.8
一 100
一 30
110
100
110
110
11 mA
-30
μA
115
110
140
mA
155
100
140
t For conditions shown as M 1N or MAX , use the appropriate value specified under recommended operating conditions.
0
!AII typical values are at Vcc = 5 V , T A = 25 C.
SDuration of the short circuit should not exceed one second.
+11 = -18 mA for 'S189 and 'S201 , -12 mA for 'S209.
NOTE 2: For the 'S189 ICC is measured with the read/write and chip-enable inputs grounded , all 口 ther inputs at 4.5 V , and the outputs open.
For the 'S201 and SN74S209 ICC is measured with a 川 chip-enable inputs grounded , all other inputs at 4.5 V , and the output open
u1
TVP 丰
0.8
Series 54S'
-30
= MAX , Series 54S'
2 .4
MIN
2
一1. 2
11
VIH
SN74S209
MAX
2
TA
ICC
MAX
0.8
Off-state output current ,
回"7
MIN
2
= MIN ,
= MIN ,
VIL = 0.8 V ,
Vcc = MIN ,
VIL = 0.8 V ,
Vcc = MAX ,
High-Ievel output voltage
'S201
'S189
TEST CONDITIONSt
PARAMETER
g Z-
3
MAX
ot
m (J)
•
NOM
16
25
SN74S201
MIN
time (see Chip enable after write pulse , th{ ëË)
Operating free.air temperature , T A
z
SN54S201
MAX
110
140
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recommended operating conditions
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SN54S289
Supply voltage , VCC
;1>
5
5.5
4.75
MIN
NOM
MAX
5
5.25
4.5
5
5.5
25
Address before write pulse , tsu(ad)
Address after write pulse , th(ad)
25
100
0•
0•
130
0•
ns
10 1-
0•
0 1-
0•
0•
10 1-
25 •
25t
100t
65t
140 •
10t
ot
ot
ot
ot
ot
ot
ot
ot
10 •
Figure 2) Data after write pulse , th(da)
Ot
0•
ot
0•
10t
Operating free-air temperature , T A
一 55
125
o
70
-55
125
。
70
ns
ns
o
70
。C
T• The arrow indicates the transition of the read/write input used for reference: tfor the low-to-high-transition ,• for the high-to-Iow transition.
electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
VOL
'S289
TEST CONDITIONSt
MIN
TYP 丰
'S301
MAX
2
High-Ievel output current
VCC=MIN ,
11=.
Vcc = MIN ,
VIH = 2 V ,
VIL = 0.8 V
Low-Ievel output voltage
MIN
TYP 丰
SN74S309
MAX
2
MIN
TYP 丰
MAX
UNIT
V
2
0.8
0.8
0.8
V
V
一1. 2
一1. 2
一1. 5
VO = 2 .4 V
40
40
100
VO = 5.5 V
100
100
250
Vcc = MIN ,
VIH = 2 V ,
Series 54S'
0.5
0.38
0.5
VIL = 0.8 V ,
IOL = 16 mA Series 74S'
0 .4 5
0.38
0 .4 5
0.38
0 .4 5
μA
V
11
Input current at maximum input voltage
Vcc = MAX , VI = 5.5 V
IIH
High-Ievel input current
Vcc = MAX , VI = 2.7 V
25
25
25
μA
IIL
Low-Ievel input current
Vcc = MAX , VI = 0.5 V
一250
-250
一 250
μA
105
110
11 mA
TA = MAX
ICC
Supply current
0
Vcc= MAX , Series 54S'
TA = 25 C
See Note 3
TA = MIN
Series 74S'
75
105
100
105
Full range
75
105
140
100
140
t For cond it: ions shown as M I N or MAX , use the appropriate value specified under recommended operating conditions.
丰 AII typical values arc at V cc = 5 V , T A = 25 C.
0
.11 = -18 mA for 'S289 and 'S301 ，一 12 mA for 'S309
NOTE 3: For the 'S289 ICC is measured with the read/write and chip-enable inputs grounded , all other inputs at 4.5 V. and the outputs open.
For the 'S301 and SN7 4S 309 ICC is measured with a 川 chip-enable inputs grounded , all other inputs at 4.5 V , and the output open.
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mA
155
110
140
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PARAMETER
IOH
ω
65
0•
time (see Chip enable after write pulse , th( ëË)
:O~
叶
V
V
Input clamp voltage
巳
UNIT
盯， A
VIK
E
5.25
16
12 月
肉
MAX
5
16
Low-Ievel input voltage
Z
NOM
5.25 4.75
16
VIL
~
MIN
16
High-Ievel input voltage
3
5
SN74S309
MAX
16
VIH
~ri C:
4.75
NOM
Low-Ievel output current , IOL
g Zz 毛ω
• 0叫
MIN
5.5
Hω
;32
SN74S301
MAX
5.5
Hold
~
4.5
SN54S301
NOM
5.5
Figure 2) Data before end of write pulse , tsu(da)
rT"I
MIN
5.5
time (see Chip enable before write pulse , tsu( ëË)
o
MAX
5.5
Setup
•><
NOM
High.level output voltage , VOH
Width of write pulse , tw(wrl (see Figure 1)
z~
SN74S289
MIN
PARAMETER
TEST CONDITIONS
tw( 阳， min)
Minimum width of write pulse
ta(ad)
Access time from address
ta(CE)
Access time from chip enable (enable time)
tSR
Sense recovery time
tpxz
Disable time from high or low level
SN54S189
TYP丰
MAX
SN54S201
SN74S201
TYP 丰
MAX
TYP 丰
MAX
SN74S209
TYP 丰
MAX
UNIT
15
25
15
25
40
100
40
65
65
85
ns
50
25
35
42
85
42
65
70
100
ns
12
25
12
17
13
40
13
30
20
40
ns
22
40
22
35
20
50
20
40
20
40
ns
CL = 5 pF , RL1 = 300 n ,
12
25
12
17
9
30
9
20
15
30
See Figure 1
12
13
45
13
35
25
40
RL = 300
I from R 川
SN74S189
TYP 丰
25
CL = 30 pF ,
I from CE
MAX
n,
See Figure 1
12
ns
random-access memories with open-collector.outputs
PARAMETER
z
~
~
TEST CONDITIONS
SN54S289
TYP 丰
MAX
SN74S289
TYP 丰
SN5 4S 301
SN74S301
MAX
TYP 丰
MAX
TYP 丰
MAX
SN74S309
TYP丰
MAX
叶
tw(wr,min) Minimum width of write pulse
15
25
15
25
40
100
40
65
65
85
l'T1
ta(ad)
Access time from address
CL=30pF ,
25
50
25
35
42
85
42
65
70
100
ns
:þ
ta(CE)
Access time from chip enable (enable time)
RL1 = 300
12
25
12
17
13
40
13
30
20
40
ns
tSR
Se nse recovery time
n,
RL2 = 600 n ,
22
40
22
35
20
50
20
40
20
40
ns
Propagation delay time, low-to-
See Figure 2
12
25
12
17
8
30
8
20
15
30
15
45
15
35
25
40
><
Mω
E Z~2Z
tpLH
z 毛ω
from R/W
high-Ievel output (disable time)
12
12
丰 AII typical values are at V cc = 5 V , T A = 25 C.
0
• 0叫
:2 汩
:0roiC3:
Ç;
i 归
schematics of inputs and outputs
国'"7
5
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UNIT
'S189, 'S201 , SN74S209,
'S289, 'S301 , SN74S309
叶
ω
EQUIVALENT OF EACH INPUT
'S289, 'S301 , SN74S309
OUTPUT
OUTPUT
V
cc
。
可
Vcc
'S189, 'S201 , SN74S209
INPUT
U T Dr U T
ns
ns
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switching characteristics over recommended operating ranges of TA and VCC (unless otherwise noted)
random-access memories with three-state outputs
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SERIES 54S/74S
RANDOM-ACCESS READ/WRITE MEMORIES
PARAMETER MEASUREMENT INFORMATION
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WRITE CYCLE VOLTAGE WAVEFORMS
LOAD CIRCUIT
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ACCESS (ENABLE) Tl ME AND DISABLE TIME FROM CHIP ENABLE
VOL TAGE WAVEFORMS
NOTES:
::-呢-""4.5V
'k..'.5V
I+ta 川」一一寸-"Ff~ 一
I+-"， .d' 叫
ACCESS TIME FROM ADDRESS INPUTS
拦艺工
M ，一一立坚引
VOLTAGE WAVEFORMS
回
A. When measuring access times from address inputs , the chip enable input(s) is(are) low and the read/write is high.
B. Waveform 1 is for the output with internal c口 nditions such that the output is low except when disabled. Waveform 2 is for the
口 utput with internal conditions such that the output is high except when disabled.
C. When measuring access and disable times from chip enable input( 剖， the address inputs are steady-state and the read/write input is
high.
D. Input waveforms are supplied by pulse generators having the following characteristics: tr .;; 2.5 ns tf';; 2.5 ns , PRR .;; 1 MHz ,
and Zout 臼 50 n.
FIGURE 1-TESTING RAM'sWITH 3-STATE OUTPUTS
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LOAD CIRCUIT
WRITE CYCLE VOLTAGE WAVEFORMS
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NOTES:
正t:::
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Þ乙:
ACCESS TIME FROM ADDRESS INPUTS
ACCESS (ENABLE) TIME AND DISABLE TIME FROM CHIP ENABLE
VOLTAGE WAVEFORMS
VOLTAGEWAVEFORMS
A. When measuring access times from address inputs , the chip-enable input(s) is(are) low and the read/write input is high
B. Waveform shown is for the output with internal conditions such that the 口 utput is low except when disabled.
C. When measuring access and disable times from chip-enable input( 叫， the address inputs are steady-state and the read/write input is
high.
D. Input waveforms are supplied by pulse generators having the following characteristics: tr .;; 2.5 ns , tf .;; 2.5 ns , PRRζ1 MHz ,
and Z~.
，. "" 50 n
OUt
FIGURE 2-TES Tl NG RAM'sWITH OPEN.COLLECTOR OUTPUTS
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TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE <HANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND 10 SUPPLY THE BEST PRODUCT POSSIBLE
THxo
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PRINTED IN U.5.A
TI cannot allume any lesponsibility lor any circuits shown
or leple"nt thot they ore llee Irom potent inlringement
E
575
171