25/0251 CY7C026A CY7C036A 16K x 16/18 Dual-Port Static RAM • Automatic power-down • Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flags for port-to-port communication • Separate upper-byte and lower-byte control • Pin select for Master or Slave • Commercial and Industrial temperature ranges • Available in 100-Pin TQFP • Pin-compatible and functionally equivalent to IDT70261 Features • True dual-ported memory cells which allow simultaneous access of the same memory location • 16K x 16 organization (CY7C026A) • 16K x 18 organization (CY7C036A) • 0.35-micron CMOS for optimum speed/power • High-speed access: 12/15/20 ns • Low operating power — Active: ICC = 180 mA (typical) — Standby: ISB3 = 0.05 mA (typical) • Fully asynchronous operation Logic Block Diagram R/WL UBL R/WR UBR CEL CER LBL LBR OEL OE R  I/O 8/9L–I/O 15/17L  8/9 8/9 8/9 I/O Control I/O 0L–I/O 7/8L 14 A0L–A13L Address Decode 8/9 I/O Control  I/O0L–I/O7/8R Address Decode True Dual-Ported RAM Array  I/O8/9L–I/O 15/17R 14 14 A0R–A13R 14 A0L–A13L CEL OEL R/WL SEM L A0R–A13R CER OE R R/WR SEM R Interrupt Semaphore Arbitration   BUSYL INTL UBL LBL BUSYR INT R UBR LB R M/S Notes: 1. See page 6 for Load Conditions. 2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices. 3. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices. 4. BUSY is an output in master mode and an input in slave mode. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 3, 2000 CY7C026A CY7C036A Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by the chip enable pin. Functional Description The CY7C026A and CY7C036A are low-power CMOS 16K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. The CY7C026A and CY7C036A are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. Pin Configurations A7L A8L A9L A10L A11L A12L A13L LBL UBL CEL SEML R/WL VCC OEL I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O8L I/O9L 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 NC NC 2 74 NC NC 3 73 NC NC 4 72 A6L I/O10L 5 71 A5L I/O11L 6 70 A4L I/O12L 7 69 A3L I/O13L 8 68 A2L GND 9 67 A1L I/O14L 10 66 A0L I/O15L 11 65 INTL VCC 12 64 BUSYL GND 13 63 GND I/O0R 14 62 M/S I/O1R 15 61 BUSYR I/O2R 16 60 INTR VCC 17 59 A0R I/O3R 18 58 A1R I/O4R 19 57 A2R I/O5R 20 56 A3R I/O6R 21 55 A4R NC 22 54 A5R NC 23 53 NC NC 24 52 NC NC 25 51 NC CY7C026A (16K x 16) 2 A6R A7R A8R A9R A10R A11R A12R A13R LBR UBR CER SEMR GND R/WR OER I/O15R GND I/O14R I/O13R I/O12R I/O11R I/O10R I/O9R I/O8R I/O7R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CY7C026A CY7C036A Pin Configurations (continued) A 7L A 6L A 8L A 10L A 9L A 11L LB L A 12L UB L SEM L CE L R/W L OE L VCC I/O 0L I/O 1L I/O 2L GND I/O 3L I/O 4L I/O 5L I/O 6L I/O 7L I/O 9L I/O 10L 100-Pin TQFP Top View 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 67 66 65 64 63 62 CY7C036A (16K x 18) 14 61 60 59 15 16 17 18 19 20 21 BUSY R INT R A 0R A 1R 57 56 55 54 53 A 2R A 3R A 4R A 13R NC NC NC A 5R A 6R A 7R A 9R A 8R A 10R A 11R LB R A 12R UB R CE R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SEM R 24 25 R/W R GND NC NC A 5L A 4L A 3L A 2L A 1L A 0L INT L BUSY L GND M/S 58 52 51 OE R 22 23 I/O 7R I/O 17R I/O 16R I/O 4R I/O 5R I/O 6R I/O 8R 68 GND I/O 3R 5 6 7 8 9 10 11 12 13 I/O 15R VCC GND I/O 0R I/O 1R I/O 2R VCC 72 71 70 69 I/O 14R I/O 15L I/O 16L 3 4 NC NC A 13L I/O 13R GND 73 I/O 12R I/O 12L I/O 13L I/O 14L 2 I/O 11R I/O 11L NC 74 I/O 10R I/O 17L 75 1 I/O 9R NC NC I/O 8L Selection Guide CY7C026A CY7C036A -12 CY7C026A CY7C036A -15 CY7C026A CY7C036A -20 Maximum Access Time (ns) 12 15 20 Typical Operating Current (mA) 195 190 180 Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) 55 50 45 0.05 0.05 0.05 Typical Standby Current for ISB3 (mA) (Both Ports CMOS Level) 3 CY7C026A CY7C036A Pin Definitions Left Port Right Port Description CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A13L A0R–A13R Address I/O0L–I/O 17L I/O0R–I/O 17R Data Bus Input/Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O 17 for x18 devices) LBL LBR Lower Byte Select (I/O0–I/O 7 for x16 devices; I/O 0–I/O8 for x18 devices) INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground NC No Connect DC Input Voltage ........................................–0.5V to + 7.0V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... >2001V Storage Temperature .................................–65°C to +150°C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied .............................................–55°C to +125°C Operating Range Supply Voltage to Ground Potential ............... –0.3V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% –40°C to +85°C 5V ± 10% Industrial Note: 5. Pulse width < 20 ns. 4 CY7C026A CY7C036A Electrical Characteristics Over the Operating Range CY7C026A CY7C036A -12 Parameter Description Min. Typ. VOH Output HIGH Voltage (VCC=Min., IOH= –4.0 mA) VOL Output LOW Voltage (VCC=Min., IOH= +4.0 mA) VIH Input HIGH Voltage VIL Input LOW Voltage IOZ Output Leakage Current ICC Operating Current (VCC = Max., Com’l. IOUT = 0 mA) Outputs Disabled Indust. 195 Standby Current (Both Ports TTL Level) CEL & CER ≥ V IH, f = fMAX 55 ISB1 ISB2 ISB3 ISB4 -15 Max. Min. 2.4 Typ. Standby Current (Both Ports CMOS Level) CEL & CER ≥ V CC –0.2V, f = 0 Standby Current (One Port CMOS Level) CEL | CER ≥ VIH, f = fMAX 75 Indust. 125 205 Indust. Com’l. 0.05 0.5 Indust. Com’l. 115 185 Indust. 10 190 285 215 305 50 70 65 95 120 180 135 205 0.05 0.5 0.05 0.5 110 160 125 175 Unit V 0.4 V V 0.8 –10 325 Max. 2.2 0.8 Com’l. Typ. 0.4 2.2 10 Min. 2.4 0.4 –10 Com’l. Max. 2.4 2.2 Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f = fMAX -20 –10 180 0.8 V 10 µA 275 mA mA 45 65 mA mA 110 160 mA mA 0.05 0.5 mA mA 100 140 mA mA Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF 10 pF Notes: 6. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 7. Tested initially and after any design or process changes that may affect these parameters. 5 CY7C026A CY7C036A AC Test Loads and Waveforms 5V 5V R1 = 893Ω RTH = 250Ω OUTPUT OUTPUT R1 = 893Ω OUTPUT C = 30 pF C = 30 pF R2 = 347Ω C = 5 pF R2 = 347Ω VTH = 1.4V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, & tLZWE including scope and jig) (b) Thévenin Equivalent (Load 1) AC Test Loads (Applicable to -12 only) OUTPUT Z0 = 50Ω ALL INPUT PULSES R = 50Ω 3.0V C 10% GND 90% 10% 90% ≤ 3 ns ≤ 3 ns VTH = 1.4V (a) Load 1 (-12 only) 1 .00 0.90 ∆ (ns) for all -12 access times 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.1 0 0.00 10 15 20 25 Capacitance (pF) (b) Load Derating Curve Note: 8. Test Conditions: C = 10 pF. 6 30 35 CY7C026A CY7C036A Switching Characteristics Over the Operating Range CY7C026A CY7C036A -12 Parameter Description Min. -15 Max. Min. -20 Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 12 15 tAA Address to Data Valid tOHA Output Hold From Address Change tACE CE LOW to Data Valid 12 15 20 ns tDOE OE LOW to Data Valid 8 10 12 ns tLZOE[11, 12, 13] tHZOE[11, 12, 13] tLZCE[11, 12, 13] tHZCE[11, 12, 13] tPU tPD tABE OE LOW to Low Z 12 3 15 3 3 OE HIGH to High Z 3 CE HIGH to High Z CE LOW to Power-Up 0 20 10 ns 12 3 10 0 ns ns 3 3 10 ns 3 3 10 CE LOW to Low Z 20 ns ns 12 0 ns ns CE HIGH to Power-Down 12 15 20 ns Byte Enable Access Time 12 15 20 ns WRITE CYCLE tWC Write Cycle Time 12 15 20 ns tSCE CE LOW to Write End 10 12 15 ns tAW Address Valid to Write End 10 12 15 ns tHA Address Hold From Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE Write Pulse Width 10 12 15 ns tSD Data Set-Up to Write End 10 10 15 ns tHD tHZWE[12, 13] tLZWE[12, 13] tWDD tDDD Data Hold From Write End 0 0 0 ns R/W LOW to High Z 10 R/W HIGH to Low Z 3 10 3 12 3 ns ns Write Pulse to Data Delay 25 30 45 ns Write Data Valid to Read Data Valid 20 25 30 ns Notes: 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OI/IOH and 30-pF load capacitance. 10. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time. 11. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 12. Test conditions used are Load 3. 13. This parameter is guaranteed but not tested. 14. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 15. For 15 ns industrial parts tHD Min. is 0.5 ns. 7 CY7C026A CY7C036A Switching Characteristics Over the Operating Range (continued) CY7C026A CY7C036A -12 Parameter BUSY TIMING Description Min. -15 Max. Min. -20 Max. Min. Max. Unit  tBLA BUSY LOW from Address Match 12 15 20 ns tBHA BUSY HIGH from Address Mismatch 12 15 20 ns tBLC BUSY LOW from CE LOW 12 15 20 ns tBHC BUSY HIGH from CE HIGH 12 15 17 ns tPS Port Set-Up for Priority 5 5 5 ns tWB R/W HIGH after BUSY (Slave) 0 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 11 13 15 ns tBDD BUSY HIGH to Data Valid INTERRUPT TIMING 12 15 20 ns  tINS INT Set Time 12 15 20 ns tINR INT Reset Time 12 15 20 ns SEMAPHORE TIMING tSOP SEM Flag Update Pulse (OE or SEM) 10 10 10 ns tSWRD SEM Flag Write to Read Time 5 5 5 ns tSPS SEM Flag Contention Window 5 5 5 ns tSAA SEM Address Access Time 12 15 20 ns Timing Data Retention Mode Data Retention Mode The CY7C026A and CY7C036A are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: VCC 1. Chip Enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2V. 4.5V VCC > 2.0V 4.5V VCC to VCC – 0.2V CE tRC V IH 2. CE must be kept between VCC – 0.2V and 70% of VCC during the power-up and power-down transitions. Parameter 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (4.5 volts). ICC DR1 Notes: 16. Test conditions used are Load 2. 17. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or t DDD–tSD (actual). 18. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested. 8 Test Conditions @ VCCDR = 2V Max. Unit 1.5 mA CY7C026A CY7C036A Switching Waveforms Read Cycle No.1 (Either Port Address Access)[19, 20, 21] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Read Cycle No.2 (Either Port CE/OE Access)[19, 22, 23] tACE CE and LB or UB tHZCE tDOE OE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Read Cycle No. 3 (Either Port)[19, 21, 22, 23] tRC ADDRESS tAA tOHA UB or LB tHZCE tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes: 19. R/W is HIGH for read cycles. 20. Device is continuously selected CE = VIL and UB or LB = VIL . This waveform cannot be used for semaphore reads. 21. OE = VIL. 22. Address valid prior to or coincident with CE transition LOW. 23. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. 9 CY7C026A CY7C036A Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing[24, 25, 26, 27] tWC ADDRESS tHZOE  OE tAW CE [28,29] tPWE tSA tHA R/W tHZWE DATA OUT tLZWE NOTE 31 NOTE 31 tSD tHD DATA IN Write Cycle No. 2: CE Controlled Timing[24, 25, 26, 32] tWC ADDRESS tAW CE [28,29] tSA tSCE tHA R/W tSD tHD DATA IN Notes: 24. R/W must be HIGH during all address transitions. 25. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 26. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + t SD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 28. To access RAM, CE = VIL, SEM = VIH. 29. To access upper byte, CE = VIL , UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 30. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 31. During this period, the I/O pins are in the output state, and input signals must not be applied. 32. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 10 CY7C026A CY7C036A Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side tSAA A 0–A 2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O 0 DATA IN VALID tSA tPWE DATA OUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Timing Diagram of Semaphore Contention[34, 35, 36] A0L –A 2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes: 33. CE = HIGH for the duration of the above timing (both write and read cycle). 34. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 35. Semaphores are reset (available to both ports) at cycle start. 36. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. 11 CY7C026A CY7C036A Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) tWC ADDRESSR MATCH tPWE R/WR tHD tSD DATA IN R VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH Note: 37. CEL = CER = LOW. 12 CY7C026A CY7C036A Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CELValid First: ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CE L tBLC tBHC BUSY L Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSY R Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSY L Note: 38. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. 13 CY7C026A CY7C036A Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR: tWC ADDRESSL WRITE 3FFF tHA  CE L R/W L INT R tINS  Right Side Clears INTR: tRC ADDRESSR READ 3FFF CE R tINR  R/WR OE R INTR Right Side Sets INT L: tWC ADDRESSR WRITE 3FFE tHA CE R R/W R INT L  tINS Left Side Clears INTL: tRC READ 3FFE ADDRESSR CE L tINR R/W L OE L INT L Notes: 39. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 40. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. 14 CY7C026A CY7C036A within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Architecture The CY7C026A and CY7C036A consist of an array of 16K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic powerdown feature controlled by CE. Each port is provided with its own Output Enable control (OE), which allows data to be read from the device. Master/Slave Functional Description A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Write Operation Semaphore Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. The CY7C026A and CY7C036A provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. Interrupts The upper two memory locations may be used for message passing. The highest memory location (3FFF) is the mailbox for the right port and the second-highest memory location (3FFE) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. When writing to the semaphore, only I/O 0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. When reading a semaphore, all sixteen/eighteen data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C026A and CY7C036A provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs 15 CY7C026A CY7C036A Table 1. Non-Contending Read/Write Inputs Outputs CE R/W OE UB LB SEM H X X X X H High Z I/O 9–I/O17 High Z I/O0–I/O8 Deselected: Power-Down Operation X X X H H H High Z High Z Deselected: Power-Down L L X L H H Data In High Z Write to Upper Byte Only L L X H L H High Z Data In Write to Lower Byte Only L L X L L H Data In Data In Write to Both Bytes L H L L H H Data Out High Z Read Upper Byte Only L H L H L H High Z Data Out Read Lower Byte Only L H L L L H Data Out Data Out Read Both Bytes X X H X X X High Z High Z Outputs Disabled H H L X X L Data Out Data Out Read Data in Semaphore Flag X H L H H L Data Out Data Out Read Data in Semaphore Flag H X X X L Data In Data In Write D IN0 into Semaphore Flag X X H H L Data In Data In Write D IN0 into Semaphore Flag L X X L X L Not Allowed L X X X L L Not Allowed Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Right Port R/WL CEL OEL A0L–13L INTL R/WR CER OE R A0R–13R INTR Set Right INTR Flag L L X 3FFF X X X X X L Reset Right INTR Flag X X X X X X L L 3FFF H Set Left INTL Flag X X X X L L L X 3FFE X  X X X X X Reset Left INTL Flag X L L 3FFE H Table 3. Semaphore Operation Example Function I/O0–I/O17 Left I/O0–I/O17 Right Status No action 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left Port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Notes: 41. If BUSYL=L, then no change. 42. If BUSYR=L, then no change. 16 CY7C026A CY7C036A Ordering Information 16K x16 Asynchronous Dual-Port SRAM Speed (ns) Package Name Ordering Code Package Type Operating Range 12 CY7C026A-12AC A100 100-Pin Thin Quad Flat Pack Commercial 15 CY7C026A-15AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C026A-15AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C026A-20AC A100 100-Pin Thin Quad Flat Pack Commercial 20 16K x18 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 12 CY7C036A-12AC A100 100-Pin Thin Quad Flat Pack Commercial 15 CY7C036A-15AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C036A-15AI A100 100-Pin Thin Quad Flat Pack Industrial 20 CY7C036A-20AC A100 100-Pin Thin Quad Flat Pack Commercial Document #: 38-00832-A Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-B © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.