LD39050xx 500 mA low quiescent current low noise voltage regulator Features ■ Input voltage from 1.5 to 5.5 V ■ Ultra low dropout voltage (200 mV typ. at 500 mA load) ■ Very low quiescent current (20 µA typ. at no load, 100 µA typ. at 500 mA load, 1 µA max in off mode) ■ Very low noise without bypass capacitor ■ Output voltage tolerance: ± 2.0 % @ 25 °C ■ 500 mA guaranteed output current ■ Wide range of output voltages available on request: 0.8 V to 4.5 V with 100 mV step and ADJ from 0.8 V ■ Logic-controlled electronic shutdown ■ Compatible with ceramic capacitor COUT = 1 µF ■ Internal current and thermal limit ■ Package DFN6 (3 x 3 mm) ■ Temperature range: -40 °C to 125 °C DFN6 (3 x 3 mm) roll off at 10 kHz. An Enable logic control function puts the LD39050 in shut-down mode allowing a total current consumption lower than 1 µA. The device also includes short-circuit constant current limiting and thermal protection. Typical applications are mobile phones, personal digital assistants (PDAs), cordless phones and similar battery-powered systems. Description The LD39050 provides 500 mA maximum current from an input voltage ranging from 1.5 V to 5.5 V with a typical dropout voltage of 200 mV. Stability is provided using ceramic capacitors. The ultra low drop-voltage, low quiescent current and low noise features make it suitable for low power battery-powered applications. Power supply rejection is 65 dB at low frequencies and starts to Table 1. March 2009 Device summary Part numbers Order codes Output voltages LD39050XX LD39050PUR ADJ from 0.8 V LD39050XX10 LD39050PU10R 1.0 V LD39050XX12 LD39050PU12R 1.2 V LD39050XX25 LD39050PU25R 2.5 V LD39050XX33 LD39050PU33R 3.3 V Rev 1 1/24 www.st.com 24 Contents LD39050xx Contents 1 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 Power Good function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 Different output voltage versions of the LD39050xx available on request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 LD39050xx Diagrams 1 Diagrams Figure 1. Schematic diagram for the LD39050PU IN PG Power-good signal IN BandGap reference Current limit OpAmp OUT Thermal protection ADJ EN Internal enable GND Figure 2. Schematic diagram for the LD39050PUxx IN PG Power-good signal IN BandGap reference Current limit OpAmp OUT Thermal protection R1 NC EN R2 Internal enable GND 3/24 Pin configuration LD39050xx 2 Pin configuration Figure 3. Pin connection (top view) EN VIN EN GND NC GND ADJ PG VOUT VOUT PG LD39050PUxx Table 2. VIN LD39050PU Pin description Pin n° Symbol LD39050PUxx EN 1 1 Enable pin logic input: Low=shutdown, High=active GND 2 2 Common ground PG 3 3 Power Good VOUT 4 4 Output voltage ADJ 5 - Adjust pin VIN 6 6 Input voltage of the LDO NC - 5 Not connected GND 4/24 Function LD39050PU EXP pad Exposed pad must be connected to GND LD39050xx Maximum ratings 3 Maximum ratings Table 3. Absolute maximum ratings Symbol Value Unit -0.3 to 7 V DC output voltage -0.3 to VI + 0.3 (7 V max) V EN Enable pin -0.3 to VI + 0.3 (7 V max) V PG Power Good pin -0.3 to 7 V ADJ Adjust pin 4 V IOUT Output current Internally limited Power dissipation Internally limited VIN VOUT PD Parameter DC input voltage TSTG Storage temperature range - 65 to 150 °C TOP Operating junction temperature range - 40 to 125 °C Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND. Table 4. Thermal data Symbol Parameter Value Unit RthJA Thermal resistance junction-ambient 55 °C/W RthJC Thermal resistance junction-case 10 °C/W Table 5. Symbol ESD ESD performance Parameter Test conditions Value Unit HBM 2 kV MM 0.3 kV ESD protection voltage 5/24 Electrical characteristics 4 LD39050xx Electrical characteristics TJ = 25 °C, VIN = 1.8 V, CIN = COUT = 1 µF, IOUT = 10 mA, VEN = VIN, unless otherwise specified. Table 6. Symbol VIN Electrical characteristics for the LD39050PU Parameter Operating input voltage VADJ VADJ accuracy IADJ Adjust pin current ΔVOUT Static line regulation ΔVOUT Transient line regulation (1) ΔVOUT Static load regulation ΔVOUT Transient load regulation (1) VDROP Dropout voltage (2) eN SVR Test conditions Output noise voltage Supply voltage rejection VOUT = 0.8V Min. Typ. 1.5 816 IOUT = 10 mA, -40°C<TJ<125°C 776 800 824 mV 1 VOUT +1 V ≤ VIN ≤ 5.5 V, IOUT = 1 mA 0.01 ΔVIN=500 mV, IOUT=10 mA, tR=5 µs 10 ΔVIN=500 mV, IOUT=10 mA, tF=5 µs 10 6/24 Short-circuit current IOUT = 10 mA to 500 mA %/V 0.002 IOUT = 10 mA to 500 mA, tR=5µs 40 IOUT = 10 mA to 500 mA, tF=5µs 40 IO = 500mA, VOUT fixed to 1.5V 40°C<TJ<125°C 200 10Hz to 100kHz, IOUT = 100 mA, VOUT = 0.8 V 30 VIN = 1.8V+/-VRIPPLE VRIPPLE = 0.25V, freq. = 1kHz IOUT = 10 mA 65 VIN = 1.8V+/-VRIPPLE VRIPPLE = 0.25V, freq.=10 kHz IOUT = 100 mA 62 IOUT = 0 mA 20 %/mA mVpp 400 mV µVRMS dB 50 100 µA IOUT=0 to 500mA, 40°C<TJ<125°C 200 VIN input current in off mode: VEN = GND(3) 0.001 Rising edge 0.92* VOUT Falling edge 0.8* VOUT RL=0 µA mVpp Power Good output voltage low Isink=6mA open drain output ISC V 800 Power Good output threshold PG 5.5 784 IOUT = 0 to 500mA Quiescent current Unit IOUT =10 mA, TJ = 25°C IOUT= 0 mA, -40°C<TJ<125°C IQ Max. 1 V 0.4 600 800 V mA LD39050xx Table 6. Electrical characteristics Electrical characteristics for the LD39050PU (continued) Symbol VEN IEN tON TSHDN COUT Parameter Test conditions Enable input logic low VIN=1.5 V to 5.5 V, 40°C<TJ<125°C Enable input logic high VIN=1.5 V to 5.5 V, 40°C<TJ<125°C Enable pin input current VEN= VIN Turn on time Min. Typ. Max. Unit 0.4 V 0.9 V 0.1 (4) 100 30 Thermal shutdown 160 Hysteresis 20 nA µs °C Output capacitor Capacitance (see typical performance characteristics for stability) 1 22 µF 1. All transient values are guaranteed by design, not production tested 2. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for output voltages below 1.5 V 3. PG pin floating 4. Turn-on time is time measured between the enable input just exceeding VEN high value and the output voltage just reaching 95% of its nominal value 7/24 Electrical characteristics LD39050xx TJ = 25 °C, VIN = VOUT(NOM) + 1 V, CIN = COUT = 1 µF, IOUT = 10 mA, VEN = VIN, unless otherwise specified. Table 7. Symbol VIN VOUT Electrical characteristics for the LD39050PUxx Parameter VOUT accuracy Static line regulation ΔVOUT Transient line regulation (1) ΔVOUT Static load regulation ΔVOUT Transient load regulation (1) VDROP SVR Max. Unit 1.5 5.5 V VOUT >1.5V, IOUT =10 mA, TJ = 25°C -2.0 2.0 VOUT >1.5 V, IOUT = 10 mA, -40°C<TJ<125°C -3.0 Operating input voltage ΔVOUT eN Test conditions Min. Typ. % 3.0 VOUT ≤ 1.5 V, IOUT = 10 mA ±20 VOUT ≤ 1.5 V, IOUT =10 mA, -40°C<TJ<125°C ±30 VOUT +1 V ≤ VIN ≤ 5.5 V, IOUT = 1 mA 0.01 ΔVIN=500 mV, IOUT=10 mA, tR=5 µs 10 ΔVIN=500 mV, IOUT=10 mA, tF=5 µs 10 IOUT = 10 mA to 500 mA 0.002 40 IOUT = 10 mA to 500 mA, tF=5µs 40 Dropout voltage (2) IOUT = 500mA, VOUT > 1.5 V -40°C<TJ<125°C 200 Output noise voltage 10Hz to 100kHz, IO = 100 mA, 30 VIN = VOUT(NOM)+0.5V+/-VRIPPLE VRIPPLE = 0.1V, freq. = 1kHz IOUT = 10 mA 65 VIN = VOUT(NOM)+0.5V+/-VRIPPLE VRIPPLE = 0.1V, freq.=10 kHz IOUT = 100 mA 62 IOUT = 0 mA 20 Quiescent current 0.001 Rising edge 0.92* VOUT Falling edge 0.8* VOUT 8/24 Short-circuit current RL=0 µA 200 Power Good output threshold ISC µVRMS 100 VIN input current in off mode: VEN = GND (3) Isink=6mA open drain output mV 50 IOUT = 0 to 500mA Power Good output voltage low 400 dB IOUT = 0 to 500mA -40°C<TJ<125°C PG %/mA mVpp IOUT = 0 mA, -40°C<TJ<125°C IQ %/V mVpp IOUT = 10 mA to 500 mA, tR=5µs Supply voltage rejection VOUT = 1.5V mV 1 V 0.4 600 800 V mA LD39050xx Table 7. Electrical characteristics Electrical characteristics for the LD39050PUxx (continued) Symbol VEN IEN tON TSHDN COUT Parameter Test conditions Enable input logic low VIN=1.5 V to 5.5 V, -40°C<TJ<125°C Enable input logic high VIN=1.5 V to 5.5 V, -40°C<TJ<125°C Enable pin input current VEN = VIN Turn on time Min. Typ. Max. Unit 0.4 V 0.9 V 0.1 (4) 100 30 Thermal shutdown 160 Hysteresis 20 nA µs °C Output capacitor Capacitance (see typical performance characteristics for stability) 1 22 µF 1. All transient values are guaranteed by design, not production tested 2. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for output voltages below 1.5 V 3. PG pin floating 4. Turn-on time is time measured between the enable input just exceeding VEN high value and the output voltage just reaching 95 % of its nominal value 9/24 Typical performance characteristics LD39050xx Typical performance characteristics Figure 4. VADJ accuracy Figure 5. 0.85 0.84 0.83 2.55 2.54 2.53 0.82 0.81 0.8 0.79 0.78 2.52 2.51 2.5 2.49 2.48 VOUT [V] VADJ [V] 5 0.77 0.76 0.75 2.47 2.46 2.45 VIN = 1.8 V IOUT = 10 mA VEN = VIN -50 -25 0 25 50 75 VOUT accuracy 100 125 VIN = 3.5 V IOUT = 10 mA VEN = VIN -50 150 -25 0 25 50 Dropout voltage vs. temperature Figure 7. 350 350 300 300 250 250 Dropout [mV] Dropout [mV] Figure 6. 200 150 100 0 25 50 200 150 100 CIN = COUT = 1 µF 75 100 125 0 -50 150 -25 0 25 50 Dropout [V] ISC [A] VEN to VIN, CIN = COUT = 1 µF 100 200 300 IOUT [mA] 10/24 100 125 150 400 500 600 Short-circuit current vs. dropout voltage 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 125 °C 85 °C 55 °C 25 °C 0 °C -25 °C -40 °C VIN from 0 to 5.5 V, VEN = VIN, CIN = 1 µF, COUT = 1 µF 0 0 75 T [°C] Dropout voltage vs. output current Figure 9. 0.3 0.275 0.25 0.225 0.2 0.175 0.15 0.125 0.1 0.075 0.05 0.025 0 150 Dropout voltage vs. temperature T [°C] Figure 8. 125 50 CIN = COUT = 1 µF -25 100 VEN to VIN, IOUT = 500 mA, VOUT = 2.5 V VEN to VIN, IOUT = 500 mA, VOUT @ 1.5 V 50 0 -50 75 T [°C] T [°C] 1 2 3 VDROP [V] 4 5 6 LD39050xx Typical performance characteristics Figure 10. Output voltage vs. input voltage Figure 11. Quiescent current vs. temperature 0.9 0.7 125°C 0.6 85°C 0.5 55°C 0.4 25°C 0.3 0°C Iq [µA] VOUT [V] 0.8 - 25°C 0.2 0.1 - 40°C VEN = VIN, CIN = COUT = 1 µF; IOUT = 500 mA 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 100 90 80 70 60 50 40 30 20 10 0 -50 No load IOUT = 0.5 A VIN = 1.8 V, VEN to VIN, CIN = 1 µF COUT = 1 µF, VOUT = 0.8 V -25 0 25 5.5 50 75 100 125 150 T [°C] VIN [V] Figure 12. Quiescent current vs. temperature Figure 13. Quiescent current in off mode vs. temperature VIN = 3.5 V, VOUT = 2.5 V, VEN = GND, CIN = COUT = 1 µF 0.5 0.4 Iq [µA] Iq [µA] 0.6 100 90 80 70 60 50 40 30 20 10 0 -50 No load VIN = 3.5 V, VEN to VIN, CIN = COUT = 1 µF, VOUT = 2.5 V IOUT = 0.5 A 0.3 0.2 0.1 -25 0 25 50 75 100 125 0 150 -50 T [°C] -25 0 25 50 75 100 125 150 T [°C] Figure 14. Load regulation Figure 15. Line regulation 0.04 0.04 IOUT = 100 mA 0.02 0.01 0 -0.01 0.01 0 -0.01 -0.02 -0.02 -0.03 -0.03 -0.04 -50 IOUT = 1 mA 0.03 0.02 Line [%/V] Load [%/mA] 0.03 -0.04 -50 VIN = 1.8 V, IOUT = from 10 mA to 500 mA, VOUT = 0.8 V, VEN = VIN -25 0 25 50 75 100 125 150 VIN = from 1.8 V to 5.5 V VEN = VIN VOUT = 0.8 V -25 0 25 50 75 100 125 150 T [°C] T [°C] 11/24 Typical performance characteristics LD39050xx Figure 16. Line regulation Figure 17. Supply voltage rejection vs. temperature 0.04 100 90 80 IOUT = 1 mA 0.03 IOUT = 100 mA SVR [dB] Line [%/V] 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -50 VIN = from 3.5 V to 5.5 V VOUT = 2.5 V VEN = VIN -25 0 25 50 T [°C] 75 100 125 150 SVR [dB] SVR [dB] VIN from 1.7 V to 1.9 V, VOUT = 0.8 V, VEN to VIN, IOUT = 100 mA, freq. = 10 kHz CIN = COUT = 1 µF -25 0 25 50 CIN = COUT = 1 µF -25 0 25 75 100 125 150 100 90 80 70 60 50 40 30 20 10 0 -50 SVR [dB] SVR [dB] CIN = COUT = 1 µF 25 50 T [°C] 12/24 125 150 CIN = COUT = 1 µF -25 0 25 50 75 100 125 150 Figure 21. Supply voltage rejection vs. frequency VIN from 2.9 V to 3.1 V, VOUT = 2.5 V, VEN to VIN, IOUT = 100 mA, freq. = 10 kHz 0 100 T [°C] Figure 20. Supply voltage rejection vs. temperature -25 75 VIN from 2.9 V to 3.1 V, VOUT = 2.5 V, VEN to VIN, IOUT = 10 mA, freq. = 1 kHz T [°C] 100 90 80 70 60 50 40 30 20 10 0 -50 50 Figure 19. Supply voltage rejection vs. temperature 100 90 80 -50 VIN from 1.7 V to 1.9 V, VOUT = 0.8 V, VEN to VIN, IOUT = 10 mA, freq. = 1 kHz T [°C] Figure 18. Supply voltage rejection vs. temperature 70 60 50 40 30 20 10 0 70 60 50 40 30 20 10 0 -50 75 100 125 150 100 90 80 70 60 50 40 30 20 10 0 IOUT = 10 mA IOUT = 100 mA VIN from 1.7 V to 1.9 V, VEN to VIN, VOUT = 0.8 V, CIN = COUT = 1 µF 0 10 20 30 40 50 60 Freq [kHz] 70 80 90 100 LD39050xx Typical performance characteristics Figure 22. Supply voltage rejection vs. frequency AP - IOUT = 100mA 100 90 5.0 IOUT = 10 mA 80 70 60 50 40 30 20 10 0 VIN from 2.9 V to 3.1 V, VEN to VIN, VOUT = 2.5 V, CIN = COUT = 1 µF 0 10 20 30 40 50 60 Freq [kHz] 70 80 90 AP - IOUT = 10mA 4.5 4.0 IOUT = 100 mA eN [uV/SQRT(Hz)] SVR [dB] Figure 23. Noise output voltage vs. frequency AP - IOUT = 1m AP - IOUT = 0A 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.E+01 100 1.E+02 1.E+03 f [Hz] 1.E+04 1.E+05 VIN = 1.8 V, VOUT = 0.8 V, VEN = 1 V, CIN = COUT = 1 µF, TA = 25 °C Figure 24. Enable voltage vs. temperature 1 1 0.9 0.8 High 0.9 0.8 Low 0.7 0.6 VEN [V] VEN [V] Figure 25. Enable voltage vs. temperature 0.5 0.4 High Low 0.7 0.6 0.5 0.4 0.3 0.2 0.3 0.2 0.1 0 0.1 0 VIN = 3.5 V IOUT = 10 mA, VOUT = 2.5 V, CIN = COUT = 1 µF -50 -25 0 25 50 75 100 125 150 -50 T [°C] Figure 26. Load transient -25 0 25 50 75 100 125 150 T [°C] Figure 27. Load transient VOUT VOUT IOUT IOUT VEN = VIN=1.8 V, IOUT = from10 mA to 0.5 A, CIN = COUT = 1 µF, VOUT = 0.8 V VIN = 5.5 V IOUT = 10 mA VOUT = 2.5 V, CIN = COUT = 1 µF VEN = VIN = 3.5V, IOUT from 10 mA to 0.5 A, VOUT = 2.5 V, CIN = COUT = 1 µF 13/24 Typical performance characteristics Figure 28. Load transient LD39050xx Figure 29. Line transient VOUT VOUT VIN IOUT VEN = VIN = 3.5 V, IOUT from 100 mA to 0.5 A, VOUT = 2.5 V, CIN = COUT = 1 µF VEN = VIN from 4.3 V to 4.8 V, IOUT = 10 mA, COUT = 1 µF, CIN = NO Figure 30. Startup transient Figure 31. Enable transient VOUT VIN VOUT VEN VEN = VIN = from 0 V to 5.5 V, IOUT=10 mA, CIN = COUT = 1 µF, VOUT = 2.5 V VEN from 0 V to 2 V, VIN = 3.5 V, VOUT = 2.5 V, IOUT = 10 mA, CIN = COUT = 1µF Figure 32. ESR required for stability with ceramic capacitors Figure 33. ESR required for stability with ceramic capacitors 1.5 ESR @ 100 kHz [Ω] 1 0.75 STABLE ZONE 0.5 ESR @ 100 kHz [Ω] 1.5 UNSTABLE ZONE 1.25 UNSTABLE ZONE 1.25 1 0.75 0.5 STABLE ZONE 0.25 0.25 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 COUT [µF] (nominal value) VIN = VEN = from 1.8 V to 5.5 V, IOUT = from 1 mA to 500 mA, VOUT = 0.8 V, CIN = 1 µF 14/24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 COUT [µF] (nominal value) VIN = VEN = from 3.5 V to 5.5 V, IOUT = from 1 mA to 500 mA, VOUT = 2.5 V, CIN = 1 µF LD39050xx 6 Application information Application information The LD39050 is an ultra low dropout linear regulator. It provides up to 500 mA with a low 200 mV dropout. The input voltage range is from 1.5 V to 5.5 V. The device is available in fixed and adjustable output versions. The regulator is equipped with internal protection circuitry, such as short-circuit current limiting and thermal protection. The regulator is designed to be stable with ceramic capacitors on the input and the output. The expected values of the input and output ceramic capacitors are from 1 µF to 22 µF with 1 µF typical. The input capacitor must be connected within 0.5 inches of the VIN terminal. The output capacitor must also be connected within 0.5 inches of output pin. There is no upper limit to the value of the input capacitor. Figure 34 and Figure 35 illustrate the typical application schematics: Figure 34. Application schematic for fixed version VIN 6 1 CIN VIN 3 PG LD39050PUxx VOUT EN VOUT 4 OFF ON 1µF GND COUT 5 NC 1µF 2 Figure 35. Application schematic for adjustable version VIN I CIN 1µF 6 VIN 1 EN PG LD39050PU VOUT 3 OFF ON GND 2 ADJ VOUT 4 5 R1 COUT 1µF R2 15/24 Application information LD39050xx For the adjustable version, the output voltage can be adjusted from 0.8 V up to the input voltage minus the voltage drop across the PMOS (dropout voltage), by connecting a resistor divider between the ADJ pin and the output, thus allowing remote voltage sensing. The resistor divider should be selected using the following equation: VOUT = VADJ (1 + R1 / R2) with VADJ = 0.8 V (typ.) It is recommended to use resistors with values in the range of 10 kΩ to 50 kΩ. Lower values can also be suitable, but will increase current consumption. 6.1 Power dissipation An internal thermal feedback loop disables the output voltage if the die temperature rises to approximately 160 °C. This feature protects the device from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without risk of damaging the device. It is very important to use a good PC board layout to maximize power dissipation. The thermal path for the heat generated by the device is from the die to the copper lead frame through the package leads and exposed pad to the PC board copper. The PC board copper acts as a heat sink. The footprint copper pads should be as wide as possible to spread and dissipate the heat to the surrounding ambient. Feed-through vias to inner or backside copper layers are also useful in improving the overall thermal performance of the device. The power dissipation of the device depends on the input voltage, output voltage and output current, and is given by: PD = (VIN -VOUT) IOUT The junction temperature of the device is: TJ_MAX = TA + RthJA x PD where: TJ_MAX is the maximum junction of the die,125 °C; TA is the ambient temperature; RthJA is the thermal resistance junction-to-ambient. 6.2 Enable function The LD39050 features an enable function. When the EN voltage is higher than 2 V the device is ON, and if it is lower than 0.8 V the device is OFF. In shutdown mode, consumption is lower than 1 µA. The EN pin does not have an internal pull-up, which means that it cannot be left floating if it is not used. 6.3 Power Good function Most applications require a flag showing that the output voltage is in the correct range. The Power Good threshold depends on the adjust voltage. When the adjust is higher than 0.92*VADJ, the Power Good (PG) pin goes to high impedance. If the adjust is below 16/24 LD39050xx Application information 0.80*VADJ the PG pin goes to low impedance. If the device is functioning well, the Power Good pin is at high impedance. If the output voltage is fixed using an external or internal resistor divider, the Power Good threshold is 0.92*VOUT. The use of the Power Good function requires an external pull-up resistor, which must be connected between the PG pin and VIN or VOUT. The typical current capability of the PG pin is up to 6 mA. The use of a pull-up resistor for PG in the range of 100 kΩ to 1 MΩ is recommended. If the Power Good function is not used, the PG pin must remain floating. 17/24 Package mechanical data 7 LD39050xx Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 18/24 LD39050xx Package mechanical data DFN6 (3x3 mm) mechanical data mm. inch. Dim. Min. Typ. Max. Min. Typ. Max. A 0.80 0.90 1.00 0.031 0.035 0.039 A1 0 0.02 0.05 0 0.001 0.002 A3 0.20 0.008 b 0.23 0.30 0.38 0.009 0.012 0.015 D 2.90 3.00 3.10 0.114 0.118 0.122 D2 2.23 2.38 2.48 0.088 0.094 0.098 E 2.90 3.00 3.10 0.114 0.118 0.122 E2 1.50 1.65 1.75 0.059 0.065 0.069 e L 0.95 0.30 0.40 0.037 0.50 0.012 0.016 0.020 7946637A 19/24 Package mechanical data LD39050xx Tape & reel QFNxx/DFNxx (3x3) mechanical data mm. inch. Dim. Min. Typ. A Min. Typ. 330 13.2 Max. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 20/24 Max. 0.504 0.519 18.4 0.724 Ao 3.3 0.130 Bo 3.3 0.130 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 LD39050xx Package mechanical data Figure 36. DFN6 (3x3) footprint recommended data 21/24 Different output voltage versions of the LD39050xx available on request LD39050xx 8 Different output voltage versions of the LD39050xx available on request Table 8. Options available on request 22/24 Order codes Output voltages LD39050PU105R 1.05 V LD39050PU15R 1.5 V LD39050PU18R 1.8 V LD39050xx Revision history 9 Revision history Table 9. Document revision history Date Revision 11-Mar-2009 1 Changes Initial release. 23/24 LD39050xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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