TI TPIC5201

SLIS020 − SEPTEMBER 1992
•
•
•
•
•
Two 7.5-A Independent Output Channels,
Continuous Current Per Channel
Low rDS(on) . . . 0.09 Ω Typical
Output Voltage . . . 60 V
Pulsed Current . . . 15 A Per Channel
Avalanche Energy . . . 120 mJ
KV PACKAGE
(TOP VIEW)
7
6
5
4
3
2
1
description
SOURCE2
DRAIN2
GATE2
GND
DRAIN1
SOURCE1
GATE1
The TPIC5201 is a power monolithic DMOS array
that consists of dual independent N-channel
enhancement-mode DMOS transistors.
schematic
GATE2
DRAIN1
DRAIN2
3
5
To ensure correct device operation, the source and the drain of the
same transistor cannot simultaneously be taken below GND.
6
The tab is electrically connected to GND.
GATE1
1
2
4
GND
7
SOURCE1
SOURCE2
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Drain-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Source-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Drain-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Gate-source voltage, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V
Continuous source-drain diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 A
Pulsed drain current, each output, all outputs on, ID (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 A
Continuous drain current, each output, all outputs on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 A
Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mJ
Continuous power dissipation at (or below) TA = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W
Continuous power dissipation at (or below) TC = 75°C, all outputs on (see Note 2) . . . . . . . . . . . . . . . 31 W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTES: 1. Pulse duration = 10 ms, duty cycle = 6%
2. For operation above 25°C free-air temperature, derate linearly at the rate of 16 mW/°C. For operation above 75°C case temperature,
and with all outputs conducting, derate linearly at the rate of 0.42 W/°C. To avoid exceeding the design maximum virtual junction
temperature, these ratings should not be exceeded.
Copyright  1992, Texas Instruments Incorporated
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2−1
SLIS020 − SEPTEMBER 1992
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
V(BR)DS
VTGS
Drain-source breakdown voltage
Gate-source threshold voltage
ID = 1 µA,
ID = 1 mA,
VDS(on)
Drain-source on-state voltage
ID = 7.5 A,
VGS = 0
VDS = VGS
VGS = 15 V, See Notes 3 and 4
VDSS
Zero-gate-voltage drain current
VDS = 48 V,
VDS = 0
IGSSF
Forward gate current, drain short
circuited to source
VGS = 20 V,
IGSSR
TYP
MAX
1.75
2.4
V
0.68
0.94
V
60
1.2
V
0.07
1
1.3
10
VDS = 0
10
100
nA
Reverse gate current, drain short
circuited to source
VGS = − 20 V, VDS = 0
10
100
nA
Static drain-source on-state
resistance
VGS = 15 V,
ID = 7.5 A,
See Notes 3 and 4 and Figures 5 and 6
0.09
0.125
rDS(on)
0.15
0.21
gfs
Forward transconductance
VDS = 15 V,
Ciss
Short-circuit input capacitance,
common source
Coss
Short-circuit output capacitance,
common source
Crss
Short-circuit reverse transfer
capacitance, common source
ID = 5 A,
TC = 25°C
TC = 125°C
UNIT
TC = 25°C
TC = 125°C
See Notes 3 and 4
2.5
4.7
µA
A
Ω
S
490
VDS = 25 V,
VGS = 0,
285
f = 300 kHz
pF
90
NOTES: 3. Technique should limit TJ − TC to 10°C maximum.
4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-drain diode characteristics, TC = 25°C
PARAMETER
VSD
trr
Forward on voltage
QRR
Total source-drain diode charge
TEST CONDITIONS
IS = 7.5 A,
di/dt = 100 A/µs,
See Figure 1
Reverse-recovery time
MIN
VGS = 0,
VDS = 48 V,
TYP
MAX
0.8
1.3
UNIT
V
200
ns
1.5
µC
resistive-load switching characteristics, TC = 25°C
PARAMETER
td(on)
tr
Turn-on delay time
td(off)
tf
Turn-off delay time
Qg
Total gate charge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
Rise time
RL = 6.7 Ω,
See Figure 2
VDD = 25 V,
tdis = 10 ns,
43
ten = 10 ns,
ns
100
Fall time
5
VDD = 48 V,
See Figure 3
ID = 2.5 A,
VGS = 15,
13.6
18
8.3
11
5.3
7
Qgs
Gate-source charge
Qgd
Gate-drain charge
LD
LS
Internal drain inductance
7
Internal source inductance
7
nC
nH
thermal resistance
PARAMETER
TEST CONDITIONS
RθJA
Junction-to-ambient thermal resistance
RθJC
Junction-to-case thermal resistance
2−2
MAX
UNIT
All outputs with equal power
62.5
°C/W
All outputs with equal power
2.4
°C/W
One output dissipating power
3.3
°C/W
•
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•
MIN
TYP
SLIS020 − SEPTEMBER 1992
PARAMETER MEASUREMENT INFORMATION
7.5 A
di/dt = 100 A/µs
QRR = Shaded Area
IS
0
25% of IRM
IRM
(see Note A)
trr
NOTE A: IRM = maximum recovery current
Figure 1. Reverse-Recovery-Current Waveforms of Source-Drain Diode
25 V
ten
VGS
VDS
Pulse Generator
tdis
90%
RL
10%
15 V
90%
0
VGS
DUT
Rgen
50 Ω
td(off)
td(on)
50 Ω
90%
VDS
10%
VDD
VDS(on)
tr
tf
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 2. Resistive Switching
•
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•
2−3
SLIS020 − SEPTEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Current
Regulator
12-V
Battery
0.2 µF
Qg
Same Type
as DUT
50 kΩ
10 V
0.3 µF
Qgd
VGS
VDD = 48 V
DUT
IG = 1 mA
0
Gate Voltage
Time
IG CurrentSampling Resistor
ID CurrentSampling Resistor
Qgs = Qg − Qgd
WAVEFORM
TEST CIRCUIT
Figure 3. Gate Charge Test Circuit and Waveform
25 V
tw
15 V
2.5 mH
VGS
ID
Pulse Generator
50 Ω
0
VDS
VGS
IAS
(see Note B)
ID
DUT
0
Rgen
50 Ω
tav
V(BR)DSX = 60 V MIN
VDS
0
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration (tw) is increased until peak current IAS = 7.5 A.
I
V
t av
AS
(BR)DSX
Energy test level is defined as E
+
+ 120 mJ min.
AS
2
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
2−4
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•
SLIS020 − SEPTEMBER 1992
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
CASE TEMPERATURE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
1
0.3
TC = 25°C
ID = 7.5 A
VGS = 5 V
rDS(on) − Static Drain-Source
On-State Resistance − Ω
rDS(on) − Static Drain-Source
On-State Resistance − Ω
0.25
VGS = 5 V
0.2
VGS = 10 V
0.15
0.1
VGS = 15 V
VGS = 10 V
VGS = 15 V
0.1
VGS = 20 V
VGS = 20 V
0.05
0
− 50
0.01
− 25
0
25
50
75
100
0
125
3
TC − Case Temperature − °C
Figure 5
15
Figure 6
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
25
15
VGS = 5 V
VGS = 10 V
TC = 25°C
ID = 7.5 A
VDS = 15 V
12
I D − Drain Current − A
20
Percentage of Units − %
6
9
12
ID − Drain Current − A
15
10
TC = 25°C
VGS = 4.5 V
VGS = 4 V
9
VGS = 3.5 V
6
VGS = 3 V
5
3
0
0
4.6
0
4.65
4.7
4.75
4.8
gfs − Forward Transconductance − S
5
Figure 7
10 15 20 25 30 35 40 45
VDS − Drain-to-Source Voltage − V
50
Figure 8
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2−5
SLIS020 − SEPTEMBER 1992
TYPICAL CHARACTERISTICS
GATE-SOURCE THRESHOLD VOLTAGE
vs
CASE TEMPERATURE
SOURCE-DRAIN DIODE CURRENT
vs
SOURCE-DRAIN VOLTAGE
100
ID = 1 mA
1.8
I SD − Source-Drain Diode Current − A
VTGS − Gate-Source Threshold Voltage − V
2
1.6
1.4
1.2
1
0.8
0.6
0.4
10
TC = 125°C
TC = − 40°C
1
TC = 25°C
0.2
0
− 50
0.1
− 25
0
50
25
75
100
0
125
0.5
1
1.5
VSD − Source-Drain Voltage − V
TC − Case Temperature − °C
Figure 9
Figure 10
GATE-SOURCE VOLTAGE
vs
GATE CHARGE
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
16
300
ID = 2.5 A
TC = 25°C
TC = 25°C
t rr − Reverse-Recovery Time − ns
14
VGS − Gate-Source Voltage − V
2
12
VDS = 20 V
10
8
6
VDS = 30 V
4
VDS = 48 V
250
200
150
100
50
2
0
0
0
1.5
3
4.5
6
7.5
9
10.5 12 13.5 15
0
100
Q − Gate Charge − nC
300
Reverse di/dt − A/µs
Figure 11
2−6
200
Figure 12
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•
400
500
SLIS020 − SEPTEMBER 1992
TYPICAL CHARACTERISTICS
VDS = 37.5 V
35
V DS − Drain-Source Voltage − V
16
RL = 7.5 Ω
IG = 100 µA
TC = 25°C
14
30
12
Gate-Source
Voltage
VDS = 25 V
25
10
VDS = 37.5 V
20
8
VDS = 25 V
15
6
VDS = 12.5 V
10
4
VGS − Gate-Source Voltage − V
40
2
5
Drain-Source Voltage
0
0
50
100
150
200
250
300
350
400
450
500
t − Time − µs
Figure 13. Resistive Switching Waveforms
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•
2−7
SLIS020 − SEPTEMBER 1992
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-SOURCE VOLTAGE
MAXIMUM PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
100
I AS − Maximum Peak Avalanche Current − A
100
I D − Maximum Drain Current − A
TC = 25°C
rDS(on) Limit
15 A
1 ms
10
7.5 A
DC
1
0.1
1
TC = 25°C
TC = 125°C
1
0.01
100
10
10
VDS − Drain-Source Voltage − V
0.1
1
10
tav − Time Duration of Avalanche − ms
Figure 14
Figure 15
r(t) − Normalized Transient Resistance
NORMALIZED TRANSIENT THERMAL IMPEDANCE
vs
SQUARE-WAVE PULSE DURATION
1
0.8
0.6
d=1
0.4
0.5
TC = 25°C
0.2
0.2
0.1
0.1
0.08
0.06
0.05
0.04
0.02
tc
Single Pulse
tw
ID
0
0.02
0.01
0.01
0.01
0.1
10
1
100
tw − Pulse Duration − ms
NOTES: ZθJC(t) = r(t) RθJC
t w + pulse duration
t c + period
d + duty cycle + t wńt c
Figure 16
2−8
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•
1000
10000
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPIC5201KC
OBSOLETE
TO-220
KC
7
TBD
Call TI
Call TI
TPIC5201KV
OBSOLETE
TO-220
KV
7
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSOT010 – OCTOBER 1994
KC (R-PSFM-T7)
PLASTIC FLANGE-MOUNT PACKAGE
0.156 (3,96)
0.146 (3,71)
0.420 (10,67)
0.380 (9,65)
DIA
0.113 (2,87)
0.103 (2,62)
0.185 (4,70)
0.175 (4,46)
0.055 (1,40)
0.045 (1,14)
0.147 (3,73)
0.137 (3,48)
0.335 (8,51)
0.325 (8,25)
1.020 (25,91)
1.000 (25,40)
1
7
0.125 (3,18)
(see Note C)
0.030 (0,76)
0.026 (0,66)
0.010 (0,25) M
0.050 (1,27)
0.300 (7,62)
0.122 (3,10)
0.102 (2,59)
0.025 (0,64)
0.012 (0,30)
4040251 / B 01/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Lead dimensions are not controlled within this area.
All lead dimensions apply before solder dip.
The center lead is in electrical contact with the mounting tab.
POST OFFICE BOX 655303
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1
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