TC74VHC9125,9126P/FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC9125P,TC74VHC9125FT,TC74VHC9125FK, TC74VHC9126P,TC74VHC9126FT,TC74VHC9126FK TC74VHC9125P/FT/FK 5-bit Universal Schmitt Buffer with 3-State Outputs TC74VHC9126P/FT/FK 5-bit Universal Schmitt Buffer with 3-State Outputs TC74VHC9125P, TC74VHC9126P The TC74VHC9125/9126 are an ultra-high-speed 5-bit Schmitt buffer fabricated using silicon-gate CMOS technology. The TC74VHC9125/9126 combines low power consumption of CMOS with Schottky TTL speeds. Y1 to Y4 outputs can be put in the high-impedance state by placing a logic HIGH on the Enable ( G ) input. The CONT input determines the logical inversion of data.A logic LOW on the CONT input configures the TC74VHC9125/9126 as an inverter; a logic HIGH on the CONT input configures the TC74VHC9125/9126 as a buffer. TC74VHC9125 Y5 output is an inverting type, and the TC74VHC9126 Y5 output is a non-inverting type. All the inputs have hysteresis between the positive-going and negative-going thresholds. Thus the TC74VHC9125/9126 are capable of squaring up transitions of slowly changing input signals and provides an improved noise immunity. Additionally, all the inputs have a newly developed protection circuit without a diode returned to VCC. This enables the inputs to be tolerant of up to 5 volts even when power supply is down. The input power-down protection capability makes the TC74VHC9125/9126 ideal for a wide range of applications, such as interfacing between different voltages, voltage translation from 5 V to 3 V and battery back-up circuits. TC74VHC9125FT, TC74VHC9126FT TC74VHC9125FK, TC74VHC9126FK Features • High speed: tpd = 5.0 ns (typ.) (VCC = 5 V) • Low supply current: ICC = 2 μA (max) (Ta = 25°C) • High noise immunity: VNIH = VNIL = 28% VCC (min) • • All inputs are provided with power-down protection. Symmetrical rise and fall delays: tpLH ∼ − tpHL • Wide operating voltage range: VCC (opr) = 2 to 5.5 V Weight DIP14-P-300-2.54: TSSOP14-P-0044-0.65A: VSSOP14-P-0030-0.50: 1 0.96 g ( typ.) 0.06 g ( typ.) 0.02 g ( typ.) 2008-02-01 TC74VHC9125,9126P/FT/FK Pin Assignment TC74VHC9125 TC74VHC9126 CONT 1 14 VCC Y1 A1 2 13 Y1 12 Y2 A2 3 12 Y2 4 11 Y3 A3 4 11 Y3 A4 5 10 Y4 A4 5 10 Y4 A5 6 9 Y5 A5 6 9 Y5 GND 7 8 G GND 7 8 G CONT 1 14 VCC A1 2 13 A2 3 A3 (top view) (top view) Truth Table Inputs Outputs Inputs Outputs G CONT A1～4 Y1～4 A5 Y5(9125) Y5(9126) H X X Z L H L L L L H H L H L L H L L H L L L H H H X : Don’t care Z : High impedance 2 2008-02-01 TC74VHC9125,9126P/FT/FK Absolute Maximum Ratings (Note1) Characteristics Symbol Rating Unit Supply voltage range VCC −0.5 to 7.0 V DC input voltage VIN −0.5 to 7.0 V VOUT −0.5 to VCC + 0.5 V Input diode current IIK −20 mA Output diode current IOK ±20 mA DC output current IOUT ±25 mA DC VCC/ground current ICC ±50 mA Power dissipation PD 500 (DIP) (Note 2)/180(TSSOP/VSSOP) mW Storage temperature Tstg −65 to 150 °C DC output voltage Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be applied until 300 mW. Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage VCC 2.0 to 5.5 V Input voltage VIN 0 to 5.5 V VOUT 0 to VCC V Topr −40 to 85 °C Output voltage Operating temperature Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 3 2008-02-01 TC74VHC9125,9126P/FT/FK Electrical Characteristics DC Characteristics Characteristics Positive threshold voltage Negative threshold voltage Hysteresis voltage Test Condition Symbol ― VP ― VN VH ― VOH VOL VCC (V) Min Typ. Max Min Max 3.0 ― ― 2.20 ― 2.20 4.5 ― ― 3.15 ― 3.15 5.5 ― ― 3.85 ― 3.85 3.0 0.90 ― ― 0.90 ― 4.5 1.35 ― ― 1.35 ― 5.5 1.65 ― ― 1.65 ― 3.0 0.30 ― 1.20 0.30 1.20 4.5 0.40 ― 1.40 0.40 1.40 Unit V V 5.5 0.50 ― 1.60 0.50 1.60 1.9 2.0 ― 1.9 ― 3.0 2.9 3.0 ― 2.9 ― 4.5 4.4 4.5 ― 4.4 ― IOH = −4 mA 3.0 2.58 ― ― 2.48 ― IOH = −8 mA 4.5 3.94 ― ― 3.80 ― 2.0 ― 0.0 0.1 ― 0.1 3.0 ― 0.0 0.1 ― 0.1 4.5 ― 0.0 0.1 ― 0.1 IOL = 4 mA 3.0 ― ― 0.36 ― 0.44 IOL = 8 mA 4.5 ― ― 0.36 ― 0.44 5.5 ― ― ±0.25 ― ±2.50 μA VIN = VIH or VIL IOL = 50 μA Low-level output voltage Ta = −40 to 85°C 2.0 IOH = −50 μA High-level output voltage Ta = 25°C VIN = VIH or VIL VIN = VIH or VIL V 3-state output off-state current IOZ Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5 ― ― ±0.1 ― ±1.0 μA Quiescent supply current ICC VIN = VCC or GND 5.5 ― ― 2.0 ― 20.0 μA VOUT = VCC or GND 4 2008-02-01 TC74VHC9125,9126P/FT/FK AC Characteristics (input: tr = tf = 3 ns) Characteristics Propagation delay time tpLH (A1 to 4 - Y1 to 4) tpHL Propagation delay time tpLH (CONT-Y1 to 4) tpHL Propagation delay time tpLH (A5 – Y5) tpHL 3-state output enable time 3-state output disable time tpZL tpZH tpLZ tpHZ Output to output skew tosLH (A1 to 4 - Y1 to 4) tosHL Input capacitance Output capacitance Power dissipation capacitance (Note 2) Test Condition Symbol VCC (V) Ta = 25°C CL (pF) Min Typ. Max Min Max 15 ― 6.0 8.0 1.0 10.0 50 ― 9.0 12.5 1.0 15.0 15 ― 5.0 5.5 1.0 7.0 50 ― 7.0 8.5 1.0 10.0 15 ― 8.5 11.5 1.0 13.5 50 ― 13.0 17.0 1.0 20.5 15 ― 6.5 8.0 1.0 9.5 50 ― 10.5 12.5 1.0 15.0 15 ― 6.0 8.0 1.0 10.0 50 ― 9.0 12.5 1.0 15.0 15 ― 5.0 5.5 1.0 7.0 50 ― 7.0 8.5 1.0 10.0 15 ― 6.0 8.0 1.0 9.5 50 ― 10.5 13.5 1.0 16.5 15 ― 4.5 5.5 1.0 6.5 50 ― 9.0 10.5 1.0 12.5 3.3 ± 0.3 50 ― 12.5 13.5 1.0 16.0 5.0 ± 0.5 50 ― 9.0 9.5 1.0 11.0 3.3 ± 0.3 50 ― ― 1.5 ― 1.5 5.0 ± 0.5 50 ― ― 1.0 ― 1.0 3.3 ± 0.3 ― 5.0 ± 0.5 3.3 ± 0.3 ― 5.0 ± 0.5 3.3 ± 0.3 ― 5.0 ± 0.5 3.3 ± 0.3 RL = 1 kΩ 5.0 ± 0.5 RL = 1 kΩ (Note 1) Ta = −40 to 85°C Unit ns ns ns ns ns ns CIN ― ― ― ― 4 10 ― 10 pF COUT ― ― ― ― 6 ― ― ― pF ― ― ― 10 ― ― ― pF CPD fIN = 1 MHz Note 1: Parameter guaranteed by design. tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn| Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD·VCC·fIN + ICC / 5 (per bit) 5 2008-02-01 TC74VHC9125,9126P/FT/FK Input Equivalent Circuit Input 6 2008-02-01 TC74VHC9125,9126P/FT/FK Package Dimensions Weight: 0.96 g (typ.) 7 2008-02-01 TC74VHC9125,9126P/FT/FK Package Dimensions Weight: 0.06 g (typ.) 8 2008-02-01 TC74VHC9125,9126P/FT/FK Package Dimensions Weight: 0.02 g (typ.) 9 2008-02-01 TC74VHC9125,9126P/FT/FK RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively “Product”) without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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