ONSEMI MC74LVX125_11

MC74LVX125
Quad Bus Buffer
With 5 V−Tolerant Inputs
The MC74LVX125 is an advanced high speed CMOS quad bus
buffer. The inputs tolerate voltages up to 7.0 V, allowing the interface
of 5.0 V systems to 3.0 V systems.
The MC74LVX125 requires the 3−state control input (OE) to be set
High to place the output into the high impedance state.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
High Speed: tPD = 4.4 ns (Typ) at VCC = 3.3 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: VOLP = 0.5 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
14
SOIC−14
D SUFFIX
CASE 751A
14
1
LVX125G
AWLYWW
1
14
14
ESD Performance:
Human Body Model >2000 V
Machine Model >200 V
These Devices are Pb−Free and are RoHS Compliant
1
TSSOP−14
DT SUFFIX
CASE 948G
1
LVX
125
ALYWG
G
14
14
1
LVX125
ALYWG
SOEIAJ−14
M SUFFIX
CASE 965
1
LVX125 = Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 3
1
Publication Order Number:
MC74LVX125/D
MC74LVX125
VCC
OE3
D3
O3
OE2
D2
O2
14
13
12
11
10
9
8
1
OE0
2
D0
2
3
4
5
6
7
OE0
D0
O0
OE1
D1
O1
GND
3
O0
D2
4
OE1
1
OE2
OE3
5
D1
Figure 1. 14−Lead Pinout (Top View)
6
O1
D3
10
9
8
O2
13
12
11
O3
Figure 2. Logic Diagram
PIN NAMES
FUNCTION TABLE
Pins
Function
OEn
Dn
On
Output Enable Inputs
Data Inputs
3−State Outputs
INPUTS
OUTPUTS
OEn
Dn
On
L
L
H
L
H
X
L
H
Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions Are
Acceptable, for ICC reasons, DO NOT FLOAT Inputs
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
–0.5 to +7.0
V
Vin
DC Input Voltage
–0.5 to +7.0
V
Vout
DC Output Voltage
–0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation
180
mW
Tstg
Storage Temperature
–65 to +150
_C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
3.6
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
TA
Operating Temperature, All Package Types
−40
+85
_C
Dt/DV
Input Rise and Fall Time
0
100
ns/V
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2
MC74LVX125
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DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
TA = 25°C
VCC
V
Min
1.5
2.0
2.4
VIH
High−Level Input
Voltage
2.0
3.0
3.6
VIL
Low−Level Input Voltage
2.0
3.0
3.6
VOH
High−Level Output
Voltage
(Vin = VIH or VIL)
IOH = −50mA
IOH = −50mA
IOH = −4mA
2.0
3.0
3.0
VOL
Low−Level Output
Voltage
(Vin = VIH or VIL)
IOL = 50mA
IOL = 50mA
IOL = 4mA
2.0
3.0
3.0
Iin
Input Leakage Current
Vin = 5.5V or GND
IOZ
Maximum Three−State
Leakage Current
ICC
Quiescent Supply
Current
Typ
TA = − 40 to 85°C
Max
Min
Max
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.58
V
0.5
0.8
0.8
2.0
3.0
1.9
2.9
2.48
0.0
0.0
Unit
V
V
0.1
0.1
0.36
0.1
0.1
0.44
V
3.6
±0.1
±1.0
mA
Vin = VIL or VIH
Vout = VCC or GND
3.6
±0.25
±2.5
mA
Vin = VCC or GND
3.6
4.0
40.0
mA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSHL
tOSLH
Parameter
Test Conditions
Propagation Delay
Input to Output
Output Enable Time
OE to O
Output Disable Time
OE to O
Output−to−Output Skew
(Note 1)
Min
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
ns
VCC = 2.7V
CL = 15pF
CL = 50pF
5.8
8.3
10.1
13.6
1.0
1.0
13.5
17.0
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
4.4
6.9
6.2
9.7
1.0
1.0
8.5
12.0
VCC = 2.7V
RL =1kW
CL = 15pF
CL = 50pF
5.3
7.8
9.3
12.8
1.0
1.0
12.5
16.0
VCC = 3.3 ± 0.3V
RL =1kW
CL = 15pF
CL = 50pF
4.0
6.5
5.6
9.1
1.0
1.0
7.5
11.0
VCC = 2.7V
RL =1kW
CL = 50pF
10.0
15.7
1.0
19.0
VCC = 3.3 ± 0.3V
RL =1kW
CL = 50pF
8.3
11.2
1.0
13.0
VCC = 2.7V
VCC = 3.3 ±0.3V
CL = 50pF
CL = 50pF
1.5
1.5
1.5
1.5
ns
ns
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
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CAPACITIVE CHARACTERISTICS
TA = 25°C
Symbol
Min
Parameter
TA = − 40 to 85°C
Typ
Max
10
Min
Max
Unit
10
pF
Cin
Input Capacitance
4
Cout
Maximum Three−State Output Capacitance
6
pF
CPD
Power Dissipation Capacitance (Note 2)
14
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per bit). CPD is used to determine the no−load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
MC74LVX125
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.5
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.3
−0.5
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
ORDERING INFORMATION
Package
Shipping†
MC74LVX125DG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74LVX125DR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
MC74LVX125DTG
TSSOP−14*
96 Units / Rail
MC74LVX125DTR2G
TSSOP−14*
2500 Tape & Reel
MC74LVX125MG
SOEIAJ−14
2000 Tape & Reel
MC74LVX125MELG
SOEIAJ−14
2000 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
SWITCHING WAVEFORMS
VCC
VCC
D
OE
50%
50%
GND
GND
tPLH
O
tPZL
tPHL
O
50% VCC
HIGH
IMPEDANCE
50% VCC
tPZH
O
tPLZ
tPHZ
VOL +0.3V
VOH -0.3V
50% VCC
Figure 3.
HIGH
IMPEDANCE
Figure 4.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 5. Propagation Delay Test Circuit
Figure 6. Three−State Test Circuit
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4
MC74LVX125
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
B
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
M
S
SOLDERING FOOTPRINT
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
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5
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC74LVX125
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
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6
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74LVX125
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
14
LE
8
Q1
E HE
M_
L
7
1
DETAIL P
Z
D
VIEW P
A
e
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.10 (0.004)
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--1.42
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.056
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MC74LVX125/D