TQP3M9035 High Linearity LNA Gain Block Applications • • • • • Repeaters Mobile Infrastructure LTE / WCDMA / CDMA / GSM General Purpose Wireless TDD or FDD systems 2x2 mm 8 Pin DFN Package Product Features • • • • • • • • • • Functional Block Diagram Pin 1 Reference Mark 50−4000 MHz Operating Range 0.65 dB Noise Figure @ 1900 MHz 16.5 dB Gain @ 1900 MHz +37 dBm Output IP3 +22.5 dBm P1dB Shut-down capability Unconditionally stable 50 Ohm Cascadable Gain Block +5V Single Supply, 115 mA Current 2x2 mm 8 Pin DFN plastic package NC 1 8 NC RF In 2 7 RF Out NC 3 6 Shut Down NC 4 5 NC Backside Paddle - RF/DC GND General Description Pin Configuration The TQP3M9035 is a high-linearity, low noise gain block amplifier in a low-cost surface-mount package. At 1900 MHz, the amplifier typically provides 16.5 dB gain, +37 dBm OIP3, and 0.65 dB Noise Figure. The LNA is also designed to be broadband without the requirement for external matching. The device is housed in a lead-free/green/RoHS-compliant industrystandard 2x2 mm package. The TQP3M9035 has the benefit of having high linearity while also providing very low noise across a broad range of frequencies. This allows the device to be used in both receive and transmit chains for high performance systems. The amplifier is internally matched using a high performance E-pHEMT process and only requires an external RF choke and blocking/bypass capacitors for operation from a single +5V supply. The low noise amplifier integrates a shutdown biasing capability to allow for operation for TDD applications. The TQP3M9035 covers the 50−4000 MHz frequency band and is targeted for wireless infrastructure or other applications requiring high linearity and/or low noise figure. Pin # Symbol Backside Paddle RF/DC GND 1, 3, 4, 5, 8 2 6 7 No Connect or GND RF In Shut Down RF Out Ordering Information Part No. TQP3M9035 TQP3M9035-PCB Description High Linearity LNA Gain Block 500−4000 MHz Eval. Board Standard T/R size = 2500 pieces on a 7” reel. Data Sheet: Rev E 10/29/2012 © 2012 TriQuint Semiconductor, Inc. - 1 of 9 - Disclaimer: Subject to change without notice ® Connecting the Digital World to the Global Network TQP3M9035 High Linearity LNA Gain Block Absolute Maximum Ratings Recommended Operating Conditions Parameter Parameter Storage Temperature Supply Voltage (VDD) RF Input Power, CW, 50Ω,T = 25°C Rating Supply Voltage (VDD) TCASE TJ (for >106 hours MTTF) −65 to 150°C +6 V +23 dBm Operation of this device outside the parameter ranges given above may cause permanent damage. Min Typ Max Units +4.75 −40 +5 +5.25 +85 190 V °C °C Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions. Electrical Specifications Test conditions unless otherwise noted: +25°C, VDD =+5V, 50 Ω system. Parameter Operational Frequency Range Test Frequency Gain Input Return Loss Output Return Loss Output P1dB Output IP3 Noise Figure Power Shutdown Control (Pin 6) Current, IDD Shutdown pin current, ISD Thermal Resistance, θjc Conditions Min 50 15 Pout=+4 dBm/tone, Δf=1 MHz On state Off state (Power down) On state Off state (Power down) VPD ≥ 3 V channel to case Data Sheet: Rev E 10/29/2012 © 2012 TriQuint Semiconductor, Inc. - 2 of 9 - +20 +32.5 Typ 1900 16.5 13 10 +23 +37 0.65 0 3 115 3 100 Max 4000 18 1.0 0.8 VDD 150 50 Units MHz MHz dB dB dB dBm dBm dB V V mA mA µA °C/W Disclaimer: Subject to change without notice ® Connecting the Digital World to the Global Network TQP3M9035 High Linearity LNA Gain Block Device Characterization Data S-Parameters Test conditions unless otherwise noted: VDD=+5 V, IDD=115 mA (typ.), Temp=+25°C, 50 Ohm system Freq (GHz) S11 (dB) S11 (ang) S21 (dB) S21 (ang) S12 (dB) S12 (ang) S22 (dB) S22 (ang) 50 100 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 -11.5 -13.8 -14.8 -15.0 -15.0 -14.9 -15.0 -15.0 -15.1 -15.2 -15.4 -15.6 -15.8 -15.9 -16.1 -16.1 -16.5 -16.4 -16.0 -15.4 -14.8 -14.2 -43.9 -43.3 -50.7 -74.6 -93.2 -106.9 -117.2 -125.4 -131.8 -137.5 -142.3 -147.1 -151.7 -156.6 -161.5 -166.5 -174.6 179.5 176.3 173.5 170.9 169.0 28.8 28.2 27.6 26.1 24.5 23.0 21.6 20.4 19.4 18.5 17.6 16.9 16.2 15.6 15.0 14.5 14.0 13.6 13.2 12.8 12.5 12.2 165.0 161.3 151.4 132.1 116.9 104.8 94.8 86.1 78.2 71.0 64.2 57.7 51.4 45.4 39.5 33.6 27.9 22.3 16.8 11.2 5.6 -0.1 -31.8 -31.5 -31.4 -31.4 -31.3 -30.9 -30.3 -29.7 -29.0 -28.3 -27.6 -27.0 -26.4 -25.9 -25.4 -25.0 -24.6 -24.2 -23.8 -23.5 -23.2 -22.9 13.5 8.5 6.5 9.2 13.3 17.6 21.5 23.5 25.1 25.8 25.5 25.1 24.4 22.8 21.2 19.3 17.4 15.1 12.8 10.3 7.9 4.7 -22.0 -26.5 -20.1 -14.9 -13.1 -12.2 -11.8 -11.6 -11.4 -11.2 -11.0 -10.7 -10.4 -10.1 -9.7 -9.3 -8.7 -8.3 -8.0 -7.8 -7.6 -7.4 -106.8 172.1 99.9 57.7 35.6 19.5 6.5 -5.1 -16.0 -26.4 -36.2 -45.5 -54.5 -62.8 -70.6 -77.8 -82.9 -88.4 -94.5 -100.7 -106.8 -113.2 Noise Parameters Test conditions unless otherwise noted: VDD=+5 V, IDD=115 mA (typ.), Temp=+25°C, 50 Ohm system Freq (MHz) 700 1100 1500 1900 2300 2700 NFmin (dB) 0.41 0.50 0.59 0.49 0.59 0.74 MagOpt (mag) 0.100 0.127 0.113 0.229 0.267 0.300 Data Sheet: Rev E 10/29/2012 © 2012 TriQuint Semiconductor, Inc. AngOpt (deg) 118 140 165 166 179 -166 - 3 of 9 - Rn (Ω) 0.046 0.048 0.060 0.045 0.048 0.051 Disclaimer: Subject to change without notice ® Connecting the Digital World to the Global Network TQP3M9035 High Linearity LNA Gain Block TQP3M9035-PCB Evaluation Board J5 C4 J3 J4 J3 VDD 1 uF R 3 J4 GND C3 C4 C3 100 pF L1 68 nH (0603) C2 L1 U1 C1 C2 J1 R2 R1 RF Input C1 2 6 100 pF 1,3,4,5,8 J2 7 Q1 100 pF RF Output R2 33k Ω J5 PD R1 See note 6. Resistors are 10k Ω not needed if shut-down C5 functionality is not used. C6 Notes: 1. See Evaluation Board PCB Information section for material and stack-up. 2. R3 (0 Ω jumper) is not shown on the schematic and may be replaced with copper trace in the target application layout. 3. All components are of 0402 size unless stated on the schematic. 4. C1, C2, and C3 are non-critical values. The reactive impedance should be as low as possible at the frequency of operation for optimal performance. 5. The L1 value is non-critical and needs to provide high reactive impedance at the frequency of operation. 6. R1 and R2 are optional and do not need to be loaded if the shut-down functionality is not needed; i.e. FDD applications. If R1 and R2 are not loaded, the LNA will operate in its standard “ON” state. 7. A through line is included on the evaluation board to de-embed the board losses. Bill of Material - TQP3M9035-PCB Reference Des. N/A Value N/A Description Printed Circuit Board Manuf. TriQuint Part Number 1084112 U1 n/a High Linearity LNA Gain Block TriQuint TQP3M9035 R1 10K Ω Resistor, Chip, 0402, 5%, 1/16W various various R2 33K Ω Resistor, Chip, 0402, 5%, 1/16W various various R3 0Ω Resistor, Chip, 0402, 5%, 1/16W various various L1 68 nH Inductor, 0603, 5%, Ceramic various various C4 1.0 uF Cap., Chip, 0402, 10%, 10V, X5R various various C1, C2, C3, C5, C6 100 pF Cap., Chip, 0402, 5%, 50V, NPO/COG various various Solder Turret various various J3, J4, J5 n/a Data Sheet: Rev E 10/29/2012 © 2012 TriQuint Semiconductor, Inc. - 4 of 9 - Disclaimer: Subject to change without notice ® Connecting the Digital World to the Global Network TQP3M9035 High Linearity LNA Gain Block Typical Performance TQP3M9035-PCB VDD = 5 V Test conditions unless otherwise noted: VDD=+5 V, IDD=110 mA (typ.), Temp=+25°C Parameter Conditions Frequency Gain Input Return Loss Output Return Loss Output P1dB Output IP3 Noise figure (1) 900 22.0 14 13 +23 +37.2 0.55 Pout= +4 dBm/tone, Δf=1 MHz Typical Value 1900 16.5 13 10 +23 +37.0 0.65 Units 2600 14.0 15 8 +23 +37.3 1.0 MHz dB dB dB dBm dBm dB Notes: 1. Noise figure data shown in the table above is de-embedded from the eval board loss. Performance Plots - TQP3M9035-PCB VDD = 5 V Gain vs. Frequency Input Return Loss (dB) 20 15 10 5 0 500 1000 1500 2000 2500 Frequency (MHz) 3000 3500 P1dB vs. Frequency 25 23 22 21 -15 -15 -20 -20 0 500 1000 1500 2000 2500 Frequency (MHz) 3000 3500 -25 4000 OIP3 vs. Pout/tone 500 1000 1500 2000 2500 Frequency (MHz) 3000 3500 4000 500 1000 1500 2000 2500 Frequency (MHz) 3000 3500 4000 Noise Figure vs. Frequency 900 MHz 1900 MHz 1.5 2600 MHz 40 35 25 0 2 1 0.5 30 0 Temp.=+25°C -5 -10 45 OIP3 (dBm) P1dB (dBm) -10 50 24 20 -5 -25 4000 Output Return Loss vs. Frequency 0 Temp.=+25°C NF (dB) Gain (dB) 25 0 Input Return Loss vs. Frequency 0 Temp.=+25°C Output Return Loss (dB) 30 0 1 2 3 4 5 Pout/Tone (dBm) 6 7 0 8 0 500 1000 1500 2000 2500 Frequency (MHz) 3000 3500 4000 Idd vs. Shutdown Voltage 140 120 +85 C Idd (mA) 100 +25 C - 40 C 80 60 40 20 0 -20 Data Sheet: Rev E 10/29/2012 © 2012 TriQuint Semiconductor, Inc. 0 1 2 3 Shutdown Voltage (V) - 5 of 9 - 4 5 Disclaimer: Subject to change without notice ® Connecting the Digital World to the Global Network TQP3M9035 High Linearity LNA Gain Block Typical Performance − TQP3M9035-PCB VDD = 3.3 V Test conditions unless otherwise noted: VDD=+3.3 V, IDD=67 mA (typ.), Temp=+25°C Parameter Conditions Frequency Gain Input Return Loss Output Return Loss Output P1dB Output IP3 Noise figure (1) Units Typical Value 900 21.2 11.4 15.6 +19 +32.7 0.55 Pout= +5 dBm/tone, Δf=1 MHz 1900 15.8 11.9 10.6 +18.8 +33 0.65 MHz dB dB dB dBm dBm dB Notes: 1. Noise figure data shown in the table above is de-embedded from the eval board loss. Performance Plots - TQP3M9035-PCB VDD = 3.3 V Test conditions unless otherwise noted: VDD =+3.3 V, IDD = 67 mA, TCASE = +25°C, 50 Ω system Gain vs. Frequency 30 Input Return Loss vs. Frequency 0 Temp.=+25°C Output Return Loss vs. Frequency 0 Temp.=+25°C Temp.=+25°C 25 15 -5 |S22| (dB) |S11| (dB) Gain (dB) -5 20 -10 -10 10 -15 -15 5 0 0 1000 2000 Frequency (MHz) 3000 -20 4000 0 1000 3000 4000 -20 0 1000 2000 Frequency (MHz) 3000 4000 OIP3 vs. Pout/tone 34 Temp.=+25°C 1 MHz tone spacing OIP3 (dBm) 2000 Frequency (MHz) 1900 MHz 900 MHz 33 32 31 0 1 2 Data Sheet: Rev E 10/29/2012 © 2012 TriQuint Semiconductor, Inc. 3 4 5 Pout/Tone (dBm) 6 7 8 - 6 of 9 - Disclaimer: Subject to change without notice ® Connecting the Digital World to the Global Network TQP3M9035 High Linearity LNA Gain Block Pin Configuration and Description Pin 1 Reference Mark NC 1 8 NC RF In 2 7 RF Out NC 3 6 Shut Down NC 4 5 NC Backside Paddle - RF/DC GND Pin No. Symbol Description 2 RF In RF Input pin. A DC Block is required. 6 Shut Down A high voltage turns off the device. If the pin is not connected or is less than 1V, then the device will operate under its normal operating condition. 7 RF Out / DCBias RF Output pin. DC bias will also need to be injected through a RF bias choke/inductor for operation. 1, 3, 4, 5, 8 NC No electrical connection. Provide grounded land pads for PCB mounting integrity. Backside Paddle RF/DC GND RF/DC ground. Use recommended via pattern to minimize inductance and thermal resistance; see PCB Mounting Pattern for suggested footprint. Evaluation Board PCB Information TriQuint PCB 1084112 Material and Stack-up 50 ohm line dimensions: width = .031”, spacing = .035” Data Sheet: Rev E 10/29/2012 © 2012 TriQuint Semiconductor, Inc. - 7 of 9 - Disclaimer: Subject to change without notice ® Connecting the Digital World to the Global Network TQP3M9035 High Linearity LNA Gain Block Mechanical Information Package Marking and Dimensions Marking: Part number – 9035 Lot Code – XXXX 9035 XXXX NOTES: 1. All dimensions are in millimeters. Angles are in degrees. 2. Except where noted, this part outline conforms to JEDEC standard MO-220, Issue E (Variation VGGC) for thermally enhanced plastic very thin fine pitch quad flat no lead package (QFN). 3. Dimension and tolerance formats conform to ASME Y14.4M-1994. 4. The terminal #1 identifier and terminal numbering conform to JESD 95-1 SPP-012. PCB Mounting Pattern NOTES: 1. All dimensions are in millimeters. Angles are in degrees. 2. Use 1 oz. copper minimum for top and bottom layer metal. 3. Vias are required under the backside paddle of this device for proper RF/DC grounding and thermal dissipation. We recommend a 0.35mm (#80/.0135") diameter bit for drilling via holes and a final plated thru diameter of 0.25 mm (0.10”). 4. Ensure good package backside paddle solder attach for reliable operation and best electrical performance. Data Sheet: Rev E 10/29/2012 © 2012 TriQuint Semiconductor, Inc. - 8 of 9 - Disclaimer: Subject to change without notice ® Connecting the Digital World to the Global Network TQP3M9035 High Linearity LNA Gain Block Product Compliance Information ESD Sensitivity Ratings Solderability ESD Rating: Value: Test: Standard: Class 1A Passes ≥ 250 V to < 500 V Human Body Model (HBM) JEDEC Standard JESD22-A114 Package contact plating: NiPdAu ESD Rating: Value: Test: Standard: Class IV Passes ≥ 1000 V Charged Device Model (CDM) JEDEC Standard JESD22-C101 Compatible with both lead-free (260 °C max. reflow temperature) and tin/lead (245 °C max. reflow temperature) soldering processes. RoHs Compliance This part is compliant with EU 2002/95/EC RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment). MSL Rating MSL Rating: Level 1 Test: 260°C convection reflow Standard: JEDEC Standard IPC/JEDEC J-STD-020 This product also has the following attributes: • Lead Free • Halogen Free (Chlorine, Bromine) • Antimony Free • TBBP-A (C15H12Br402) Free • PFOS Free • SVHC Free Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: [email protected] Tel: Fax: For technical questions and application information: +1.503.615.9000 +1.503.615.8902 Email: [email protected] Important Notice The information contained herein is believed to be reliable. TriQuint makes no warranties regarding the information contained herein. TriQuint assumes no responsibility or liability whatsoever for any of the information contained herein. TriQuint assumes no responsibility or liability whatsoever for the use of the information contained herein. The information contained herein is provided "AS IS, WHERE IS" and with all faults, and the entire risk associated with such information is entirely with the user. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for TriQuint products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. TriQuint products are not warranted or authorized for use as critical components in medical, life-saving, or lifesustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Data Sheet: Rev E 10/29/2012 © 2012 TriQuint Semiconductor, Inc. - 9 of 9 - Disclaimer: Subject to change without notice ® Connecting the Digital World to the Global Network