DA6512.000 11 July, 2012 MAS6512 This is preliminary information on a new product under development. Micro Analog Systems Oy reserves the right to make any changes without notice. Capacitive Sensor Signal Interface IC Single or Dual Capacitance Sensors Low Voltage Operation Low Power Consumption On Chip Temperature Sensor Internal Clock Oscillator 16-Bit Ratiometric ∆Σ CDC EEPROM Calibration Memory Serial Interface • • • • • • • • DESCRIPTION MAS6512 capacitive sensor signal Interface IC can interface both single and dual capacitance sensors. It uses a 16-bit Capacitance-to-Digital Converter (CDC), which employs a delta-sigma (∆Σ) conversion technique. The output data from the ∆Σ-modulator is processed by an on-chip decimator filter, producing a high resolution conversion result. The converter is run by an internal clock oscillator making an external converter clock unnecessary. The converter input range is programmable to meet various sensor offset and changing capacitance values. Maximum sensor capacitance is 40pF but higher maximum value can be reached by using slower conversion speed or scaling the signal by using an external series capacitor. The measurement resolution depends on the programmed capacitance range and over sampling ratio (OSR) selections. MAS6512 supports two capacitance measurement modes. The output can be FEATURES • • • • • • • • • • Single and Differential Capacitive Sensors Sensor Offset and Gain Adjustment • Changing Capacitance Range 2pF…30pF • Internal Offset Capacitance Matrix 0pF…22pF • External Capacitance up to 40pF (or higher using external clock) Resolution 14 bit (OSR=4096, ∆C=20pF) Internal Clock Oscillator On Chip Temperature Sensor -40°C...+85°C Low Voltage Operation 1.8 V…3.6 V Low Supply Current: 1.9 µA...28 µA Conversion Time 5.8ms...82.6ms (12Hz...173Hz) 16-bit Ratiometric ∆Σ CDC Internal 256-bit EEPROM Calibration Memory I2C is a registered trademark of NXP. proportional either to capacitance difference (CS-CR) or to capacitance ratio (CS-CR)/CS. The IC is designed especially to meet the requirement for low power consumption, thus making it an ideal choice for battery powered systems. Current consumption values of 28 µA with high resolution or 1.9 µA with low resolution, at a conversion rate of one conversion per second, can be achieved. In addition to measuring capacitance the device has an internal temperature sensor for temperature measurement and temperature compensation purposes. The 256-bit EEPROM memory stores trimming and calibration coefficients on chip. A serial interface, compatible with a bi2 directional 2-wire I C bus and 4-wire SPI bus, is used for conversion setup, starting a conversion and reading the conversion result. APPLICATIONS • • • • • • • • • • • • 2 I C and SPI Compatible Serial Interface QFN-16 Package Capacitive Pressure Sensors Humidity Sensors Medical Devices Flow Meters Sport Watches Altimeter and Barometer Systems Mobile and Battery Powered Systems Low Frequency Measurement applications Current/Power Consumption Critical Systems Industrial and Process Control applications in noisy environments 1 (26) DA6512.000 11 July, 2012 BLOCK DIAGRAM VDD OSCOUT VDD MISO MUX CS CLK OSC I2C / SDA/MOSI SCL/SCLK SPI CC CONTROL XCS XSPI CR EOC ∆Σ XCLR VREG TEMP EEPROM VREG TEST1 TEST TEST2 GND GND Figure 1. MAS6512 block diagram FUNCTIONAL DESCRIPTION MAS6512 can interface both single and dual capacitance sensors. Single capacitance sensors should be connected between the CS and the CC inputs. The second capacitor of a dual capacitance sensor should be connected between the CR and the CC inputs. the EEPROM memory in the beginning of each conversion. To avoid modification of the EEPROM by mistake there is an EEPROM write enable register which needs to be set to %01010101 (55HEX) before any changes can be done to the EEPROM. A Capacitance-to-Digital Converter (CDC) converts the input capacitances into a 16-bit output word (code). The converter front-end can be configured either for capacitance difference (CS-CR) or capacitance ratio (CS-CR)/CS measurement mode. Converter resolution is selected by the over sampling ratio (OSR) setting. Higher OSR corresponds to higher resolution but also longer conversion time. MAS6512 has an internal clock oscillator making an external clock unnecessary. To save power it’s turned on only when a conversion is running. The frequency is trimmed to 200kHz using a 6-bit register. An external clock, connected to the OSCOUT pin, can however be used when a specific test mode is chosen. This might be necessary when measuring large capacitance since a slower clock frequency is needed in this case. There are two internal 22pF capacitance matrices connected to the CS and the CR inputs. These matrices are used for sensor offset calibration and are programmable in 8-bit steps (86fF/step). The gain is programmable with 8-bits resolution and sets the range for how much the measured capacitance can change. MAS6512 includes an internal temperature sensor for temperature compensation purposes. A multiplexer in the front-end is used to select either the external capacitive sensor or the internal temperature sensor. Trim and calibration coefficients can be stored in the 256-bit EEPROM memory. The stored trim values for the oscillator frequency, offset capacitance and gain are automatically read from I2C is a registered trademark of NXP. MAS6512 includes a 1.8V regulator that can be disabled in capacitance measurement mode. In temperature measurement mode the regulator is always used. The regulator is turned off between conversions. Communication with MAS6512 is handled by the serial interface compatible with either a bi2 directional 2-wire I C bus or a 4-wire SPI bus. The XSPI pin is for selecting which bus type is used. The XCLR pin can be used to reset the device including the serial communication. The EOC pin indicates if a conversion has finished and the result is ready to be read from the memory via the serial interface. 2 (26) DA6512.000 11 July, 2012 ABSOLUTE MAXIMUM RATINGS All Voltages with Respect to Ground Parameter Symbol Supply Voltage Voltage Range for All Pins Latchup Current Limit VDD Junction Temperature Storage Temperature TJmax TS ILUT Conditions For all pins, test according to JESD78A. Note 1 Min Max Unit -0.3 -0.3 -100 5.0 VDD + 0.3 +100 V V mA - 55 + 150 +125 °C °C Note 1: See EEPROM memory data retention at hot temperature. Storage or bake at hot temperatures will reduce the wafer level trimming and calibration data retention time. Note: The absolute maximum rating values are stress ratings only. Functional operation of the device at conditions between maximum operating conditions and absolute maximum ratings is not implied and EEPROM contents may be corrupted. Exposure to these conditions for extended periods may affect device reliability (e.g. hot carrier degradation, oxide breakdown). Applying conditions above absolute maximum ratings may be destructive to the devices. Note: This is a CMOS device and therefore it should be handled carefully to avoid any damage by static voltages (ESD). RECOMMENDED OPERATION CONDITIONS Parameter Symbol Conditions Min Typ Max Unit Supply Voltage VDD VDD 1.8 1.9 3.0 2.7 2.7 3.3 3.6 3.6 3.6 V Supply Voltage at EEPROM Programming Operating Temperature Internal regulator disabled Internal regulator enabled T=+25°C. Note 1. V -40 +25 +85 °C TA Note 1. The recommended condition for EEPROM programming is room temperature. ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 2.7 V, TA = -40°C to +85°C, typical values at TA = +27°C, unless otherwise specified. Parameter Internal regulator voltage Quiescent current Conversion current consumption Average current consumption Conversion time VDD rise time for proper power on reset (POR) Internal system clock oscillator frequency Sensor excitation frequency Symbol VREG IQ IDD_CONV IDD_AVE tCONV tVDD_RISE Conditions Regulator enabled All inputs at VDD, no load. Note 1. During conversion 1 conversion/s OSR=4096 OSR=2048 OSR=1024 OSR=512 OSR=256 OSR=4096 OSR=2048 OSR=1024 OSR=512 OSR=256 Note 2. OSCOUT MCLK No internal clock division Internal clock division Min Typ Max 1.8 Unit V 0.1 µA 390 µA 28 14.1 7.1 3.7 1.9 82.6 41.6 21.1 10.9 5.8 µA ms 400 ns 200 kHz 50 25 kHz Note 1. Setting XCS low activates the EEPROM memory regardless of the XSPI setting and the device consumes 20µA …30µA current. To minimize current consumption XCS should be set low only during time periods when the device is used during SPI communication. Note 2. Resetting the device using the XCLR pin is necessary in case the VDD rise time is longer than specified here. 3 (26) DA6512.000 11 July, 2012 ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 2.7 V, TA = -40°C to +85°C, typical values at TA = +27°C, unless otherwise specified. Parameter Internal offset capacitor matrix selection Changing capacitance range in capacitance difference mode Maximum allowed sensor capacitance in capacitance difference mode Changing capacitance range in capacitance ratio mode Maximum allowed sensor capacitance in capacitance ratio mode Integral nonlinearity Symbol CR_OS, CS_OS COS_STEP ∆CDIFF CS_MAX ∆CRATIO Min Typ Max Unit 22 pF 2 2 20 30 pF pF 2 20 40 Note 1. 20 20 >20 pF 0 0.086 No internal clock division Internal clock / 2 Internal clock Internal clock / 2 External clock Note 2. CS_MAX Note 2. INL RMS resolution RMS resolution Internal temperature sensor Conditions OSR=256, capacitance difference mode Difference mode CODEDIFF~(CS-CR) ∆C=20pF OSR=4096 Ratio mode CODERATIO~(CS-CR)/CS ∆C=20pF OSR=4096 Linearity Gain Offset OSR=4096 OSR=2048 OSR=1024 OSR=512 OSR=256 Non-calibrated, note 3. Non-calibrated, note 3. 0.012 % of ∆C 14 bit 14 ±0.35 bit °C ±0.5 267,8 267,6 267,3 33,3 4,1 -4.5 pF LSB/ °C +3.5 % ±11 °C Note 1. In capacitance difference mode the maximum allowed sensor and reference capacitor values can be extended using lower external oscillator frequency; CS_MAX=20pF*200kHz/f OSC_EXT. Note 2. In capacitance ratio mode also larger capacitances are possible depending on sensor characteristics. Please contact Micro Analog Systems to check sensor suitability. Note 3. By calibrating the temperature measurement and compensating offset and gain errors an overall accuracy close to the linearity accuracy can be achieved. 4 (26) DA6512.000 11 July, 2012 ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 2.7 V, TA = -40°C to +85°C, typical values at TA = +27°C, unless otherwise specified. Parameter Symbol Conditions Min Typ EEPROM size EEPROM data retention TA = +85 °C TA = +125 °C 10 Output data word length Linear output code range (10%...90% of full output code range) CODEDIFF CODERATIO Full output code range CODEDIFF CODERATIO Difference mode Cs_min=8pF, Cs_max=12pF, Cr=10pF, gain setting 6Dhex OSR=256 OSR=512 OSR=1024 OSR=2048 OSR=4096 Ratio mode Cs_min=8pF, Cs_max=12pF, Cr=7.68pF, gain setting 4Dhex OSR=256 OSR=512 OSR=1024 OSR=2048 OSR=4096 OSR=256 OSR=512 OSR=1024 OSR=2048 OSR=4096 OSR=256 OSR=512 OSR=1024 OSR=2048 OSR=4096 Max Unit 256 bit 24 1 16 years bit 89 71 5721 5727 5731 799 6422 51494 51552 51580 102 769 5944 5839 5786 0 0 0 0 0 0 0 0 0 0 790 6389 51362 51486 51547 892 7152 57280 57312 57328 888 7136 57216 57280 57312 Digital inputs Parameter Symbol Conditions Min Input High Voltage VIH VDD = 1.8…3.6V Input Low Voltage VIL VDD = 1.8…3.6V 80% VDD 0% VDD Serial Bus Clock Frequency Typ fSCL_SCLK Max Unit 100% VDD 20% VDD 400 V V kHz Digital outputs PARAMETER SYMBOL CONDITIONS MIN Output high voltage VOH ISource=0.6mA Output low voltage VOL ISink=0.6mA 80% VDD 0% VDD Signal rise time Signal fall time tr tf TYP 200 200 MAX UNIT 100% VDD 20% VDD V V ns ns 5 (26) DA6512.000 11 July, 2012 OPERATING MODES MAS6512 has two capacitance measurement modes and one temperature measurement mode. In capacitance measurement mode the output is proportional to either capacitance difference (CS-CR) or to capacitance ratio (CS-CR)/CS. In temperature measurement mode the output is proportional to the absolute temperature. Measurement mode configuration and start of conversion is done by writing 8-bit configuration data to the Measurement control register (address E2HEX). See further details in the Measurement control register chapter. MAS6512 includes a 256-bit EEPROM memory for storing trim and calibration data on chip. Four bytes (32 bits) of EEPROM are reserved for trim values but the remaining 28 bytes (224 bits) are free for calibration and other data. The stored trim data consists of measurement configuration settings that are automatically read from EEPROM memory in the beginning of each conversion. The calibration data should comprise of calibration and temperature compensation coefficients that can be used to calculate accurate calibrated sensor and temperature measurement results from the noncalibrated measurement reading. All calculations need to be done in an external micro controller unit (MCU). A calibrated MAS6512 sensor system should be operated as illustrated in figure 2. The calibration and compensation coefficients need to be read to the MCU memory only once. From each pair of sensor and temperature measurement readings the accurate sensor and temperature values can then be calculated by using an external MCU. All communication with MAS6512 is done using 2 either the I C bus or the SPI bus. Starting an A/D conversion, reading the conversion result and reading and writing data from and to the EEPROM memory are all accomplished via serial bus communication. In addition to the serial buses the digital interface includes also end-of-conversion (EOC) and master reset (XCLR) pins. See A/D Conversion in the Serial 2 Data Interface (I C Bus) Control chapter. START READ EEPROM CALIBRATION DATA MEASURE SENSOR MEASURE TEMPERATURE CALCULATE CALIBRATED TEMPERATURE CALCULATE TEMPERATURE COMPENSATED SENSOR VALUE Figure 2. Flow chart for a calibrated MAS6512 sensor system 6 (26) DA6512.000 11 July, 2012 REGISTER AND EEPROM DATA ADDRESSES Table 1. Register and EEPROM data addresses A7 A6 A5 A4 A3 A2 A1 A0 I2C BUS HEX SPI BUS HEX W=write R=read W: 40…41 R: C0…C1 W: 42 R: C2 W: 43 R: C3 W: 44 R: C4 W: 45 R: C5 W: 46 R: C6 W: 47 R: C7 W: 48…4F R: C8…CF W: 50…5F R: D0…DF W: 60 R: E0 W: 61 R: E1 W: 62 R: E2 W: 63 R: E3 W: 64 R: E4 W: 65 R: E5 W: 66 R: E6 W: 6A R: EA W: 6B R: EB W: 6D R: ED W: 6E R: EE A7 1 0 0 0 0 0 X C0…C1 A7 1 0 0 0 0 1 0 C2 A7 1 0 0 0 0 1 1 C3 A7 1 0 0 0 1 0 0 C4 A7 1 0 0 0 1 0 1 C5 A7 1 0 0 0 1 1 0 C6 A7 1 0 0 0 1 1 1 C7 A7 1 0 0 1 X X X C8…CF A7 1 0 1 X X X X D0…DF A7 1 1 0 0 0 0 0 E0 A7 1 1 0 0 0 0 1 E1 A7 1 1 0 0 0 1 0 E2 A7 1 1 0 0 0 1 1 E3 A7 1 1 0 0 1 0 0 E4 A7 1 1 0 0 1 0 1 E5 A7 1 1 0 0 1 1 0 E6 A7 1 1 0 1 0 1 0 EA A7 1 1 0 1 0 1 1 EB A7 1 1 0 1 1 0 1 ED A7 1 1 0 1 1 1 0 EE Description EEPROM; free for any data EEPROM; free for any data EEPROM; CS capacitor matrix trim data EEPROM; CR capacitor matrix trim data EEPROM; Gain trim data EEPROM; Oscillator frequency trim data EEPROM; free for any data EEPROM; free for any data EEPROM; free for any data Reset register; no data, only addressed for reset Test register Measurement control register CS capacitor matrix register CR capacitor matrix register Gain register Oscillator frequency control register 1st (MSB) byte of the conversion result 2nd (LSB) byte of the conversion result Status register for EEPROM Trimming control register Note E E E+T E+T E+T E+T E E E R R R R+T R+T R+T R+T R R R R X = Don’t care, E = EEPROM, R= Register, T = Trim data Note: When using the SPI serial interface the register address bit A7 is also used for selecting write (A7= 0) or read (A7=1) operation. For the I2C interface address bit A7 = 1. 7 (26) DA6512.000 11 July, 2012 REGISTER AND EEPROM DATA ADDRESSES MAS6512 includes a 32 bytes (256 bits) EEPROM data memory and eleven registers. Four bytes (32 bits) of EEPROM are reserved for trim values but the remaining 28 bytes (224 bits) are free for storing sensor calibration and other data. See table 1 on the previous page for register and EEPROM data addresses. In the SPI serial bus the address bit A7 selects between write (A7=0) and read (A7=1) operation. In 2 the I C serial bus A7 is always high (A7=1) and selection between write and read operation is done 2 with the LSB bit of the I C device address. See table 6 in chapter 2-WIRE SERIAL DATA INTERFACE 2 (I C® BUS). MAS6512 has four trim registers: CS capacitor matrix register (E3/63HEX), CR capacitor matrix register (E4/64HEX), Gain register (E5/65HEX) and Oscillator frequency register (E6/66HEX). These are marked with “R+T” in table 1. Each of these registers has a corresponding EEPROM byte where trim values can be permanently stored. These are marked with “E+T” in table 1. Trim values are automatically read from EEPROM in the beginning of each conversion when this feature is enabled in the trimming control register (EE/6EHEX). When disabled it is possible to test different trim data in the trim registers before final trimming values are found and stored in the EEPROM. Reset register (E0/60HEX) does not contain any data. Any dummy data written to this register forces a reset. A reset initializes all control registers (addresses E1HEX…EEHEX) to a zero value. Test register (E1/61HEX) is mainly used for testing and trimming purposes. See table 2 in chapter TEST REGISTER. If an external clock signal is used the test register is needed for selecting the external clock signal. The CS (E3/63HEX) and the CR (E4/64HEX) capacitor matrix registers contain a capacitor value between 0 and 22pF in 86fF steps. The Gain register (E5/65HEX) controls the gain of the CDC front-end. Together with the CS and CR values it determines the input capacitance conversion range. The Oscillator frequency control register (E6/66HEX) is used only during internal clock oscillator trimming. During trimming this register value is iterated to give the desired 200kHz oscillator frequency. When the best value is found it can be written to the internal clock oscillator frequency trimming EEPROM address (C6/46HEX). In normal operation the trim value is automatically read from the EEPROM memory in the beginning of each conversion. The clock frequency is trimmed by MAS during wafer level testing and there should be no need to modify it. The 16-bit A/D conversion result (capacitance or temperature) is stored into two registers EAHEX (MSB, most significant byte) and EBHEX (LSB, least significant byte). The EEPROM status register (ED/6DHEX) reflects the EEPROM error correction status. This register can be used to verify that the EEPROM operation has finished without errors. The Trimming control register (E9/69HEX) defines if the trim data in the EEPROM or in the registers are used during operation. The Trimming control register is also used for enabling EEPROM write. The default setting is that all trim data is automatically read from the EEPROM memory in the beginning of each conversion and that the EEPROM write is disabled. See the Trimming control register description for details. The Measurement control register (E2/62HEX) is used for configuring and starting an A/D conversion. 8 (26) DA6512.000 11 July, 2012 RESET REGISTER (E0/60HEX) This register is used to reset all control registers (addresses E1H…EEH) to a zero value. There are no data bits in this register. However it is necessary to write dummy data to this register to make a reset. The reset will take place immediately after any data 2 has been written to the address E1/61HEX via the I C or SPI interface. TEST REGISTER (E1/61HEX) In normal operation the Test register value is 00HEX and the internal clock oscillator is used for all the measurements. The SEL_EXTCLK bit enables the use of an external clock signal connected to the OSCOUT pin. This may come necessary if the sensor capacitance is too high to be used with the internal 200kHz clock signal. Sensor capacitances up to around 20pF can be measured with the internal 200kHz oscillator, or up to 40pF if the internal clock frequency is divided by two (see SOSCOUT below). By setting the SOSCOUT bit it is possible to divide the internal clock oscillator frequency by two, giving a 100kHz frequency. This lower clock frequency can be used for measuring up to about 40pF capacitances. For measuring larger than 40pF Table 2. MAS6512 test register (E1/61HEX) description Bit Bit Name Description Number 7-6 5 SEL_EXTCLK Not used Selects external clock 4-2 STEST[2:0] TEST1 and TEST2 signal selection ∆Σ-ADC inputs connected to TEST1 and TEST2 pins 1 SOSCOUT Select OSCOUT frequency 0 FOSC Forces the oscillator on without conversion sensor capacitances (CS) it is necessary to use an external clock frequency having a frequency of around fEXT=200kHz*20pF/Cs or less. Note that the frequency division selection SOSCOUT applies only to the internal clock signal. The STEST bits are used for connecting different internal signals to the TEST1 and TEST2 pins. In STEST[2:0]=101 test setup TEST1 and TEST2 operate as voltage inputs which are connected to the differential input of the ∆Σ-ADC. VTESTP is the positive input and VTESTN is the negative input of the ∆Σ-ADC. FOSC can be used to force the internal oscillator to be on all the time. Normally the internal oscillator is turned on only during the measurements to save power. Value Function 0 1 Normal mode An external clock can be connected to OSCOUT and the internal oscillator is disabled 000…100 Reserved for internal testing purpose (TEST1 and TEST2 are outputs) 101 VTESTP => TEST1 (input) VTESTN => TEST2 (input) 110…111 No function 0 1 0 OSCOUT = 200 kHz OSCOUT = 100 kHz OSC is on only during conversion OSC is forced on 1 X = Don’t care, SDM = Sigma delta modulator 9 (26) DA6512.000 11 July, 2012 MEASUREMENT CONTROL REGISTER (E2/62HEX) This register is used to configure and initiate a measurement. See table 3 below. A new conversion is started simply by writing 8-bit configuration data to the measurement control register (E2/62HEX). Table 3. Measurement control register (E2/62HEX) description Bit Number Bit Name Description Value 7-5 OSRS Over Sampling Ratio (OSR) Selection 4 REGEN Regulator Enable 3 SCO Start Conversion 2 XETS Sensor Selection 1 0 XRC Not used Front end function selector The OSRS over sampling ratio selection bits choose between five different OSR values. High OSR value corresponds to high resolution but also longer conversion time. See Electrical characteristics for further details. The REGEN bit enables/disables the internal voltage regulator. When enabled the regulator is turned on during conversions and automatically turned off after each conversion to save power. During temperature measurements the regulator is always enabled regardless of the REGEN bit setting. Note that if Test register FOSC=1 and if REGEN=1 the regulator is forced on all the time independently of measurements. 000 001 010 011 100 0 1 0 1 0 1 0 1 Function OSR = 256 OSR = 512 OSR = 1024 OSR = 2048 OSR = 4096 Voltage regulator disabled Voltage regulator enabled No conversion Start conversion External capacitive sensor Internal temperature sensor Ratio converter Difference converter The SCO Start conversion bit needs to be set 1 for every new measurement. It is automatically reset to 0 after each measurement. The XETS Sensor selection bit controls the frontend multiplexer and connects either the external capacitive sensor (XETS=0) or the internal temperature sensor (XETS=1) to the ∆Σ-converter. The XRC bit selects between two external capacitive sensor measurement modes. It does not have any effect on temperature measurement. In Ratio converter mode the measured value will be proportional to capacitance ratio (CS-CR)/CS. In Difference converter mode the measurement will be proportional to capacitance difference (CS-CR). 10 (26) DA6512.000 11 July, 2012 CS AND CR CAPACITOR MATRIX REGISTERS (E3/63HEX AND E4/64HEX) There are two internal capacitor matrices that add capacitance in parallel to the sensor capacitor (CS) and the reference capacitor (CR). These offset capacitances are used to adjust the sensor signal to an optimal range. Each capacitor matrix has a selectable capacitance from 0pF up to 22pF in typical 86fF steps. The three sigma process variation of the capacitor matrix capacitance is ±10%.The CS capacitor matrix register (E3/63HEX) has a corresponding EEPROM byte (C3/43HEX) for storing the trim value. Also the CR capacitor matrix register (E4/64HEX) has corresponding EEPROM byte (C4/44HEX) for storing the trim value. After finding suitable CS and CR capacitor matrix register values the trim values can be stored in the nonvolatile EEPROM. In normal operating mode these trim values are automatically read from the EEPROM during each conversion start. See also table 9 Trimming control Register (EE/6EHEX) for other operating modes. Table 4. CS capacitor matrix register (E3/63HEX), EEPROM (C3/43HEX) Bit Number Bit Name Description Value 7-0 OCDACS CDAC control bits 0HEX…FFHEX Table5. CR capacitor matrix register (E4/64HEX), EEPROM (C4/44HEX) Bit Number Bit Name Description Value 7-0 OCDACR CDAC control bits 0HEX…FFHEX Function CS offset trimming Function CR offset trimming GAIN REGISTER (E5/65HEX) The gain register sets the excitation signal level for the capacitive sensor. The eight bits (GRDAC) can be programmed to values between 0 and 255. Together with the CS and the CR capacitor matrix trim parameters it’s used to adjust the sensor signal to an optimal range. The goal is to get a maximum dynamic range and keep the signal within linear input range of the ∆Σ-modulator. This condition is met when the signal minimum and maximum covers the whole linear input range. The output of MAS6512 has the relationship to the ∆Σ-modulator output: following CODEOUT = QAVE ⋅ CODERANGE QAVE is the average measurement result (from the over sampling) of the ∆Σ-modulator and varies from 0 to 1. The CODERANGE is the maximum output code which depends on OSR and measurement mode selections. See page 5 Full output code range specification in the Electrical characteristics table. The linear signal range of the modulator is from QAVE=10% to QAVE =90%. In case of capacitance difference measurement mode; QAVE = In this mode the gain register value GRDAC sets the VS level. VS= (VDD/1.8V)*(33mV+GRDAC*2.88mV) VR = (VDD/1.8V)*144mV CS = External sensor + CS matrix capacitance CR = External reference + CR capacitance CREF = 6pF, three sigma variation ±10% In case of capacitance ratio measurement mode; C V QAVE = 1 − R ∗ R CS VS In this mode the gain register value GRDAC sets the VS level. VS = (VDD/1.8V)*GRDAC*0.52mV VR= (VDD/1.8V)*100.8mV CS = External sensor + CS matrix capacitance CR = External reference + CR capacitance The gain register (E5/65HEX) has a corresponding EEPROM byte (C5/45HEX). After finding a suitable gain register value it can be stored in the EEPROM memory. In normal operating mode the gain trim value is read automatically from the EEPROM during each conversion start. Table 6. Gain register (E5/65HEX), EEPROM (C5/45HEX) Bit Number Bit Name Description Value 7-0 GRDAC RDAC control bits 1 CS − C R V + ∗ S 2 CREF 2 ∗ VR 0HEX…FFHEX Function Gain control by sensor excitation signal level control 11 (26) DA6512.000 11 July, 2012 OSCILLATOR FREQUENCY CONTROL REGISTER (E6/66HEX) Note that the internal clock oscillator frequency has been factory trimmed and the trim value has been stored in the EEPROM (C6/46HEX). It is recommended not to change the factory programmed value! The oscillator frequency control register (E6/66HEX) is for trimming the internal clock oscillator to 200 kHz frequency. This 200kHz (or 100kHz if Table 7. Oscillator frequency control register (E6/66HEX) Bit Number Bit Name Description 5-0 OSCF Oscillator frequency control bits SOSCOUT=1) can be measured at the OSCOUT pin. The six LSB bits adjust the oscillator period in 104ns steps. The period increases when the trim value increases. Typically a register value of 28HEX corresponds to the nominal 200kHz clock oscillator frequency. After finding a suitable trim value it can be stored to the EEPROM (C6/46HEX). Value Function 0HEX…3FHEX Oscillator frequency control EEPROM STATUS REGISTER (ED/6DHEX) The EEPROM status register (ED/6DHEX) indicates if the stored EEPROM byte is corrupted. The register is updated after each EEPROM data byte read command. See table 8 below. The ERROR bit tells whether an data error has been detected or not. The DED bit tells whether two or more bit errors have been detected. The EEPROM can correct internally only single bit errors i.e. when ERROR=1 and DED=0. The read EEPROM data byte is corrupted if ERROR=DED=1. Table 8. MAS6512 EEPROM status register (ED/6DHEX). Only bits (7:6) are used. Bit Number Bit Name Description Value 7 ERROR 6 DED 5-0 EEPROM error detection EEPROM double error detection 0 1 0 1 0 Function No errors Error detected No errors 2 (or more) data errors - X = Don’t care 12 (26) DA6512.000 11 July, 2012 CONVERSION RESULT REGISTERS (EA…EBHEX) After measuring capacitance or temperature the 16bit conversion result is stored into two register addresses EAHEX and EBHEX. The MSB (most significant byte) is at EAHEX and LSB (least significant byte) at EBHEX. TRIMMING CONTROL REGISTER (EE/6EHEX) The Trimming control register (EE/6EHEX) is used to select between different trimming operating modes and enabling EEPROM write. See table 9 showing the functions of the Trimming control register. After a power-up reset, master reset via XCLR or a software reset the Trimming control register (EE/6EHEX) gets the value %00000000 (00HEX). This is the normal operating mode for a trimmed MAS6512 device. In this mode the capacitive frontend trim values to use (CS, CR and Gain) are automatically read from the EEPROM memory in the beginning of each conversion start. The EEPROM is normally write protected. To disable the write protection the Trimming control register should be set to %01010101 (55HEX). Table 9. Trimming control Register (EE/6EHEX) Bit Bit Name Description Number 7-0 REGEE<7:0> EEPROM control bits When calibrating a sensor there is an operating mode in which only the factory calibrated internal oscillator (OSC) clock trim data is read from the EEPROM memory. This mode is selected by writing %10101010 (AAHEX) to the Trimming control register. In this mode it is possible to run conversion tests for different front-end trim register values before suitable values are found and programmed to the EEPROM. There is also a trimming mode in which all trim data including the internal oscillator trim data is taken from the trim registers rather than from the EEPROM. This mode is selected by writing %11111111 (FFHEX) to the Trimming control register. Value Function 00000000 All trim data from EEPROM (normal operating mode) EEPROM write enabled Only OSC from EEPROM All trim data from registers All trim data from EEPROM 01010101 10101010 11111111 OTHER 13 (26) DA6512.000 11 July, 2012 EEPROM WRITE PROCEDURE START POWER UP DEVICE Connect supply voltage VDD INITIAL CONDITIONS Optional: Reset device by XCLR or by writing any data to the reset register 30HEX ENABLE EEPROM WRITEWrite 55HEX to the Trimming control register EE/6EHEX WRITE DATA TO EEPROM Write data byte (8-bit) to selected EEPROM memory address WAIT Wait minimum 16ms after writing byte (8-bit) to EEPROM VERIFY WRITTEN DATA Read the written data byte (8-bit) from the EEPROM memory address yes Write more data? no DISABLE EEPROM WRITE Write 00HEX to the Trimming control register EE/6EHEX STOP Figure 3. Flow chart for MAS6512 EEPROM write 14 (26) DA6512.000 11 July, 2012 EEPROM WRITE PROCEDURE This chapter gives instructions for writing data to the EEPROM memory. The MAS6512 16-bit Capacitance to Digital Converter (CDC) has a 256 bit (32 bytes) EEPROM memory. 8 bits (1 byte) has been reserved for storing internal clock oscillator trimming data. 24 other bits (3 bytes) are for trimming the capacitive sensor front-end. The remaining 232 bits (28 bytes) are free for other use. See figure 3 on previous page showing the EEPROM write procedure. Make sure in the beginning of the EEPROM write procedure that the MAS6512 initial conditions are met. Connecting VDD triggers power-on-reset (POR) but to make sure the device is reset an additional reset can be given using the XCLR pin or writing any data on the reset register E0/60HEX via the serial bus. EEPROM write is enabled by writing value 55HEX to the Trimming control Register (EE/6EHEX). The default register value after power on is 00HEX. Next the data can be written to the EEPROM memory one byte (8-bit) at a time. It is necessary to have a delay of minimum 16ms after programming each byte (8-bit). The success of each write can be verified by reading back the data (8-bit) and comparing it to the original byte (8-bit). Additionally it is also possible to check the EEPROM status register (ED/6DHEX) value after each read back. The EEPROM status register value should be 00HEX when the read EEPROM data byte is free of errors. After all data bytes are written the EEPROM memory can be protected from write by writing 00HEX to the Trimming control Register (EE/6EHEX). See table 1 showing the MAS6512 register and EEPROM data addresses. 15 (26) DA6512.000 11 July, 2012 2-WIRE SERIAL DATA INTERFACE (I C BUS) 2 Serial Interface MAS6512 has an I C bus compatible two wire serial data interface comprising of serial clock (SCL) and bi-directional serial data (SDA) pins. In 2 the I C bus both SCL & SDA lines are of opendrain design, thus, external pull-up resistors are needed. 2 The serial data interface is used to configure and start the A/D conversion and read the measurement result when the A/D conversion has finished. The digital interface includes also end of conversion (EOC) and master reset (XCLR) pins. The EOC goes high when the A/D conversion has finished. The XCLR is used to reset the A/D converter. A reset initializes internal registers, counters and the serial communication bus. After connecting the supply voltage to MAS6512, and before starting operating the device via the serial bus, it is required to reset the device with the XCLR reset pin if the supply voltage rise time has been longer than 400 ns (typ). If the supply voltage rise time is shorter than this making an external reset with the XCLR pin is not necessary since the device is automatically reset by the power on reset (POR) circuitry. It is however recommended to use the XCLR reset feature to solve unexpected error state conditions. Device Address The I C bus definition allows several I C bus devices to be connected to the same bus. The devices are distinguished from each other by unique device address codes. MAS6512 device address is 2 2 shown in table 10. The LSB bit of the device address defines whether the bus is configured for Read (1) or Write (0) operation. ECHEX= Write, EDHEX= Read. Table 10. MAS6512 device address (EC/EDHEX) A7 A6 A5 A4 A3 A2 A1 W/R 1 1 1 0 1 1 0 0/1 I C Bus Protocol Definitions 2 Data transfer is initiated with a Start bit (S) when SDA is pulled low while SCL stays high. Then, SDA sets the transferred bit while SCL is low and the data is sampled (received) when SCL rises. When the transfer is complete, a Stop bit (P) is sent by releasing the data line to allow it to be pulled up while SCL is constantly high. when SCL is high. Data at the SDA pin can change value only when SCL is low. Each SDA line byte transfer must contain 8-bits where the most significant bit (MSB) always comes first. Each byte has to be followed by an acknowledge bit (see further below). The number of bytes transmitted per transfer is unrestricted. Figure 4 shows the start (S) and stop (P) bits and a data bit. Data must be held stable at the SDA pin S SDA SCL 1 0 P Figure 4. I C bus protocol definitions 2 Bus communication includes Acknowledge (A) and not Acknowledge (N) messages. To send an acknowledge the receiver device pulls the SDA low for one SCL clock cycle. For not acknowledge (N) the receiver device leaves the SDA high for one SCL clock cycle in which case the master can then generate either a Stop (P) bit to abort the transfer, or a repeated Start (Sr) bit to start a new transfer. Abbreviations: A= Acknowledge by Receiver N = Not Acknowledge by Receiver S = Start Sr = Repeated Start P = Stop = from Master (MCU) to Slave (MAS6512) = from Slave (MAS6512) to Master (MCU) 16 (26) DA6512.000 11 July, 2012 2-WIRE SERIAL DATA INTERFACE (I C BUS) 2 Conversion Starting – Write Sequence Conversion is started by writing configuration bits into the Measurement control register (address E2HEX). The write sequence is illustrated in Table 11. Table 11. MAS6512 I2C bus write sequence bits S AW A MC A DC A P Abbreviations: AW = Device Write Address (%1110 1100) AR = Device Read Address (%1110 1101) MC = Measurement control register (%1110 0010) Ax = Conversion Result Registers; MSB (x=M, %1110 1010) or LSB (x=L, %1110 1011) Each serial bus operation, like write, starts with the start (S) bit (see figure 4). After start (S) the MAS6512 device address with write bit (AW, see table 10) is sent followed by an Acknowledge (A). After this the Measurement control register address (see table 1) is sent and followed by an DC = Measurement Control Register Data Dx = Conversion Result Register Data; MSB (x=M), ISB (x=I) or LSB (x=L) Acknowledge (A). Next the Measurement control register data (DC, see table 3) is written and followed by an Acknowledge (A). Finally the serial bus operation is ended with stop (P) command (see figure 4). A/D Conversion After power on reset or external reset (XCLR) the EOC output is high. After an A/D conversion is started the EOC output is set low until the conversion is finished and the EOC goes back high, indicating that the conversion is done and data is ready for reading. The EOC is set low only by starting a new conversion. To save power the internal oscillator runs only during conversion. During an A/D conversion the input signal is sampled continuously leading to an output conversion result that is a weighted average of the samples taken. Conversion Result – Read Sequence Table 12 presents a general control sequence for a single register data read. Table 12. MAS6512 I2C bus single register (address Ax) read sequence bits S AW A Ax A Sr AR A Dx N P Table 13 shows the control sequence for reading the 16-bit A/D conversion result from the Conversion result registers. The LSB (DL) register data read can follow right after the MSB register data (DM) read since if the read sequence is continued (not ended by a Stop bit P) the register address is automatically incremented to point to the next register. Table 13. MAS6512 I2C bus MSB (first) and LSB (second) A/D conversion result read sequence S AW A AM A Sr AR A DM A DL N P 17 (26) DA6512.000 11 July, 2012 4-WIRE SERIAL DATA INTERFACE (SPI BUS) SPI bus communication is selected by setting XSPI pin low. access bit A7 cleared (0) and in read access it is set (1). SPI communication differs from I2C bus in the following way. It requires four wires for bi-directional communication since each line operates in one direction only. Device selection is done by using separate chip select XCS control lines instead of using device address. Each SPI bus device has its own XCS control line and a device is selected by pulling its XCS line low (see figure 5 below). The fourth wire in the SPI bus is the serial clock line, SCLK. Data is transferred at rising edges of the serial clock during which the data line should be stable. Figure 5 illustrates write access communication. MAS6512 has an auto increment function which means that if there are more than one data byte transferred the additional data bytes are delivered to following register addresses. In write communication the MISO line is high impedance. In SPI bus communication it is good to note that setting XCS low activates the EEPROM memory regardless of the XSPI setting and the device consumes 20µA …30µA current. To minimize current consumption XCS should be set low only during time periods when the device is used during SPI communication. The selection between write or read access is done by register address MSB bit A7 (see table 1 “Register and EEPROM data addresses”). In write XCS SCLK SCK MOSI SDA MSB Register Address Byte MSB LSB Data Byte LSB High Z MISO Figure 5. SPI Protocol – Write Access (register address MSB bit A7=0) Figure 6 illustrates read access communication. The auto increment function can be utilized also in read access and if there are more than one data byte read the additional data bytes are delivered from following register addresses. XCS SCK SCLK SDA MOSI MISO MSB Register Address Byte High Z Ignored LSB MSB Data Byte LSB Figure 6. SPI Protocol – Read Access (register address MSB bit A7=1) 18 (26) DA6512.000 11 July, 2012 TRIMMING FOR SENSOR CAPACITANCE MAS6512 has two capacitance measurement modes and a temperature measurement mode. In capacitance measurement mode the output can be proportional either to capacitance difference (CS-CR) or to capacitance ratio (CS-CR)/CS. In temperature measurement mode the output is proportional to absolute temperature. trimming is based on selecting the minimum linear range capacitance same as CS MIN and maximum linear range capacitance same as CS MAX. At the linear range minimum and maximum limits the average of the ∆Σ-modulator output is 10% and 90% respectively. In the following trimming equations we denote these by For trimming it is necessary to know the sensor capacitance CS range CS MIN…CS MAX. For optimal utilization of the MAS6512AA1 input range the DMIN = 0.1 DMAX = 0.9 MAS6512 in capacitance difference mode The reference capacitor value CR is calculated from CR = [CS MIN*(DMAX-0.5)-CS MAX*(DMIN-0.5)] / (DMAX-DMIN) If an external CR is used, it is connected between pins CR and CC. If an internal CR is used, the trim code for CR is calculated from REGE4HEX = (CR/CR MAX)*255 where CR MAX is nominally 22pF, but subject to ±10 % (±3 sigma) process variation. The reference voltage, VS, can be calculated using the following equation: VS = [144mV*(DMAX-DMIN)*2*CREF] / (CS MAX-CS MIN) where CREF is nominally 6 pF, but also has ±10 % variation. The gain register trim value is calculated from REGE5HEX = [(VS-33 mV) / 734mV]*255 REGE4HEX and REGE5HEX are 8-bit values, so they range from 0 to 255. When their values are found, the same values can be written to corresponding EEPROM addresses C4HEX and C5HEX. However, with SPI bus, the address MSB in write operation is 0, so the addresses are actually 44HEX and 45HEX. Example: Single capacitance sensor CS MIN=8pF CS MAX=12pF CR = [8pF*(0.9-0.5)-12pF*(0.1-0.5)]/(0.9-0.1) = 10pF REGE4HEX = (10pF/22pF)*255 = 115.9 ~ 116 VS = [144mV*(0.9-0.1)*2*6pF] / (12pF-8pF) = 345.6mV REGE5HEX = [(345.6-33 mV) / 734mV]*255 = 108.6 ~109 REGE3HEX = 0 (no internal CS capacitor matrix used) 19 (26) DA6512.000 11 July, 2012 TRIMMING FOR SENSOR CAPACITANCE MAS6512 in capacitance ratio mode The reference capacitor CR is calculated from CR = [CS MIN*CS MAX*(DMAX-DMIN)] / (CS MAX*DMAX-CS MIN*DMIN) If an external CR is used, it is connected between pins CR and CC. If an internal CR is used, the trim code for CR is calculated from REGE4HEX = (CR/CR MAX)*255 where CR MAX is nominally 22pF, but subject to ±10 % (±3 sigma) process variation. The reference voltage, VS, can be calculated using the following equation: VS = 100.8mV * (CS MAX-CS MIN) / (CS MAX*DMAX-CS MIN*DMIN) The gain register trim value is calculated from REGE5HEX = (VS / 133.3mV)*255 REGE4HEX and REGE5HEX are 8-bit values, so they range from 0 to 255. When their values are found, the same values can be written to corresponding EEPROM addresses C4HEX and C5HEX. However, with SPI bus, the address MSB in write operation is 0, so the addresses are actually 44HEX and 45HEX. Example: Single capacitance sensor CS MIN=8pF CS MAX=12pF CR = [8pF*12pF*(0.9-0.1)] / (12pF*0.9-8pF*0.1) = 7.68pF REGE4HEX = (7.68pF/22pF)*255 = 89.0 ~ 89 VS = 100.8mV*)/(12pF-8pF)/(12pF*0.9-8pF*0.1)=40.32mV REGE5HEX = (40.32mV/133.3mV)*255 = 77.1 ~ 77 REGE3HEX = 0 (no internal CS capacitor matrix used) 20 (26) DA6512.000 11 July, 2012 APPLICATION INFORMATION VDD 100n VDD GND VDD OSCOUT MUX CS 4k7 MISO CLK OSC I2C / MCU SCL/SCLK Cs SPI CC XCS CONTROL VDD XSPI Cr optional 4k7 SDA/MOSI CR ∆Σ VREG TEMP EEPROM EOC optional XCLR optional VREG TEST1 TEST TEST2 GND GND GND NOTE: It is recommended to use the XCLR reset feature to solve unexpected error state conditions. The XCLR pin can be left unconnected if not used. It has internal pull up to VDD. 2 Figure 7. MAS6512 configured for I C bus communication Note: MAS6512 has an effective ESD clamp protection structure that can be triggered if the VDD rises too fast. For this reason it’s recommended to use a supply decoupling capacitor having a value of 100nF or higher to slow down the VDD rise time. Accuracy Improvement – Averaging An averaging technique can be used to remove conversion errors caused by noise and thus improve measurement accuracy. By doing several A/D conversions and calculating the average result it’s possible to average out noise. Theoretically the noise is reduced by a factor N where N is the number of averaged samples. A/D converter nonlinearities cannot be removed by averaging. 21 (26) DA6512.000 11 July, 2012 9 CR 10 CC 11 CS 12 GND MAS6512 IN QFN-16 4x4x0.75 PACKAGE TEST1 15 XCS 1 EOC 16 8 VREG 7 XCLR 6 SCL_SCLK 5 SDA_MOSI VDD 4 TEST2 14 MISO 3 OSCOUT 13 XSPI 2 MAS6512 AA1 YYWW XXXXX Top Marking Information: MAS6512 = Product Number, AA1 = Version Number YYWW = Year Week XXXXX = Lot Number QFN-16 4x4x0.75 PIN DESCRIPTION Pin Name Pin Type XCS XSPI 1 2 DI DI MISO VDD SDA_MOSI 3 4 5 DO P DI/O SCL_SCLK XCLR VREG CR CC CS GND OSCOUT TEST2 TEST1 EOC 6 7 8 9 10 11 12 13 14 15 16 DI DI AO AI AI AI G DI/DO AI/O DO DO Function Chip Select (SPI) SPI / I2C Bus Selection SPI: XSPI=low I2C: XSPI=high Master Input Slave Output (SPI) Power Supply Voltage Serial Bus Data (I2C) Master Output Salve Input (SPI) Serial Bus Clock (I2C / SPI) Master Reset Voltage Regulator Output 1.8V Reference Capacitance Pin Common Capacitance Pin Sensing Capacitance Pin Power Supply Ground Oscillator Output Test pin 2 Test pin 1 End of Conversion P = Power, G = Ground, DO = Digital Output, , DI = Digital Input, AO = Analog Output, AI = Analog Input 22 (26) DA6512.000 11 July, 2012 PACKAGE (QFN-16 4X4x0.75) OUTLINE D D/2 E/2 TOP VIEW A3 A PIN 1 MARK AREA SIDE VIEW DETAIL A A1 SEATING PLANE Package Center Line X or Y D2 b D2/2 L e BOTTOM VIEW EXPOSED PAD DETAIL A Symbol Terminal Tip e/2 E2 E2/2 SHAPE OF PIN #1 IDENTIFICATION IS OPTIONAL Min Nom Max PACKAGE DIMENSIONS A 0.700 0.750 0.800 A1 0.000 0.020 0.050 A3 0.203 REF b 0.250 --0.350 D 3.950 4.000 4.050 D2 (Exposed.pad) 2.700 --2.900 E 3.950 4.000 4.050 E2 (Exposed.pad) 2.700 --2.900 e 0.650 BSC L 0.350 --0.450 Dimensions do not include mold or interlead flash, protrusions or gate burrs. Unit mm mm mm mm mm mm mm mm mm mm 23 (26) DA6512.000 11 July, 2012 SOLDERING INFORMATION ◆ For Lead-Free / Green QFN 4mm x 4mm Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile According to RSH test IEC 68-2-58/20 260°C 3 Thermal profile parameters stated in IPC/JEDEC J-STD-020 should not be exceeded. http://www.jedec.org Solder plate 7.62 - 25.4 µm, material Matte Tin Lead Finish EMBOSSED TAPE SPECIFICATIONS P2 PO P1 D0 T X E F W B0 R 0.25 typ K0 X A0 User Direction of Feed Orientation on tape Dimension Ao Bo Do E F Ko Po P1 P2 T W Min/Max 4.30 ±0.10 4.30 ±0.10 1.50 +0.1/-0.0 1.75 5.50 ±0.05 1.10 ±0.10 4.0 8.0 ±0.10 2.0 ±0.05 0.3 ±0.05 12.00 ±0.3 All dimensions in millimeters Unit mm mm mm mm mm mm mm mm mm mm mm 24 (26) DA6512.000 11 July, 2012 REEL SPECIFICATIONS W2 A D C Tape Slot for Tape Start N B W1 Carrier Tape Cover Tape End Start Trailer Dimension A B C D N W 1 (measured at hub) W 2 (measured at hub) Trailer Leader Components Min Leader Max 330 1.5 12.80 20.2 100 12.4 13.50 14.4 18.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape Unit mm mm mm mm mm mm mm mm mm Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative 25 (26) DA6512.000 11 July, 2012 ORDERING INFORMATION Product Code Product Description MAS6512AA1WAD00 Capacitive Sensor Signal Interface IC Capacitive Sensor Signal Interface IC Capacitive Sensor Signal Interface IC EWS-tested wafer, thickness 370 µm MAS6512AA1WAD05 MAS6512AA1Q1706 Dies on waffle pack, thickness 370 µm QFN-16 4x4x0.75 Package, Pb-free, RoHS compliant, Tape & Reel, 1000 / 3000 pcs components on reel Contact Micro Analog Systems Oy for other wafer thickness options. LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kutomotie 16 FI-00380 Helsinki, FINLAND Tel. +358 10 835 1100 Fax +358 10 835 1119 http://www.mas-oy.com NOTICE Micro Analog Systems Oy (MAS) reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. MAS assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and MAS makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. MAS products are not authorized for use in safety-critical applications (such as life support) where a failure of the MAS product would reasonably be expected to cause severe personal injury or death. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safetyrelated requirements concerning their products and any use of MAS products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by MAS. Further, Buyers must fully indemnify MAS and its representatives against any damages arising out of the use of MAS products in such safety-critical applications. MAS products are neither designed nor intended for use in military/aerospace applications or environments. Buyers acknowledge and agree that any such use of MAS products which MAS has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. MAS products are neither designed nor intended for use in automotive applications or environments. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, MAS will not be responsible for any failure to meet such requirements. 26 (26)