MICROCHIP SST25PF020B-80-4C-QAE-T

SST25PF020B
2 Mbit 2.3-3.6V SPI Serial Flash
Features
Product Description
• Single Voltage Read and Write Operations
- 2.3-3.6V
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
- 80 MHz (2.7-3.6V operation)
- 50 MHz (2.3-2.7V operation)
• Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read Current: 10 mA (typical)
- Standby Current: 5 µA (typical)
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 32 KByte overlay blocks
- Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
- Chip-Erase Time: 35 ms (typical)
- Sector-/Block-Erase Time: 18 ms (typical)
- Byte-Program Time: 7 µs (typical)
• Auto Address Increment (AAI) Programming
- Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
- Software polling the BUSY bit in Status Register
- Busy Status readout on SO pin in AAI Mode
• Hold Pin (HOLD#)
- Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of
the status register
• Software Write Protection
- Write protection through Block-Protection bits
in status register
• Temperature Range
- Commercial: 0°C to +70°C
• Packages Available
- 8-lead SOIC (150 mils)
- 8-contact WSON (6mm x 5mm)
- 8-contact USON (3mm x 2mm)
• All non-Pb (lead-free) devices are RoHS compliant
The 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ultimately lowers total system costs. The SST25PF020B
devices are enhanced with improved operating frequency and even lower power consumption.
SST25PF020B SPI serial flash memories are manufactured with proprietary, high-performance CMOS
SuperFlash technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
 2012 Microchip Technology Inc.
The SST25PF020B devices significantly improve performance and reliability, while lowering power consumption. The devices write (Program or Erase) with a
single power supply of 2.3-3.6V for SST25PF020B.
The total energy consumed is a function of the applied
voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program operation is less than alternative flash memory
technologies.
The SST25PF020B device is offered in 8-lead SOIC
(150 mils), 8-contact WSON (6mm x 5mm), and 8-contact USON (3mm x 2mm) packages. See Figure 2-1 for
pin assignments.
DS25135A-page 1
SST25PF020B
1.0
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
and
Data Latches
Control Logic
Serial Interface
CE#
FIGURE 1-1:
DS25135A-page 2
SCK
SI
SO
WP#
HOLD#
25135 B1.0
FUNCTIONAL BLOCK DIAGRAM
 2012 Microchip Technology Inc.
SST25PF020B
2.0
PIN DESCRIPTION
CE#
1
SO
2
8
VDD
7
HOLD#
CE#
1
SO
2
8
VDD
7
HOLD#
Top View
Top View
WP#
3
6
SCK
WP#
3
6
SCK
VSS
4
5
SI
VSS
4
5
SI
8-Contact WSON
8-Lead SOIC
25135 08-wson QA P2.0
25135 08-soic S2A P1.0
CE#
1
SO
2
Top View
8
VDD
7
HOLD#
WP#
3
6
SCK
VSS
4
5
SI
8-Contact USON
25135 08-uson Q3A P1.0
FIGURE 2-1:
TABLE 2-1:
PIN ASSIGNMENTS
PIN DESCRIPTION
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#
pin. See “Hardware End-of-Write Detection” on page 11 for details.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for
the duration of any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
Hold
To temporarily stop serial communication with SPI flash memory without resetting
the device.
VDD
Power Supply
To provide power supply voltage: 2.3-3.6V for SST25PF020B
VSS
Ground
 2012 Microchip Technology Inc.
DS25135A-page 3
SST25PF020B
3.0
MEMORY ORGANIZATION
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
The SST25PF020B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable
blocks.
4.0
The SST25PF020B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
Standby mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
DEVICE OPERATION
The SST25PF020B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
CE#
SCK
MODE 3
MODE 3
MODE 0
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SI
MSB
HIGH IMPEDANCE
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
FIGURE 4-1:
4.1
25135 SPIprot.0
SPI PROTOCOL
Hold Operation
The HOLD# pin is used to pause a serial sequence
underway with the SPI flash memory without resetting
the clocking sequence. To activate the HOLD# mode,
CE# must be in active low state. The HOLD# mode
begins when the SCK active low state coincides with
the falling edge of the HOLD# signal. The HOLD mode
ends when the HOLD# signal’s rising edge coincides
with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active
low state, then the device exits in Hold mode when the
SCK next reaches the active low state. See Figure 4-2
for Hold Condition waveform.
Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH.
If CE# is driven high during a Hold condition, the device
returns to Standby mode. As long as HOLD# signal is
low, the memory remains in the Hold condition. To
resume communication with the device, HOLD# must
be driven active high, and CE# must be driven active
low. See Figure 4-2 for Hold timing.
SCK
HOLD#
Active
Hold
Active
Hold
Active
25135 HoldCond.0
FIGURE 4-2:
DS25135A-page 4
HOLD CONDITION WAVEFORM
 2012 Microchip Technology Inc.
SST25PF020B
4.2
Write Protection
SST25PF020B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register, and
the Top/Bottom Sector Protection Status bits (TSP and
BSP) in Status Register 1, provide Write protection to
the memory array and the status register. See Table 44 for the Block-Protection description.
TABLE 4-1:
4.3
4.2.1
WRITE PROTECT PIN (WP#)
The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the WriteStatus-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION
WP#
BPL
Execute WRSR Instruction
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
Status Register
The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
TABLE 4-2:
During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4-2 describes
the function of each bit in the software status register.
SOFTWARE STATUS REGISTER
Default at
Power-up
Read/Write
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
R
2
BP0
Indicates current level of block write protection (See Table 4-4)
1
R/W
3
BP1
Indicates current level of block write protection (See Table 4-4)
1
R/W
4:5
RES
Reserved for future use
0
N/A
6
AAI
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0
R
7
BPL
1 = BP1, BP0 are read-only bits
0 = BP1, BP0 are read/writable
0
R/W
Bit
Name
Function
0
BUSY
1
 2012 Microchip Technology Inc.
DS25135A-page 5
SST25PF020B
4.4
Software Status Register 1
The Software Status Register 1 is an additional register that
contains Top Sector and Bottom Sector Protection bits.
These register bits are read/writable and determine the lock
TABLE 4-3:
Bit
0:1
2
BSP
4:7
RES
4.4.1
SOFTWARE STATUS REGISTER 1
Name
RES
TSP
3
Function
Reserved for future use
Top Sector Protection status
1 = Indicates highest sector is write locked
0 = Indicates highest sector is Write accessible
Bottom Sector Protection status
1 = Indicates lowest sector is write locked
0 = Indicates lowest sector is Write accessible
Reserved for future use
BUSY
The Busy bit determines whether there is an internal
Erase or Program operation in progress. A “1” for the
Busy bit indicates the device is busy with an operation
in progress. A “0” indicates the device is ready for the
next valid operation.
4.4.2
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
TABLE 4-4:
•
•
•
•
Default at
Power-up
0
0
Read/Write
N/A
R/W
0
R/W
0
N/A
memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Write-Status-Register instruction completion
4.4.3
WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the
internal memory Write Enable Latch. If the WriteEnable-Latch bit is set to “1”, it indicates the device is
Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept
any memory Write (Program/Erase) commands. The
Write-Enable-Latch bit is automatically reset under the
following conditions:
•
•
•
•
and unlock status of the top and bottom sectors. Table 4-3
describes the function of each bit in the Software Status
Register 1.
AUTO ADDRESS INCREMENT (AAI)
The Auto Address Increment Programming-Status bit
provides status on whether the device is in AAI programming mode or Byte-Program mode. The default at
power up is Byte-Program mode.
4.4.4
BLOCK PROTECTION (BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of
the memory area, as defined in Table 4-4, to be software
protected against any memory Write (Program or Erase)
operation. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as
WP# is high or the Block-Protect-Lock (BPL) bit is 0.
Chip-Erase can only be executed if Block-Protection bits
are all 0. After power-up, BP1 and BP0 are set to 1.
SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25PF020B1
Status Register Bit2
Protection Level
BP1
BP0
Protected Memory Address
2 Mbit
0
0
0
None
1 (1/4 Memory Array)
0
1
030000H-03FFFFH
1 (1/2 Memory Array)
1
0
020000H-03FFFFH
1 (Full Memory Array)
1
1
000000H-03FFFFH
1. X = Don’t Care (RESERVED) default is ‘0’
2. Default at power-up for BP1 and BP0 is ‘11’. (All Blocks Protected)
DS25135A-page 6
 2012 Microchip Technology Inc.
SST25PF020B
4.4.5
BLOCK PROTECTION LOCK-DOWN
(BPL)
WP# pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents
any further alteration of the BPL, BP1, and BP0 bits of
the status register and BSP and TSP of Status Register
1. When the WP# pin is driven high (VIH), the BPL bit
has no effect and its value is “Don’t Care”. After powerup, the BPL bit is reset to 0.
4.4.6
TOP-SECTOR PROTECTION/
BOTTOM-SECTOR PROTECTION
The Top-Sector Protection (TSP) and Bottom-Sector
Protection (BSP) bits independently indicate whether
the highest and lowest sector locations are Write
locked or Write accessible. When TSP or BSP is set to
‘1’, the respective sector is Write locked; when set to ‘0’
the respective sector is Write accessible. If TSP or BSP
is set to '1' and if the top or bottom sector is within the
boundary of the target address range of the program or
erase instruction, the initiated instruction (Byte-Program, AAI-Word Program, Sector-Erase, Block-Erase,
and Chip-Erase) will not be executed. Upon power-up,
the TSP and BSP bits are automatically reset to ‘0’.
 2012 Microchip Technology Inc.
DS25135A-page 7
SST25PF020B
4.5
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25PF020B. The instruction bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The complete list of instructions is provided in Table 4-5. All
instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of
TABLE 4-5:
SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-StatusRegister instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction commands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.
DEVICE OPERATION INSTRUCTIONS
Instruction
Description
Op Code Cycle1
Address
Cycle(s)2
Dummy
Cycle(s)
Data
Cycle(s)
Read
Read Memory
0000 0011b (03H)
3
0
1 to ∞
High-Speed Read
Read Memory at higher speed
0000 1011b (0BH)
3
1
1 to ∞
4 KByte SectorErase3
Erase 4 KByte of memory array
0010 0000b (20H)
3
0
0
32 KByte BlockErase4
Erase 32 KByte block of memory
array
0101 0010b (52H)
3
0
0
64 KByte BlockErase5
Erase 64 KByte block of memory
array
1101 1000b (D8H)
3
0
0
Chip-Erase
Erase Full Memory Array
0110 0000b (60H) or
1100 0111b (C7H)
0
0
0
Byte-Program
To Program One Data Byte
0000 0010b (02H)
3
0
1
AAI-Word-Program6
Auto Address Increment Programming
1010 1101b (ADH)
3
0
2 to ∞
RDSR7
Read-Status-Register
0000 0101b (05H)
0
0
1 to ∞
RDSR1
Read-Status-Register 1
0011 0101b (35H)
0
0
1 to ∞
EWSR
Enable-Write-Status-Register
0101b 0000b (50H)
0
0
0
WRSR
Write-Status-Register
0000 0001b (01H)
0
0
1 or 2
WREN
Write-Enable
0000 0110b (06H)
0
0
0
WRDI
Write-Disable
0000 0100b (04H)
0
0
0
RDID8
Read-ID
1001 0000b (90H) or
1010 1011b (ABH)
3
0
1 to ∞
JEDEC-ID
JEDEC ID Read
1001 1111b (9FH)
0
0
3 to ∞
EBSY
Enable SO to output RY/BY# status
during AAI programming
0111 0000b (70H)
0
0
0
DBSY
Disable SO to output RY/BY# status
during AAI programming
1000 0000b (80H)
0
0
0
1.
2.
3.
4.
5.
6.
One bus cycle is eight clock periods.
Address bits above the most significant bit of each density can be VIL or VIH.
4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0=1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID
and Device ID output stream is continuous until terminated by a low-to-high transition on CE#.
DS25135A-page 8
 2012 Microchip Technology Inc.
SST25PF020B
4.5.1
READ (33/25 MHZ)
The Read instruction, 03H, supports up to 33 MHz (2.73.6V operation) or 25 MHz (2.3-2.7V operation) Read.
The device outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-
ment to the beginning (wrap-around) of the address
space. Once the data from address location 3FFFFH
has been read, the next output will be from address
location 000000H.
The Read instruction is initiated by executing an 8-bit
command, 03H, followed by address bits [A23-A0]. CE#
must remain active low for the duration of the Read
cycle. See Figure 4-3 for the Read sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47
48
55 56
63 64
70
MODE 0
ADD.
ADD.
03
SI
ADD.
MSB
MSB
N
DOUT
HIGH IMPEDANCE
SO
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
25135 ReadSeq.0
FIGURE 4-3:
4.5.2
READ SEQUENCE
HIGH-SPEED-READ (80/50 MHZ)
through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address
space. Once the data from address location 3FFFH
has been read, the next output will be from address
location 00000H.
The High-Speed-Read instruction, supporting up to 80
MHz (2.7-3.6V operation) or 50 MHz (2.3-2.7V operation) Read, is initiated by executing an 8-bit command,
0BH, followed by address bits [A23-A0] and a dummy
byte. CE# must remain active low for the duration of the
High-Speed-Read cycle. See Figure 4-4 for the HighSpeed-Read sequence.
Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
MODE 0
0B
SI
MSB
ADD.
MSB
ADD.
ADD.
HIGH IMPEDANCE
SO
X
N
DOUT
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)
FIGURE 4-4:
25135 HSRdSeq.0
HIGH-SPEED-READ SEQUENCE
 2012 Microchip Technology Inc.
DS25135A-page 9
SST25PF020B
4.5.3
BYTE-PROGRAM
The Byte-Program instruction is initiated by executing
an 8-bit command, 02H, followed by address bits [A23A0]. Following the address, the data is input in order
from MSB (bit 7) to LSB (bit 0). CE# must be driven
high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait
TBP for the completion of the internal self-timed ByteProgram operation. See Figure 4-5 for the Byte-Program sequence.
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte
must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a
protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active
low for the duration of the Byte-Program instruction.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
ADD.
02
SI
ADD.
MSB
MSB
SO
15 16
23 24
31 32
39
MODE 0
ADD.
DIN
MSB
LSB
HIGH IMPEDANCE
25135 ByteProg.0
FIGURE 4-5:
4.5.4
BYTE-PROGRAM SEQUENCE
AUTO ADDRESS INCREMENT (AAI)
WORD-PROGRAM
The AAI program instruction allows multiple bytes of
data to be programmed without re-issuing the next
sequential address location. This feature decreases
total programming time when multiple bytes or entire
memory array is to be programmed. An AAI Word program instruction pointing to a protected memory area
will be ignored. The selected address range must be in
the erased state (FFH) when initiating an AAI Word
Program operation. While within AAI Word Programming sequence, only the following instructions are
valid: for software end-of-write detection—AAI Word
(ADH), WRDI (04H), and RDSR (05H); for hardware
end-of-write detection—AAI Word (ADH) and WRDI
(04H). There are three options to determine the completion of each AAI Word program cycle: hardware
detection by reading the Serial Output, software detection by polling the BUSY bit in the software status register, or wait TBP. Refer to“End-of-Write Detection” for
details.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. Initiate the AAI Word
Program instruction by executing an 8-bit command,
ADH, followed by address bits [A23-A0]. Following the
addresses, two bytes of data are input sequentially,
each one from MSB (Bit 7) to LSB (Bit 0). The first byte
of data (D0) is programmed into the initial address [A23A1] with A0=0, the second byte of Data (D1) is programmed into the initial address [A23-A1] with A0=1.
CE# must be driven high before executing the AAI
DS25135A-page 10
Word Program instruction. Check the BUSY status
before entering the next valid command. Once the
device indicates it is no longer busy, data for the next
two sequential addresses may be programmed, followed by the next two, and so on.
When programming the last desired word, or the highest unprotected memory address, check the busy status using either the hardware or software (RDSR
instruction) method to check for program completion.
Once programming is complete, use the applicable
method to terminate AAI. If the device is in Software
End-of-Write Detection mode, execute the Write-Disable (WRDI) instruction, 04H. If the device is in AAI
Hardware End-of-Write Detection mode, execute the
Write-Disable (WRDI) instruction, 04H, followed by the
8-bit DBSY command, 80H. There is no wrap mode
during AAI programming once the highest unprotected
memory address is reached. See Figures 4-8 and 4-9
for the AAI Word programming sequence.
4.5.5
END-OF-WRITE DETECTION
There are three methods to determine completion of a
program cycle during AAI Word programming: hardware detection by reading the Serial Output, software
detection by polling the BUSY bit in the Software Status
Register, or wait TBP. The Hardware End-of-Write
detection method is described in the section below.
 2012 Microchip Technology Inc.
SST25PF020B
4.5.6
HARDWARE END-OF-WRITE DETECTION
The Hardware End-of-Write detection method eliminates the overhead of polling the Busy bit in the Software Status Register during an AAI Word program
operation. The 8-bit command, 70H, configures the
Serial Output (SO) pin to indicate Flash Busy status
during AAI Word programming. (see Figure 4-6) The 8bit command, 70H, must be executed prior to initiating
an AAI Word-Program instruction. Once an internal
programming operation begins, asserting CE# will
immediately drive the status of the internal flash status
on the SO pin. A ‘0’ indicates the device is busy and a
‘1’ indicates the device is ready for the next instruction.
De-asserting CE# will return the SO pin to tri-state.
While in AAI and Hardware End-of-Write detection
mode, the only valid instructions are AAI Word (ADH)
and WRDI (04H).
To exit AAI Hardware End-of-Write detection, first execute WRDI instruction, 04H, to reset the Write-EnableLatch bit (WEL=0) and AAI bit. Then execute the 8-bit
DBSY command, 80H, to disable RY/BY# status during
the AAI command. See Figures 4-7 and 4-8.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
70
SI
MSB
HIGH IMPEDANCE
SO
25135 EnableSO.0
FIGURE 4-6:
ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
80
SI
MSB
SO
HIGH IMPEDANCE
25135 DisableSO.0
FIGURE 4-7:
DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
 2012 Microchip Technology Inc.
DS25135A-page 11
SST25PF020B
CE#
MODE 3
0
0
7
0
7
7 8
15 16 23 24
31 32
39 40 47
0
7 8
15 16 23
SCK MODE 0
SI
AD
WREN
EBSY
A
A
A
D0
D1
AD
D2
D3
Load AAI command, Address, 2 bytes data
SO
Check for Flash Busy Status to load next valid1 command
CE# cont.
0
7 8
15 16 23
0
7
0
7
0
7 8
15
SCK cont.
SI cont.
Dn-1
AD
WRDI
Dn
Last 2
Data Bytes
DBSY
RDSR
WRDI followed by DBSY
to exit AAI Mode
DOUT
SO cont.
1
Check for Flash Busy Status to load next valid command
Note:
1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
25135 AAI.HW.3
FIGURE 4-8:
AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
HARDWARE END-OF-WRITE DETECTION
Wait TBP or poll Software Status
register to load next valid1 command
CE#
MODE 3
0
7 8
15 16 23 24
31 32 39 40 47
0
7 8
15 16 23
0
7 8
15 16 23
0
7
0
7 8
15
SCK MODE 0
SI
AD
A
A
A
D0
D1
Load AAI command, Address, 2 bytes data
AD
D2
D3
AD
Dn-1
Dn
Last 2
Data Bytes
SO
Note:
WRDI
RDSR
WRDI to exit
AAI Mode
DOUT
1. Valid commands during AAI programming: AAI command, RDSR command, or WRDI command
FIGURE 4-9:
DS25135A-page 12
25135 AAI.SW.2
AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
SOFTWARE END-OF-WRITE DETECTION
 2012 Microchip Technology Inc.
SST25PF020B
4.5.7
4-KBYTE SECTOR-ERASE
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H, followed by address
bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to determine the sector
address (SAX), remaining address bits can be VIL or VIH.
CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software
status register or wait TSE for the completion of the
internal self-timed Sector-Erase cycle. See Figure 4-10
for the Sector-Erase sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31
MODE 0
ADD.
ADD.
20
SI
MSB
ADD.
MSB
HIGH IMPEDANCE
SO
25135 SecErase.0
FIGURE 4-10:
4.5.8
SECTOR-ERASE SEQUENCE
32-KBYTE AND 64-KBYTE BLOCKERASE
nificant Address) are used to determine block address
(BAX), remaining address bits can be VIL or VIH. CE#
must be driven high before the instruction is executed. The
64-KByte Block-Erase instruction is initiated by executing an
8-bit command D8H, followed by address bits [A23-A0].
Address bits [AMS-A16] are used to determine block address
(BAX), remaining address bits can be VIL or VIH. CE# must
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
TBE for the completion of the internal self-timed 32KByte Block-Erase or 64-KByte Block-Erase cycles.
See Figures 4-11 and 4-12 for the 32-KByte BlockErase and 64-KByte Block-Erase sequences.
The 32-KByte Block-Erase instruction clears all bits in
the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. The 64-KByte Block-Erase instruction clears all bits
in the selected 64 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must remain
active low for the duration of any command sequence.
The 32-KByte Block-Erase instruction is initiated by
executing an 8-bit command, 52H, followed by address
bits [A23-A0]. Address bits [AMS-A15] (AMS = Most Sig-
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
52
SI
MSB
SO
15 16
23 24
31
MODE 0
ADDR
ADDR
ADDR
MSB
HIGH IMPEDANCE
25135 32KBklEr.0
FIGURE 4-11:
32-KBYTE BLOCK-ERASE SEQUENCE
 2012 Microchip Technology Inc.
DS25135A-page 13
SST25PF020B
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
ADDR
ADDR
D8
SI
MSB
ADDR
MSB
HIGH IMPEDANCE
SO
25135 63KBlkEr.0
FIGURE 4-12:
4.5.9
64-KBYTE BLOCK-ERASE SEQUENCE
CHIP-ERASE
The Chip-Erase instruction clears all bits in the device
to FFH. A Chip-Erase instruction will be ignored if any
of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of
the Chip-Erase instruction sequence. The Chip-Erase
instruction is initiated by executing an 8-bit command,
60H or C7H. CE# must be driven high before the instruction
is executed. The user may poll the Busy bit in the software
status register or wait TCE for the completion of the
internal self-timed Chip-Erase cycle. See Figure 4-13
for the Chip-Erase sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
60 or C7
SI
MSB
SO
HIGH IMPEDANCE
25135 ChEr.0
FIGURE 4-13:
4.5.10
CHIP-ERASE SEQUENCE
READ-STATUS-REGISTER (RDSR)
The Read-Status-Register (RDSR) instruction allows
reading of the status register. The Status Register may
be read at any time even during a Write (Program/
Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any
new commands to assure that the new commands are
properly received by the device. CE# must be driven
low before the RDSR instruction is entered and remain
low until the status data is read. Read-Status-Register
is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure
4-14 for the RDSR instruction sequence.
DS25135A-page 14
 2012 Microchip Technology Inc.
SST25PF020B
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
05
SI
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
Status
Register Out
25135 RDSRseq.0
FIGURE 4-14:
4.5.11
READ-STATUS-REGISTER (RDSR) SEQUENCE
READ-STATUS-REGISTER (RDSR1)
remain low until the status data is read. Read-StatusRegister 1 is continuous with ongoing clock cycles until
it is terminated by a low to high transition of the CE#.
See Figure 4-15 for the RDSR instruction sequence.
The Read-Status-Register 1 (RDSR1) instruction
allows reading of the status register 1. CE# must be
driven low before the RDSR instruction is entered and
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
SI
35
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
Status
Register Out
25135 RDSR1seq.0
FIGURE 4-15:
4.5.12
READ-STATUS-REGISTER 1 (RDSR1) SEQUENCE
WRITE-ENABLE (WREN)
execution of the Write-Status-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status
Register will be cleared upon the rising edge CE# of the
WRSR instruction. CE# must be driven high before the
WREN instruction is executed.
The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit in the Status Register to 1 allowing
Write operations to occur. The WREN instruction must
be executed prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
06
SI
MSB
SO
HIGH IMPEDANCE
25135 WREN.0
FIGURE 4-16:
WRITE ENABLE (WREN) SEQUENCE
 2012 Microchip Technology Inc.
DS25135A-page 15
SST25PF020B
4.5.13
WRITE-DISABLE (WRDI)
ress. Any program operation in progress may continue
up to TBP after executing the WRDI instruction. CE#
must be driven high before the WRDI instruction is executed.
The Write-Disable (WRDI) instruction resets the WriteEnable-Latch bit and AAI bit to 0 disabling any new
Write operations from occurring. The WRDI instruction
will not terminate any programming operation in prog-
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
04
SI
MSB
SO
HIGH IMPEDANCE
25135 WRDI.0
FIGURE 4-17:
4.5.14
WRITE DISABLE (WRDI) SEQUENCE
ENABLE-WRITE-STATUSREGISTER (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction
and opens the status register for alteration. The WriteStatus-Register instruction must be executed immediately after the execution of the Enable-Write-StatusRegister instruction. This two-step instruction
sequence of the EWSR instruction followed by the
WRSR instruction works like SDP (software data protection) command structure which prevents any accidental alteration of the status register values. CE# must
be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction
is executed.
4.5.15
WRITE-STATUS-REGISTER (WRSR)
The Write-Status-Register instruction writes new values to the BP1, BP0, and BPL bits of the status register.
CE# must be driven low before the command
sequence of the WRSR instruction is entered and
driven high before the WRSR instruction is executed.
See Figure 4-18 for EWSR or WREN and WRSR for
byte-data input sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”.
When the WP# is low, the BPL bit can only be set from
“0” to “1” to lock-down the status register, but cannot be
reset from “1” to “0”. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
and BP1 bits in the status register can all be changed.
As long as BPL bit is set to 0 or WP# pin is driven high
(VIH) prior to the low-to-high transition of the CE# pin at
the end of the WRSR instruction, the bits in the status
register can all be altered by the WRSR instruction. In
this case, a single WRSR instruction can set the BPL
bit to “1” to lock down the status register as well as
altering the BP0, BP1, and BP2 bits at the same time.
See Table 4-1 for a summary description of WP# and
BPL functions.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 0
01
50 or 06
SI
MSB
SO
MODE 3
MSB
STATUS
REGISTER IN
7 6 5 4 3 2 1 0
MSB
HIGH IMPEDANCE
25135 EWSR.0
FIGURE 4-18:
DS25135A-page 16
ENABLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND
WRITE-STATUS-REGISTER (WRSR) BYTE-DATA INPUT SEQUENCE
 2012 Microchip Technology Inc.
SST25PF020B
The Write-Status-Register instruction also writes new
values to the Status Register 1. To write values to Status Register 1, the WRSR sequence needs a worddata input—the first byte being the Status Register bits,
followed by the second byte Status Register 1 bits. CE#
must be driven low before the command sequence of
the WRSR instruction is entered and driven high before
the WRSR instruction is executed. See Figure 4-19 for
EWSR or WREN and WRSR instruction word-data
input sequences.
‘1’ to lock-down the status registers, but cannot be
reset from ‘1’ to ‘0’. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
BP1, TSP, and BSP bits in the status register can all be
changed. As long as BPL bit is set to 0 or WP# pin is
driven high (VIH) prior to the low-to-high transition of the
CE# pin at the end of the WRSR instruction, the bits in
the status register can all be altered by the WRSR
instruction. In this case, a single WRSR instruction can
set the BPL bit to “1” to lock down the status register as
well as altering the BPL, BP0, BP1, TSP, and BSP bits
at the same time. See Table 4-1 for a summary description of WP# and BPL functions.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to ‘1’. When
the WP# is low, the BPL bit can only be set from ‘0’ to
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
MODE 0
01
50 or 06
SI
MSB
MSB
STATUS
STATUS
REGISTER
REGISTER 1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
MSB
HIGH IMPEDANCE
SO
25135 EWSR1.0
FIGURE 4-19:
ENABLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND
WRITE-STATUS-REGISTER (WRSR) WORD-DATA INPUT SEQUENCE
The WRSR instruction can either execute a byte-data
or a word-data input. Extra data/clock input, or within
byte-/word-data input, will not be executed. The reason
for the byte support is for backward compatibility to
products where WRSR instruction sequence is followed by only a byte-data.
 2012 Microchip Technology Inc.
DS25135A-page 17
SST25PF020B
4.5.16
JEDEC READ-ID
The JEDEC Read-ID instruction identifies the device as
SST25PF020B and the manufacturer as Microchip.
The device information can be read from executing the
8-bit command, 9FH. Following the JEDEC Read-ID
instruction, the 8-bit manufacturer’s ID, BFH, is output
from the device. After that, a 16-bit device ID is shifted
out on the SO pin. Byte 1, BFH, identifies the manufac-
turer as Microchip. Byte 2, 25H, identifies the memory
type as SPI Serial Flash. Byte 3, 8CH, identifies the
device as SST25PF020B. The instruction sequence is
shown in Figure 4-20. The JEDEC Read ID instruction
is terminated by a low to high transition on CE# at any
time during data output.
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MODE 0
SCK
9F
SI
SO
HIGH IMPEDANCE
BF
25
MSB
8C
MSB
25135 JEDECID.1
FIGURE 4-20:
JEDEC READ-ID SEQUENCE
TABLE 4-6:
JEDEC READ-ID DATA
Device ID
Manufacturer’s ID
Memory Type
Memory Capacity
Byte1
Byte 2
Byte 3
BFH
25H
8CH
DS25135A-page 18
 2012 Microchip Technology Inc.
SST25PF020B
4.5.17
READ-ID (RDID)
The Read-ID instruction (RDID) identifies the devices
as SST25PF020B and manufacturer as Microchip. The
device information can be read from executing an 8-bit
command, 90H or ABH, followed by address bits [A23A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device
ID is located in address 00001H. Once the device is in
Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H
until terminated by a low to high transition on CE#.
Refer to Tables 4-6 and 4-7 for device identification
data.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47 48
55 56
63
MODE 0
90 or AB
SI
00
00
MSB
ADD1
MSB
HIGH IMPEDANCE
SO
BF
Device ID
BF
Device ID
HIGH
IMPEDANCE
MSB
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
Device ID = 8CH for SST25PF020B
1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
25135 RdID.0
FIGURE 4-21:
TABLE 4-7:
READ-ID SEQUENCE
PRODUCT IDENTIFICATION
Manufacturer’s ID
Address
Data
00000H
BFH
00001H
8CH
Device ID
SST25PF020B
 2012 Microchip Technology Inc.
DS25135A-page 19
SST25PF020B
5.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
TABLE 5-1:
Range
OPERATING RANGE
TABLE 5-2:
AC CONDITIONS OF TEST1
Ambient Temp
VDD
Input Rise/Fall Time
Output Load
0°C to +70°C
2.3-3.6V
5ns
CL = 30 pF
Commercial
1. See Figures 5-6 and 5-7
TABLE 5-3:
DC OPERATING CHARACTERISTICS
Limits
Symbol Parameter
Max
Units
IDDR
Read Current
12
mA
CE#=0.1 VDD/0.9 VDD@33 MHz, SO=open
IDDR3
Read Current
20
mA
CE#=0.1 VDD/0.9 VDD@80 MHz, SO=open
IDDW
Program and Erase Current
30
mA
CE#=VDD
ISB
Standby Current
20
µA
CE#=VDD, VIN=VDD or VSS
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
1
µA
VOUT=GND to VDD, VDD=VDD Max
0.7
V
VDD=VDD Min
V
VDD=VDD Max
V
IOL=100 µA, VDD=VDD Min
ILO
Output Leakage Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOL2
Output Low Voltage
VOH
Output High Voltage
DS25135A-page 20
Min
0.7 VDD
0.2
0.4
VDD-0.2
Test Conditions
V
IOL=1.6 mA, VDD=VDD Min
V
IOH=-100 µA, VDD=VDD Min
 2012 Microchip Technology Inc.
SST25PF020B
TABLE 5-4:
CAPACITANCE (TA = 25°C, F=1 MHZ, OTHER PINS OPEN)
Parameter
Description
COUT1
CIN1
Output Pin Capacitance
Input Capacitance
Test Condition
Maximum
VOUT = 0V
12 pF
VIN = 0V
6 pF
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 5-5:
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
Test Method
NEND1
Endurance
10,000
Cycles
JEDEC Standard A117
TDR1
ILTH1
Data Retention
100
Years
JEDEC Standard A103
100 + IDD
mA
Latch Up
JEDEC Standard 78
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 5-6:
AC OPERATING CHARACTERISTICS, 2.3-2.7V
25 MHz
Symbol
Parameter
Min
50 MHz
Max
Min
Max
Units
50
MHz
1
Serial Clock Frequency
TSCKH
Serial Clock High Time
TSCKL
Serial Clock Low Time
18
9
ns
TSCKR
Serial Clock Rise Time (Slew Rate)
0.1
0.1
V/ns
TSCKF
Serial Clock Fall Time (Slew Rate)
0.1
0.1
V/ns
TCES2
CE# Active Setup Time
5
5
ns
TCEH2
TCHS2
TCHH2
CE# Active Hold Time
5
5
ns
CE# Not Active Setup Time
5
5
ns
CE# Not Active Hold Time
5
5
ns
TCPH
CE# High Time
50
50
ns
FCLK
25
18
9
ns
TCHZ
CE# High to High-Z Output
TCLZ
SCK Low to Low-Z Output
0
0
ns
TDS
Data In Setup Time
2
2
ns
TDH
Data In Hold Time
4
4
ns
THLS
HOLD# Low Setup Time
5
5
ns
THHS
HOLD# High Setup Time
5
5
ns
THLH
HOLD# Low Hold Time
5
5
ns
THHH
HOLD# High Hold Time
5
5
ns
THZ
HOLD# Low to High-Z Output
7
7
ns
TLZ
HOLD# High to Low-Z Output
7
7
ns
TOH
Output Hold from SCK Change
TV
Output Valid from SCK
12
8
ns
TSE
Sector-Erase
25
25
ms
TBE
Block-Erase
25
25
ms
TSCE
Chip-Erase
50
50
ms
TBP
Byte-Program
10
10
µs
7
0
7
0
ns
ns
1. Maximum clock frequency for Read instruction, 03H, is 25 MHz
2. Relative to SCK
 2012 Microchip Technology Inc.
DS25135A-page 21
SST25PF020B
TABLE 5-7:
AC OPERATING CHARACTERISTICS, 2.7-3.6V
33 MHz
Symbol
Parameter
FCLK1
Serial Clock Frequency
Min
80 MHz
Max
Min
33
Max
Units
80
MHz
TSCKH
Serial Clock High Time
13
6
ns
TSCKL
Serial Clock Low Time
13
6
ns
TSCKR2
Serial Clock Rise Time (Slew Rate)
0.1
0.1
V/ns
TSCKF
Serial Clock Fall Time (Slew Rate)
0.1
0.1
V/ns
TCES3
TCEH3
TCHS3
TCHH3
CE# Active Setup Time
5
5
ns
CE# Active Hold Time
5
5
ns
CE# Not Active Setup Time
5
5
ns
CE# Not Active Hold Time
5
5
ns
50
TCPH
CE# High Time
TCHZ
CE# High to High-Z Output
50
15
ns
7
ns
TCLZ
SCK Low to Low-Z Output
0
0
ns
TDS
Data In Setup Time
2
2
ns
TDH
Data In Hold Time
4
4
ns
THLS
HOLD# Low Setup Time
5
5
ns
THHS
HOLD# High Setup Time
5
5
ns
THLH
HOLD# Low Hold Time
5
5
ns
THHH
HOLD# High Hold Time
5
THZ
HOLD# Low to High-Z Output
TLZ
HOLD# High to Low-Z Output
TOH
Output Hold from SCK Change
TV
Output Valid from SCK
10
6
ns
TSE
Sector-Erase
25
25
ms
TBE
Block-Erase
25
25
ms
TSCE
Chip-Erase
50
50
ms
TBP
Byte-Program
10
10
µs
5
7
ns
7
7
7
0
0
ns
ns
ns
1. Maximum clock frequency for Read Instruction, 03H, is 33 MHz
2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
3. Relative to SCK.
TCPH
CE#
TCHH
TCES
TSCKF
TCEH
TCHS
SCK
TDS
SI
SO
TDH
TSCKR
MSB
LSB
HIGH-Z
HIGH-Z
25135 SerIn.0
FIGURE 5-1:
DS25135A-page 22
SERIAL INPUT TIMING DIAGRAM
 2012 Microchip Technology Inc.
SST25PF020B
CE#
TSCKH
TSCKL
SCK
TOH
TCLZ
SO
TCHZ
MSB
LSB
TV
SI
25135 SerOut.0
FIGURE 5-2:
SERIAL OUTPUT TIMING DIAGRAM
CE#
THHH
THHS
THLS
SCK
THLH
THZ
TLZ
SO
SI
HOLD#
25135 Hold.0
FIGURE 5-3:
HOLD TIMING DIAGRAM
 2012 Microchip Technology Inc.
DS25135A-page 23
SST25PF020B
5.1
Power-Up Specifications
All functionalities and DC specifications are specified
for a VDD ramp rate of greater than 1V per 100 ms (0V
- 3.0V in less than 300 ms). See Table 5-8 and Figure
5-4 for more information.
TABLE 5-8:
RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1
VDD Min to Read Operation
100
µs
TPU-WRITE1
VDD Min to Write Operation
100
µs
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
VDD
VDD Max
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
VDD Min
TPU-READ
TPU-WRITE
Device fully accessible
Time
25135 PwrUp.0
FIGURE 5-4:
POWER-UP TIMING DIAGRAM
TABLE 5-9:
RECOMMENDED POWER-UP/-DOWN LIMITS
Limits
Symbol
Parameter
Min
Max
Units
TPF
VDD Falling Time
1
100
ms/V
TPR
VDD Rising Time
0.033
100
ms/V
TOFF
VDD Off Time
VOFF
VDD Off Level
DS25135A-page 24
100
Conditions
ms
0.3
V
0V (recommended)
 2012 Microchip Technology Inc.
SST25PF020B
VDD
VOFF
GND
25135 F28.1
TOFF
FIGURE 5-5:
RECOMMENDED POWER-UP/-DOWN WAVEFORM
VIHT
VHT
INPUT
VHT
REFERENCE POINTS
OUTPUT
VLT
VLT
VILT
25135 IORef.0
AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement
reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 5-6:
AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
CL
25135 TstLd.0
FIGURE 5-7:
A TEST LOAD EXAMPLE
 2012 Microchip Technology Inc.
DS25135A-page 25
SST25PF020B
6.0
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
XX
PART NO.
Operating
Frequency
Device
XX
XXX
X
Endurance/
Temperature
Package
Tape/Reel
Indicator
Device:
SST25PF020B
= 2 Mbit, 2.3-3.6V, Serial Peripheral Interface flash memory
Operating
Frequency:
80
= 80 MHz
Endurance:
4
= 10,000 cycles
Temperature:
C
= 0°C to +70°C
Package:
QAE
SAE
Q3AE
= WSON (6mm x 5mm), 8-contact
= SOIC (150 mil), 8-lead
= USON(3mm x 2mm), 8-contact
Tape and
Reel Flag:
T
= Tape and Reel
DS25135A-page 26
Valid Combinations:
SST25PF020B-80-4C-QAE
SST25PF020B-80-4C-QAE-T
SST25PF020B-80-4C-SAE
SST25PF020B-80-4C-SAE-T
SST25PF020B-80-4C-Q3AE
SST25PF020B-80-4C-Q3AE-T
 2012 Microchip Technology Inc.
SST25PF020B
7.0
PACKAGING DIAGRAMS
Pin #1
Identifier
TOP VIEW
SIDE VIEW
7°
4 places
0.51
0.33
5.0
4.8
1.27 BSC
END VIEW
4.00
3.80
6.20
5.80
45°
0.25
0.10
1.75
1.35
0.25
0.19
Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
FIGURE 7-1:
7°
4 places
0°
8°
08-soic-5x6-SA-8
1.27
0.40
1mm
8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 150MIL BODY WIDTH (5MM X 6MM)
PACKAGE CODE: SA
 2012 Microchip Technology Inc.
DS25135A-page 27
SST25PF020B
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Pin #1
0.2
Pin #1
Corner
1.27 BSC
5.00 ± 0.10
0.076
4.0
0.48
0.35
3.4
0.70
0.50
0.05 Max
6.00 ± 0.10
0.80
0.70
Note: 1. All linear dimensions are in millimeters (max/min).
2. Untoleranced dimensions (shown with box surround)
are nominal target dimensions.
3. The external paddle is electrically connected to the
1mm
die back-side and possibly to certain VSS leads.
This paddle can be soldered to the PC board;
it is suggested to connect this paddle to the VSS of the unit.
Connection of this paddle to any other voltage potential can
result in shorts and/or electrical malfunction of the device.
FIGURE 7-2:
DS25135A-page 28
CROSS SECTION
0.80
0.70
8-wson-5x6-QA-9.0
8-CONTACT VERY-VERY-THIN SMALL OUTLINE NO-LEAD (WSON)
PACKAGE CODE: QA
 2012 Microchip Technology Inc.
SST25PF020B
2.45
3.00
±0.10
0.25
±0.05
Pin #1
(laser
engraved
see note 2)
See notes
3 &4
Pin # 1
1.60
2.00
±0.10
0.5 BSC
0.15 max
0.08
0.05 Max
0.60
0.45
0.40
±0.05
0.2
0.35
±0.05
1mm
8-uson-2x2-Q3A-1.1
Note: 1.
2.
3.
4.
5.
6.
FIGURE 7-3:
Similar to JEDEC JEP95 MO-252 variant U2030D, though number of contacts and some dimensions may be different.
The topside pin #1 indicator is laser engraved; its approximate shape and location is as shown.
From the bottom view, the pin #1 indicator may be either a curved indent or a 45-degree chamfer.
Untoleranced dimensions are nominal target dimensions.
All linear dimensions are in millimeters (max/min).
Lead-frame nominal thickness 0.127mm or 0.15mm (supplier-dependent).
8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (USON)
PACKAGE CODE: Q3A
 2012 Microchip Technology Inc.
DS25135A-page 29
SST25PF020B
TABLE 7-1:
REVISION HISTORY
Revision
A
Description
•
DS25135A-page 30
Initial release of spec
Date
Nov 2012
 2012 Microchip Technology Inc.
SST25PF020B
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQs), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
 2012 Microchip Technology Inc.
DS25135A-page 31
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-678-1
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2012 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS25135A-page 32
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 852-2401-1200
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 2012 Microchip Technology Inc.
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DS25135A-page 33