UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 ECONOMY HIGH-SPEED PWM CONTROLLER FEATURES D Peak Current Mode, Average Current Mode, D D D D D D D D D D D DESCRIPTION The UC28023 and UC28025 are fixed-frequency PWM controllers optimized for high-frequency switched-mode power supply applications. The UC28023 is a single output PWM for single-ended topologies while the UC28025 offers dual alternating outputs for double-ended and full bridge topologies. or Voltage Mode (with Feed-Forward) Control Methods Practical Operation Up to 1 MHz 50-ns Propagation Delay to Output ±1.5-A Peak Totem Pole Outputs 9-V to 30-V Nominal Operational Voltage Range Wide Bandwidth Error Amplifier Fully Latched Logic with Double Pulse Suppression Pulse-by-Pulse Current Limiting Programmable Maximum Duty Cycle Control Under--Voltage Lockout with Hysteresis Trimmed 5.1-V Reference with UVLO Same Functionality as UC3823 and UC3825 Targeted for cost effective solutions with minimal external components, UC2802x include an oscillator, a temperature compensated reference, a wide band width error amplifier, a high-speed current-sense comparator and high-current active-high totem-pole outputs to directly drive external MOSFETs. Protection circuitry includes a current limit comparator with a 1-V threshold, a TTL compatible shutdown port, and a soft-start pin which will double as a maximum duty cycle clamp. The logic is fully latched to provide jitter free operation and prohibit multiple pulses at an output. An undervoltage lockout section with 800 mV of hysteresis assures low start-up current. During undervoltage lockout, the outputs are high impedance. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. APPLICATIONS D Off-Line and DC/DC Power Supplies D Converters Using Voltage Mode, Peak D Current Mode, or Average Current Mode Control Methods Single-Ended or Two-Switch Topology Designs Devices are available in the industrial temperature range of --40°C to 105°C. Package offerings are 16-pin SOICW (DW), or 16-pin PDIP (N) packages. ORDERING INFORMATION TA = TJ --40°C 40°C to 105°C (1) PACKAGED DEVICES OUTPUT CONFIGURATION EXTERNAL CURRENT LIMIT REFERENCE PDIP-16 (N) SOICW--16 (DW) Single Yes UC28023N UC28023DW Dual Alternating No UC28025N UC28025DW The DW package are also available taped and reeled. Add an R suffix to the device type (i.e., UC28023DWR (2,000 devices per reel). PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005 -- 2010, Texas Instruments Incorporated www.ti.com 1 UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UC28023 Input voltage range, UC28025 UNIT VC, VCC VC, VCC 30 V Output current, IOUT(DC) OUT OUTA, OUTB ±0.5 A Peak output current, pulsed 0.5 ms IOUT(pulsed) OUT OUTA, OUTB ±2.0 A 200 pF Capacitive load, CLOAD Analog inputs Output current, IREF Output current, ICLOCK Soft-start sink current, ISINK_SS Output current, IOUT(EA) Oscillator charging current, IOSC_CHG Power Dissipation at TA = 25°C (all packages) INV, NI, RAMP INV, NI, RAM --0.3 V to 7 V SS, ILIM/SD SS, ILIM/SD VREF + 0.3 V, --0.3 V VREF VREF 10 CLOCK CLOCK --5 SS SS 5 EAOUT EAOUT 20 RT RT --5 1 Operating junction temperature range, TJ --55 to 150 Storage temperature, Tstg --65 to 150 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, Tsol (1) 2 RATING V mA W °C C 300 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. All currents are positive into and negative out of the specified terminal. www.ti.com UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 UC28023 N PACKAGE (TOP VIEW) INV NI EAOUT CLOCK RT CT RAMP SS 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 UC28023 DW PACKAGE (TOP VIEW) VREF VCC OUT VC PGND ILIMREF GND ILIM/SD 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VREF VCC OUT VC PGND ILIMREF GND ILIM/SD UC28025 DW PACKAGE (TOP VIEW) UC28025 N PACKAGE (TOP VIEW) INV NI EAOUT CLOCK RT CT RAMP SS INV NI EAOUT CLOCK RT CT RAMP SS VREF VCC OUTB VC PGND OUTA GND ILIM/SD INV NI EAOUT CLOCK RT CT RAMP SS www.ti.com 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VREF VCC OUTB VC PGND OUTA GND ILIM/SD 3 UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS TA = --40°C to 105°C , TJ = TA, RT = 3.65 kΩ, CT = 1 nF, VCC = 15 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.05 V REFERENCE VREF Reference voltage TJ = 25°C, 5.10 5.15 Line regulation voltage 10 V ≤ VCC ≤ 30 V 2 15 Load regulation voltage 1 mA ≤ IREF ≤ 10 mA 5 15 Temperature stability(1) T(min) < TA < T(max) Total output voltage variation(1) Line, load, temperature Output noise ISS voltage(1) IREF = 1 mA 0.2 4.95 10 Hz < f < 10 kHz 0.4 mV/°C 5.25 V 50 Long term stability voltage(1) TJ = 125°C, Short circuit current VREF = 0 V --20 Initial accuracy(1) TJ = 25°C 360 Voltage stability(1) 10 V ≤ VCC ≤ 30 V Temperature stability(1) T(min) < TA < T(max) Total voltage variation(1) Line, temperature 1000 hours mV μV 5 25 mV --50 --100 mA 400 440 kHz 0.2% 2.0% OSCILLATOR fOSC VCLOCK_H High-level clock output voltage VCLOCK_L Low-level clock output voltage VRAMP(p) Ramp peak voltage(1) 3.9 voltage(1) VRAMP(v) Ramp valley VRAMP(v-p) Ramp vally-to-peak voltage(1) 5% 340 460 kHz 4.5 2.3 2.9 2.6 2.8 3.0 0.70 1.00 1.25 1.6 1.8 2.0 V ERROR AMPLIFIER VIN Input offset voltage IBIAS Input bias current 0.6 3.0 15 IIN Input offset current 0.1 1.0 AVOL Open loop gain 1 V ≤ VOUT ≤ 4 V 60 95 CMRR Common mode rejection ratio 1.5 V ≤ VCM ≤ 5.5 V 75 95 PSRR Power supply rejection ratio 10 V ≤ VCC ≤ 30 V 85 110 IOUT(sink) Output sink current V(EAOUT) = 1 V 1.0 2.5 IOUT(src) Output source current V(EAOUT) = 4 V --0.5 --1.3 VOH High-level output voltage I(EAOUT) = --0.5 mA 4.0 4.7 5.0 VOL Low-level output voltage I(EAOUT) = 1 mA 0 0.5 1.0 3.0 5.5 MHz 6 12 V/μs 80% 90% 40% 45% Unity gain bandwidth(1) Slew rate(1) mV μA A dB mA V PWM COMPARATOR IBIAS RAMP bias current Maximum duty cycle Minimum duty cycle EAOUT zero DC threshold tDELAY (1) Ensured Delay to output VRAMP = 0 V UC28023 UC28025 (2) UC28023 --5 μA 0% UC28025 0% VRAMP = 0 V time(1) by design. Not production tested. (2) Tested as 80% minimum for the oscillator which is the equivalent of 40% for UC28025. 4 --1 www.ti.com 1.10 1.25 1.40 V 50 100 ns UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS TA = --40°C to 105°C , TJ = TA, RT = 3.65 kΩ, CT = 1 nF, VCC = 15 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 20 UNIT SOFT-START ICHG Charge current VSS = 0.5 V 3 9 IDISCHG Discharge current VSS = 1.0 V 1.0 7.5 μA mA CURRENT LIMIT/SHUTDOWN ILIMIT Current limit bias current ILIMIT Offset voltage UC28023 0 V < V(ILIM/SD) < 4 V ILIMREF Common mode range(1) UC28023 1.00 Current limit threshold voltage UC28025 0.9 1.0 1.1 1.25 1.40 1.55 50 80 0.25 0.40 1.2 2.2 Shutdown threshold voltage tDELAY Delay to output time(1) ±10 μA 15 mV 1.25 V ns OUTPUT VOL VOH IOUT = 20 mA Low level output voltage Low-level IOUT = 200 mA IOUT = --20 mA High level output voltage High-level 13.0 IOUT = --200 mA 13.5 V 12 13 100 500 μA 30 60 ns Start threshold voltage 8.8 9.2 9.6 Hysteresis 0.4 0.8 1.2 Collector leakage VC = 30 V Rise time / Fall time(1) CLOAD = 1 nF UNDERVOLTAGE LOCKOUT (UVLO) V SUPPLY CURRENT ICC (1) Start-up current VCC = 8 V 1.1 2.0 Operating current VINV = VRAMP = VILIM = 0 V VINV = 1 V 25 35 mA Ensured by design. Not production tested. THERMAL RESISTANCE PACKAGE θJA (°C/W) θJC (°C/W) N(2) 90(2) 45 DW(2) 50--100(2) 27 (2) Specified θJA (junction-to-ambient) is for devices mountied to 5-square-inch FR4 PC board with one ounce copper where noted. When resistance range is given, lower values are for 5-square-inch aluminum PC board. Test PWB is 0.062 inches thick and typically uses 0.635 mm trace width for power packages and 1.3 mm trace widths for non-power packages with a 100x100 mil probe land area at the end of each trace. www.ti.com 5 UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 FUNCTIONAL BLOCK DIAGRAM CLOCK 4 UC28025 RT 5 CT 6 EAOUT 3 NI 2 INV 1 11 OUTA PWM Latch + 1.25 V RAMP 7 13 VC Toggle F/F OSCILLATOR T R 14 OUTB SD Wide Bandwidth Error Amplifier 12 PGND VIN + 9 μA UC28023 Inhibit 13 VC 14 OUT SS 8 ILIMREF 11 (UC28023 Only) 1V (UC28025 Only) 1V 12 PGND ILIM Comparator Shutdown Comparator ILIM/SD 9 Internal Bias 1.4 V 16 VREF VCC 15 VCC Good REF GEN 9V GND 10 VREF Good 4V UVLO Output Inhibit UDG--03048 6 www.ti.com UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 TERMINAL FUNCTIONS NAME TERMINAL I/O DESCRIPTION UC28023 UC28025 CLOCK 4 4 O Output of the internal oscillator CT 6 6 I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length. EAOUT 3 3 O Output of the error amplifier for compensation GND 10 10 -- Analog ground return pin. ILIM/SD 9 9 I Input to the current limit comparator and the shutdown comparator. ILIMREF 11 -- I Pin to set the current limit threshold externally. INV 1 1 I Inverting input to the error amplifier NI 2 2 I Non-inverting input to the error amplifier OUT 14 -- O High current totem pole output of the on-chip drive stage. OUTA -- 11 O High current totem pole output A of the on-chip drive stage. OUTB -- 14 O High current totem pole output B of the on-chip drive stage. PGND 12 12 -- Ground return pin for the output driver stage RAMP 7 7 I Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode operation this serves as the input voltage feed-forward function by using the CT ramp. In peak current mode operation, this serves as the slope compensation input. RT 5 5 I Timing resistor connection pin for oscillator frequency programming SS 8 8 I Soft-start input pin. VC 13 13 -- Power supply pin for the output stage. This pin should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths. VCC 15 15 -- Power supply pin for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths VREF 16 16 O 5.1--V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane. www.ti.com 7 UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION + VIN 42 V to 56 V -- VOUT 5 V 1 A to 10 A 12 V + 0.1 μF 15 13 VCC VC 16 VREF 4.7 μF 15 V OUTB 14 -5:1 1Ω OUTA 11 4.3 kΩ 10 kΩ UC28025 1 INV 6 μF 1 kΩ 1N 5820 2 NI 0.8 μH 4.7 μF 1 kΩ ILIM/SD 9 1 nF 22 pF 3.3 kΩ 3 EAOUT RAMP 7 8.2 kΩ 10 nF 4 CLOCK 5 RT 1.5 kΩ CT 6 PGND 12 GND SS 10 8 1 kΩ 120 pF CT 470 pF 0.1 μF UDG--03047 Figure 1. Typical Application: 1.5 MHz, 48-V to 5-V DC/DC Push-Pull Converter Using UC28025 8 www.ti.com UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION PCB LAYOUT CONSIDERATIONS High speed circuits demand careful attention to layout and component placement. To assure proper performance of the UC2802x follow these rules: 1. Use a ground plane. 2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves this purpose. 3. Bypass VCC, VC, and VREF. Use 0.1-μF monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1-cm of total lead length for each capacitor between the bypassed pin and the ground plane. 4. Treat the timing capacitor, CT, as a bypass capacitor. ERROR AMPLIFIER Figure 2 shows a simplified schematic of the UC2802x error amplifier and Figures 3 and 4 show its characteristics. 5.1 V INV 16 VREF 3 1 EAOUT 200 Ω NI 2 UDG--03049 Figure 2. Simplified Error Amplifier Schematic www.ti.com 9 UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION GAIN AND PHASE vs FREQUENCY 100 VOLTAGE vs TIME 5 VIN GAIN 60 AV -- Gain -- dB VSEAout -- E/A Output Voltage -- V 80 40 20 0 0 --20 --90 --40 100 1k 10 k 100 k 1M 10 M --180 100 M Phase -- ° PHASE 4 3 2 1 0 0.2 0.4 0.6 tdelay -- Delay Time-- μs fOSC -- Frequency -- Hz Figure 3. Open Loop Frequency Response VOUT 0.8 1.0 Figure 4. Unity Gain Slew Rate CONTROL METHODS UC2802x UC2802x CT CT 6 RAMP OSCILLATOR RAMP 1.25 V * RSENSE From Error Amplifier OSCILLATOR 7 * UDG--03050 From Error Amplifier * A small filter may be required to supress switch noise. UDG--03050 Figure 6. Peak Current Mode Control Figure 5. Voltage Mode Control 10 6 1.25 V 7 CT CT ISENSE www.ti.com UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION OSCILLATOR IR 10.0 UC2802x RT 3 kΩ ≤ RT ≤ 100 kΩ 5 4.70 3V IC = IR 2.20 TD -- Dead Time -- μs CT 6 5.1 V CLOCK 4 DEAD TIME vs TIMING CAPACITANCE 1.00 0.47 0.22 Blanking 0.10 TD 400 μA 0.047 0.47 UDG--03052 2.2 4.7 10.0 22.0 47 CT -- Timing Capacitance -- nF 100 Figure 8. Figure 7. Oscillator Circuit TIMING RESISTANCE vs FREQUENCY 100 k 1.0 160 DEAD TIME vs FREQUENCY 4.7 nF 140 1 nF 470 pF 10 k 100 nF TD -- Dead Time -- ns RT -- Timing Resistance -- Ω 2.2 nF 47 nF CT = 1 nF 120 CT = 470 pF 100 22 nF 10 nF 1k 100 1k 10 k 100 k 1M fOSC -- Frequency -- Hz 80 10 k 100 k fOSC -- Frequency -- Hz 1M Figure 10. Figure 9. Oscillator Circuit www.ti.com 11 UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION SYNCHRONIZATION Figure 11 shows a generalized synchronization. Figure 12 shows a synchronozed operation of two units in close proximity. UC2802x (Master) UC2802x (Slave) VREF 16 RT 1.15 Ω 10 μF CLOCK 43 Ω 0.1 μF 43 Ω 0.1 μF 5 CT CT RT 6 CT 2N222 4 RT RT 5 6 43 Ω Local Ramp 0.1 μF 24 Ω CT To other slaves 24 Ω Local Ramp 470 Ω UDG--03050 Figure 11. Generalized Synchronization UC2802x (Master) CLOCK UC2802x (Slave) 4 4 CLOCK 16 VREF RT RT 5 CT 6 Local Ramp 5 RT 6 CT CT UDG--03050 Figure 12. Synchronization of Two Units In Close Proximity 12 www.ti.com UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION FEEDFORWARD CIRCUIT VIN UC2802x RFF CFF 7 RAMP 4 CLOCK 6 CT 5 RT UDG--03050 Figure 13. Feedforward Technique for Off-Line Voltage-Mode Applications CONSTANT VOLT-SECOND CLAMP CIRCUIT The circuit for the UC28023 shown in Figure 14 describes achievement a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 (ILIM/SD) crosses the 1-V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional inverter block must be such that the ramp capacitor can be completely discharged during the minimum deadtime. UC28023 VIN OUT RT 14 ILIM/SD 9 CR UDG--03050 Figure 14. Achieving Constant Volt-Second Product Clamp with the UC28023 www.ti.com 13 UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 The circuit for the UC28025 shown in Figure 15 describes achievement a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 (ILIM/SD) crosses the 1-V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional inverter block must be such that the ramp capacitor can be completely discharged during the minimum deadtime. UC28025 VIN OUTB RT 14 ILIM/SD 9 OUTA 11 CR UDG--03050 Figure 15. Achieving Constant Volt-Second Product Clamp with the UC28025 14 www.ti.com UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION OUTPUTS UC28023 has one output and UC28025 has dual alternating outputs. UC2802x SATURATION VOLTAGE vs OUTPUT CURRENT 3 15 VCC VSAT -- Saturation Voltage -- V 13 VC OUTx 2 Source 1 12 PWRGND Sink 10 GND 0 0 0.25 Figure 16. Simplified Schematic --0.2 10 5 40 80 120 160 tRISE (tFALL) -- Time -- ns CLOAD = 10 nF 0.2 0 200 15 ILOAD -- Load Current -- A VOUT -- Output Voltage -- V 0 0 1.50 RISE/FALL TIME vs OUTPUT VOLTAGE AND LOAD CURRENT VOUT -- Output Voltage -- V 0.2 ILOAD -- Load Current -- A CLOAD = 1 nF 0 1.25 Figure 17. RISE/FALL TIME vs OUTPUT VOLTAGE AND LOAD CURRENT 15 0.50 0.75 1.00 IOUT -- Output Current -- A --0.2 10 5 0 0 100 200 300 400 tRISE (tFALL) -- Time -- ns 500 Figure 19. Figure 18. www.ti.com 15 UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION Open Loop Laboratory Test Fixture The following test fixture is useful for exercising many of the UC28025’s functions and measuring their specifications. As with any wideband circuit, careful ground and by-pass procedures should be followed. The use of a ground plane is highly recommended. UC28025 0.1 μF VCC 15 4 CLOCK RT 3.65 kΩ 5 RT 0.1 μF 6 CT 200 Ω 3 EAOUT 27 kΩ 50 Ω 10 kΩ 4.7 kΩ 68 kΩ 2 NI 22 kΩ 27 kΩ 10 kΩ 10 μF OUTA 11 OUTB 14 ERROR AMPLIFIER 1 INV 4.7 kΩ 15 V 10 uF OSCILLATOR VC 13 CT 1.0 nF 7 RAMP 15 V 1N5820 1N5820 PGND 12 GND 10 8 SS 0.1 μF 10 μF VREF 16 9 ILIM/SD 3.3 kΩ UDG--03051 Figure 20. Laboratory Test Fixture References 1. 1.5-MHz Current Mode IC Controlled 50--Watt Power Supply, Texas Instruments Application Note Literature No. SLUA053. 2. The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, Texas Instruments Application Note Literature No. SLUA125. Revision History Rev E to Rev F 1. Updated Typical Application Diagram, Figure 1, page 8. 16 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UC28023DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28023DW UC28023DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28023DW UC28023DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28023DW UC28023DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28023DW UC28023N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 105 UC28023N UC28023NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 105 UC28023N UC28025DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28025DW UC28025DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28025DW UC28025DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28025DW UC28025DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28025DW UC28025N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 105 UC28025N UC28025NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 105 UC28025N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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