TI LM3017LEX/NOPB

LM3017
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SNOSC66C – MARCH 2012 – REVISED MARCH 2013
High Efficiency Low-Side Controller with True Shutdown
Check for Samples: LM3017
FEATURES
KEY SPECIFICATION
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1
2
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Fully Compliant to Thunderbolt™ Technology
Specifications
True Shutdown for Short Circuit Protection
Input Side Current Limit
Single Enable Pin with Three Modes of
Operation: Boost, Pass Through, or Shutdown
Built-in Charge Pump for High-side NFET
Disconnect Switch
1A Push-pull Driver for Low-side NFET
Peak Current Mode Control
Simple Slope Compensation
Protection Features: Thermal Shutdown,
Cycle-by-cycle Current Limit, Short Circuit
Protection, Output Overvoltage Protection, and
Latch-off
Internal Soft-start
2.4mm × 2.7mm × 0.8mm 10-pin QFN Package
APPLICATIONS
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Thunderbolt Technology™ Host Ports
Notebook and Desktop Computers, Tablets,
and Other Portable Consumer Electronics
Hard Disc Drives, Solid State Drives
Offline Power Supplies
Set-Top Boxes
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Input Voltage Range of 5V to 18V
600 kHz fixed Frequency Operation
±1% Reference Voltage Accuracy Over
Temperature
Low Shutdown Current (< 1µA), 40nA Typical
DESCRIPTION
The LM3017 is a versatile low-side NFET controller
incorporating true shutdown and input side current
limiting. It is designed for simple implementation of
boost conversions in Thunderbolt™ Technology. The
LM3017 can also be configured for flyback or SEPIC
designs. The input voltage range of 5V to 18V
accommodates a two or three cell lithium ion battery
or a 12V rail. The enable pin accepts a single input to
drive three different modes of operation: boost, pass
through, or shutdown mode. The LM3017 draws very
low current in shutdown mode, typically 40nA from
the input supply.
The LM3017 provides an adjustable output in order to
drive the Power Load Switch or Mux for the host
Thunderbolt™ port. The ability to drive an external
high-side NMOS provides for true isolation of the load
from the input. Current limiting on the input ensures
that inrush and short-circuit currents are always under
control. The LM3017 incorporates built in thermal
shutdown, cycle-by-cycle current limit, short-circuit
protection, output overvoltage protection, and softstart. It is available in a 10-pin QFN package.
TYPICAL APPLICATION CIRCUIT
30180901
Typical Boost Converter Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Thunderbolt is a trademark of Intell Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
LM3017
SNOSC66C – MARCH 2012 – REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAM
10-PIN VQFN
TOP VIEW
30180903
PIN DESCRIPTIONS
PIN
NAME
NO.
DESCRIPTION
FUNCTION
VCC
1
Driver supply voltage pin
Output of internal regulator powering low side NMOS driver. A minimum of 0.47µF
must be connected from this pin to PGND for proper operation.
DR
2
Low-side NMOS gate driver
output
Output gate drive to low side NMOS gate.
PGND
3
Power Ground
Ground for power section. External power circuit reference. Should be connected
to AGND at a single point.
VG
4
High side NMOS gate driver
output
Output gate drive to high side NMOS gate.
EN/MODE
5
Multi-function input pin
This input provides for chip enable, and mode selection. See functional description
for details.
FB
6
Feed-back input pin
Negative input to error amplifier. Connect to feed-back resistor tap to regulate
output.
COMP
7
Compensation pin
A resistor and capacitor combination connected to this pin provides frequency
compensation for the regulator control loop.
AGND
8
Analog Ground
Ground for analog control circuitry. Reference point for all stated voltages.
ISEN
9
Current sense input
Current sense input, with respect to Vin, for all current limit functions.
VIN
10
Power Supply input pin
Input supply to regulator. See applications section for recommendations on bypass
capacitors on this pin.
2
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ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN to PGND, AGND
–0.3
20
V
FB, COMP, VCC,DR to PGND, AGND
–0.2
6
V
EN/MODE
-0.2
5.5
V
VG
-0.3
VIN+6
V
VIN-0.3
VIN
V
1.0
A
150
°C
ISEN to PGND, AGND
Peak low side driver output current
Power Dissipation
UNIT
Internally Limited
Storage Temperature Range
–65
Junction Temperature
150
°C
ESD Susceptibility, Human Body Model (3)
1.5
kV
(1)
(2)
(3)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings indicates conditions for which
the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method is per JESD-22-114.
OPERATING RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TJ
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Voltage, VIN
5.4
18
V
Junction Temperature Range
–40
+125
°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings indicates conditions for which
the device is intended to be functional, but does NOT guarantee specific performance limits. For specifications and test conditions, see
the Electrical Characteristics. The specifications apply only for the test conditions.
ELECTRICAL CHARACTERISTICS
Limits in standard type are for TJ = 25°C only; limits apply over the junction temperature (TJ) range of –40°C to +125°C.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 12V.
SYMBOLS
PARAMETER
TEST CONDITIONS
VFB
Feedback Voltage
Vcomp = 1.4V
ΔVLINE
Feedback Voltage Line Regulation
5V ≤ Vin ≤ 18V
Input Under Voltage Lock-Out
Voltage
Rising
Input Under Voltage Lock-Out
Hysteresis
Falling; below VUVLO
Nominal Switching Frequency
EN/MODE = 1.6 V
VUVLO
FSW
RDS(ON)
Low side NMOS driver resistance;
top driver FET
Low side NMOS driver resistance;
bottom driver FET
VCC
Driver Voltage Supply
Dmax
Maximum Duty Cycle
Tmin(on)
Minimum On Time
(1)
(2)
MIN (1)
TYP (2)
MAX (1)
1.256
1.27
1.282
0.33
4.6
4.82
600
V
%
4.9
280
550
UNIT
V
mV
635
kHz
3.4
Ω
VIN = 5V, IDR = 0.2 A
1
VIN < 6 V
VIN
VIN ≥ 6 V
5.6
V
86
%
125
ns
All limits are specified at room temperature (standard type face) and at temperature extremes (bold type face). All room temperatures
are 100% production tested. All limits at temperature extremes are specified via correlation using Statistical Quality Control (SQD)
methods. All limits are used to calculate Average Outgoing Quaity Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
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ELECTRICAL CHARACTERISTICS (continued)
Limits in standard type are for TJ = 25°C only; limits apply over the junction temperature (TJ) range of –40°C to +125°C.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 12V.
SYMBOLS
PARAMETER
MIN (1)
TEST CONDITIONS
IQ-boost
Supply Current in Boost Mode - No
switching
EN/MODE = 1.6V, FB = 1.4V
IQ-SD
Supply Current in Shutdown Mode
EN/MODE pin = 0.4V
IQ-pass
Supply Current in Pass-Through
mode
EN/MODE = 2.6V, FB = 1.4V
TYP (2)
MAX (1)
5.2
9
mA
0.025
1
µA
1.4
2.3
mA
UNIT
Ven-pass
Pass-Through Mode Threshold
(3)
Rising
2.19
2.4
2.56
V
Vmode-hyst
Mode change hysteresis, falling (3)
Falling
65
107
165
V
V
Ven-shutdown
Shut-down Mode Threshold
(3)
Falling
0.2
0.4
0.59
Ven-boost
Boost Mode Enable Window (3)
Rising
0.65
1.22
1.6
Ien
EN/MODE pin bias current
(4)
EN/MODE = 1.6V
VSENSE
Cycle-by-Cycle Current Limit
Threshold during boost mode
EN/MODE = 1.6V
FB = 50V
ΔVSC
Short Circuit Current Limit
Threshold during boost mode
EN/MODE = 1.6 V, FB = 0 V
VSL
Internal Ramp Compensation
Voltage
VLIM1
Input Current Limit Threshold
Voltage in Pass-Through mode
during TLIM1 (3)
EN/MODE = 2.6V
70
85
95
mV
ΔVLIM2
Input Current Limit Threshold
Voltage in Pass-Through mode
during TLIM2 (3)
EN/MODE = 2.6V
14.5
18
21
mV
TLIM1
Curent Limit Time at TLIM1 (3)
900
µs
TLIM2
Current Limit Time at TLIM2 (3)
3.6
ms
TSC
Current Limit Time at TSC (3)
±1.0
V
µA
142
170
182
mV
18
30
42
mV
90
mV
900
µs
Upper Output-Over Voltage
Protection Threshold
Rising threshold measured at FB pin with
respect to FB pin,
VCOMP = 1.45V
40
mV
Lower Output-Over Voltage
Protection Threshold
Falling threshold measured at FB pin with
respect to FB pin,
VCOMP = 1.45V
26
mv
4.9
V
VOVP
(5)
VGS-on
On State Drive voltage at VG pin
VGS-off
Off State Drive voltage at VG pin (6)
Vin = 5V, ISEN = VIN – 200mV
IG = 0A
IG
Maximum Drive current at VG pin
VIN = 5V, ISEN = 5V
VG = VIN
Gm
Error Amplifier Transconductance
VCOM = 1.4 V, ICOMP = ±50µA
340
522
900
µA/V
AVOL
Error Amplifier Open Loop Voltage
Gain
VCOM = 1.2 V to 1.8V, ICOMP = 0A
190
313
450
V/V
RO
Error Amplifier Open Loop Output
Resistance (7)
IEAO
Error Amplifier Output Current
Swings
(3)
(4)
(5)
(6)
(7)
4
VIN = 5V, ISEN = 5V, IG = 0A
3.8
5
mV
20
µA
600
kΩ
SOURCING:
VCOMP = 1.4V, VFB = 1.1V
27
66
115
µA
SINKING:
VCOMP = 1.4V, VFB = 1.4V
49
68
125
µA
See sections on operational modes and short circuit protection.
The bias current flowing through this pin is compensated and can flow either into or out-of this pin.
This is the gate-to-source voltage drive of Q2, when the controller turns on this FET.
This voltage is measured from the VG pin to AGND, when the controller fully turns off Q2.
This parameter is calculated from the error amplified Gm and AVOL, and is not tested.
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ELECTRICAL CHARACTERISTICS (continued)
Limits in standard type are for TJ = 25°C only; limits apply over the junction temperature (TJ) range of –40°C to +125°C.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 12V.
SYMBOLS
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
VEAO
Error Amplifier Output Voltage
Limits
UPPER: VFB = 0V, COMP pin floating
Tr
Drive Pin Rise Time
Cload = 3nF, VDR = 0V to 3V
Tf
Drive Pin Fall Time
Cload = 3nF, VDR = 3V to 0V
25
ns
TSD
Thermal Shutdown Threshold
165
°C
TSD-hyst
Thermal Shutdown Threshold
Hysteresis
10
°C
θJA
Thermal Resistance from Junction
to Ambient
36
°C/W
LOWER: VFB = 1.4V
10-Lead QFN LEK10A
2.3
UNIT
V
25
ns
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V
0.82
5
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, VIN = 12V, TJ = 25°C, circuit of Figure 29
Switching Frequency vs Temperature
650
Supply current in Pass-through Mode (IG-pass)
1.6
8V
12V
SUPPLY CURRENT (mA)
640
FREQUENCY (kHz)
630
620
610
600
590
580
570
-40°C
27°C
90°C
1.4
1.2
1.0
560
550
0.8
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
80 100
4
6
8
10 12 14
INPUT VOLTAGE (v)
Figure 1.
140
3.8
MINIMUM ON-TIME (ns)
SUPPLY CURRENT (mA)
Minimum On-Time vs Temperature
145
-40°C
27°C
90°C
3.6
3.4
3.2
135
130
125
120
115
110
3.0
4
6
8
10 12 14
INPUT VOLTAGE (V)
16
18
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
Figure 3.
PASS FET GATE-SOURCE VOLTAGE (V)
CURRENT LIMIT TIMING (ms)
Pass FET Drive Voltage vs Input Voltage (VGS-on)
TLIM1
TLIM2
4.5
80 100
Figure 4.
Current Limit Timing vs Temperature
5.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
80 100
Figure 5.
6
18
Figure 2.
Supply Current in Boost Mode (IQ-boost)
4.0
16
6.5
-40°C
27°C
90°C
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
4
5
6
7 8 9 10 11 12 13 14
INPUT VOLTAGE (V)
Figure 6.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, VIN = 12V, TJ = 25°C, circuit of Figure 29
Pass FET Drive Current vs Temperature
PASS FET GATE DRIVE CURRENT ( A)
35
VCC Voltage vs Input Voltage
6.2
VIN = 12V
-40°C
27°C
90°C
6.0
30
5.8
VCC (V)
25
20
5.6
5.4
5.2
15
5.0
10
4.8
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
80 100
2
3
4
5 6 7 8 9 10 11 12
INPUT VOLTAGE (V)
Figure 7.
Figure 8.
Load Regulation
0.25
98
0.20
96
0.15
94
0.10
ûVOUT(%)
EFFICIENCY (%)
Efficiency, VOUT = 15 V
100
92
90
0.05
0.00
-0.05
88
-0.10
86
-0.15
84
8Vin
10Vin
12Vin
82
80
-0.20
-0.25
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT CURRENT (A)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT CURRENT (A)
Figure 9.
Figure 10.
Line Regulation
Startup Waveforms, VIN = 8 V
0.25
0.1A output current
0.5A output current
1A output current
0.20
0.15
VO
5V/Div
0.10
ûVOUT(%)
8Vin
10Vin
12Vin
EN
500 mV/Div
0.05
0.00
-0.05
-0.10
IO
200 mA/Div
-0.15
-0.20
-0.25
8
9
10
11
INPUT VOLTAGE (V)
TIME (5 ms/DIV)
12
Figure 11.
Figure 12.
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FUNCTIONAL BLOCK DIAGRAM
VG
ISEN
VIN
Ramp Adjust
-
+
200 mV
+
Pass
Control
Current
Sense
Amp.
-
A
Internal
Reg
Short-circuit
Comparator
+
Limit
References
Charge
Pump
VCC
Limit
-
Level
Shifter
1.27V
Reference
Soft
Start
+
PWM
-
+
-
Drive
Logic
DR
+
E.A.
-
EN/MODE
Logic
Internal Slope
Compensation
OSC
OVP
FB
EN/MODE
COMP
AGND
PGND
FUNCTIONAL DESCRIPTION
The LM3017 uses a fixed frequency, Pulse Width Modulated (PWM), current mode control architecture. A highside current sense amplifier provides inductor current information by sensing the voltage drop across RSEN. The
voltage across this resistor is fed into the ISEN pin. This voltage is then level shifted and fed into the positive input
of the PWM comparator. As with all architectures of this type, a compensation ramp is required to ensure stability
of the current control loop under all operating conditions. A nominal value of the ramp is provided internally while
additional ramp can be added through the ISEN pin. The output voltage is sensed through an external feedback
resistor divider network and fed into the error amplifier (EA) negative input (feedback pin, FB). The output of the
error amplifier (COMP pin) is added to the slope compensation ramp and fed into the negative input of the PWM
comparator.
At the start of any switching cycle, the oscillator sets a high signal on the DR pin (gate of the external MOSFET)
and the external MOSFET turns on. When the voltage on the positive input of the PWM comparator exceeds the
negative input, the Drive Logic is reset and the external MOSFET turns off.
Under extremely light load or no-load conditions, the energy delivered to the output capacitor when the external
MOSFET is on during the minimum on time is more than what is delivered to the load. An over-voltage
comparator inside the LM3017 prevents the output voltage from rising under these conditions by sensing the
feedback (FB pin) voltage and resetting the RS latch. The latch remains in a reset state until the output decays to
the nominal value. Thus the operating frequency decreases at light loads, resulting in excellent efficiency.
8
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TRUE SHUTDOWN
The LM3017 incorporates circuitry to control a high side NMOS transistor in series with the inductor. This feature
is used to dis-connect the load from the input supply and protect the system from shorts on the output. Using an
NMOS, rather than a PMOS transistor, saves the use of a diode from the inductor to ground. When the NMOS is
turned-off, the inductor brings the source belowground, keeping it on until the current is safely brought to zero. A
built-in charge pump supplies typically VIN+5V to drive the gate of this NMOS.
OPERATION OF THE EN/MODE PIN
The EN/MODE pin is used to control the modes of the regulator by driving the high side gate (VG pin) to enable
or disable the output through the pass MOSFET. Furthermore it defines the current limit for each operation mode
(see next section). The following table shows the modes versus the voltage on the EN/MODE pin:
EN/MODE PIN VOLTAGE
MODE
≤ 0.4V
Shutdown
1.6 V to 2.2 V
Boost
≥2.6 V
Pass-through
Figure 13 shows the output voltage behavior in the various operation modes.
SHUTDOWN MODE
Pulling the EN/MODE pin to less than 0.4V (typ.), during any mode of operation, will place the part in full
shutdown mode. The boost regulator and the pass FET will be off and the load will be disconnected from the
input supply. In this mode, the regulator will draw a maximum of 1µA from the input supply.
BOOST MODE
The boost regulator can be turned on by bringing the EN/MODE pin to greater than 1.6V, but less than 2.2V.
This is the run mode for the boost regulator. Note that the LM3017 will always start in pass-through and transition
to boost mode.
STANDBY MODE
Setting the EN/MODE pin to greater than 2.6V (typ.), will place the part in pass-through mode. The boost
regulator will be off and the pass MOSFET will be on. During this mode, the load is connected to the input supply
through the inductor and power diode, and is fully protected from output short circuits.
EN/MODE CONTROL
As stated previously, the EN/MODE pin controls the state of the LM3017. As with any digital input , the voltage
on this pin must not be allowed to slowly cross the various thresholds. Although hysteresis is used on this input,
slowly varying signal may cause unpredictable behavior. Also, the EN/MODE pin must not be allowed to float.
One way to control the LM3017, from digital logic, is to use the circuit shown in Figure 14. The resistor values
are adjusted based on the above table and the logic supply used. The MOSFET can be any small signal device,
such as the 2N7002.
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EN/MODE
> 2.6V
1.6V < EN/MODE <2.2V
< 0.4V
Pass-through
Pass On
Boost Off
Shut-down
mode
Boost On
Pass-through
Pass On
Boost Off
Boost On
Pass-through
Pass On
Boost Off
Shut-down
mode
Output Voltage
Vout
Vin
0V
Pass-through
Pass On
Boost Off
Shut-down
mode
Shut-down
mode
Figure 13. Typical EN/MODE Operation
3.3V Logic
LM3017
11 k:
A
EN/MODE
REN1
REN2
µC
22 k:
B
Figure 14. Typical EN/MODE Control Circuit
10
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CURRENT LIMIT AND SHORT CIRCUIT PROTECTION
Boost Mode
The LM3017 implements current limit protection by controlling the pass FET, Q2.
In boost mode the LM3017 features both cycle-by-cycle current limit and short circuit protection. Unlike most
boost regulators, the LM3017 can protect itself from short circuits on the output by shutting off the pass FET. The
boost current limit, defined by VCL=170mV in the electrical characteristics table, turns off the boost FET for
normal overloads on a cycle-by-cycle basis. The current is limited to VCL/RSEN until the overload is removed.
Should the output be shorted, or otherwise pulled below VIN, the inductor current will have a tendency to “runaway”. This is prevented by the short circuit protection feature, defined as VSC = 200mV in the electrical
characteristics table. When this current limit is tripped, the current is limited to VSC/RSEN by controlling the pass
FET. If the short persists for TSC > 450µs the pass FET will be latched off. In this way, the current is limited to
VSC/Rsen until the short is removed or the time of TSC = 450µs is completed. Pulling the EN/MODE pin low
(<0.4V, typ) is required to reset this short circuit latch-off mode. The delay of TSC = 450µs helps to prevent
nuisance latch-off during a momentary short on the output.
Start-up Boost Mode
During start-up in boost mode, peak inductor current may be higher compared to normal operation. To allow for
this, current limit levels and timing are different during startup. The current limit is defined by VLIM2 = 100mV
(typ.) in the electrical characteristics table, for the first TLIM2 = 3.6ms (typ.). The current is limited to VLIM2/RSEN,
for this period . Once the TLIM2 = 3.6ms (typ.) timer has finished, the current limit is increased to VSC = 200mV
(typ.). For the first TLIM2 = 3.6ms (typ.) of the start-up, the latch-off feature is not enabled, however the current will
always be limited to VLIM2/RSEN. This allows the part to start-up normally. If the current limit is still tripped at the
end of TLIM2 = 3.6ms (typ.) , the TSC = 900µs (typ.) timer is started. Once the TSC = 900µs (typ.) time has expired,
the pass FET (Q2) is latched off. This gives a total current-limited time of TSC + TLIM2 = 4.05ms (typ.), in cases
where the LM3017 is started into a short circuit at the output.
Pass-Through Mode
In pass-through mode the power path is protected from shorts and overloads by the current limit defined as VLIM1
= 85mV (typ.) in the electrical characteristics table. When this current limit is tripped, the current is limited to
VLIM1/RSEN by controlling the pass FET. If the short persists for TLIM1 > 900µs (typ.) the pass FET (Q2) will be
latched off. In this way, the current is limited to VLIM1/RSEN until the short is removed or the time of TLIM1 = 900µs
(typ.) is completed. Pulling the EN/MODE pin low (0.4V, typ.) is required to reset this latch-off mode.
Start-up Pass-Through Mode
During start-up in pass mode, the current limit is defined by VLIM2 = 100mV (typ.) in the electrical characteristics
table, for the first TLIM2 = 3.6ms (typ.). The current is limited to VLIM2/RSEN, for this period . Once the TLIM2 =
3.6ms (typ.) timer has finished, the current limit is reduced to VLIM1 = 85mV (typ.). For the first TLIM2 = 3.6ms
(typ.) of the start-up, the latch-off feature is not enabled, however the current will always be limited to VLIM2/RSEN.
This higher limit allows the part to start-up normally. If the current limit is still tripped at the end of TLIM2 = 3.6ms
(typ.), the TLIM1 = 900µs (typ.) timer is started. Once the TLIM1= 900µs time has expired, the pass FET(Q2) is
latched off. This gives a total current-limited time of TLIM1+ TLIM2 = 4.5ms (typ.), in cases where the LM3017 is
started into a short circuit at the output.
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Figure 15. REPLACE THIS FIGURE. Current Limit/Short Circuit Protection
OVER VOLTAGE PROTECTION
The LM3017 incorporates output over-voltage protection (OVP). At light, or no load the minimum switch on-time
may not be short enough to allow regulation in constant frequency PWM mode. In these cases the output voltage
(and therefore the voltage on the FB pin) will try to rise. When the voltage on the FB pin reaches approximately
20mV higher than the regulation point, the power switch (Q1) is turned off. Q1 will remain off until the FB voltage
drops back to the regulation point, at which time normal switching will begin again. In this way the LM3017 will
prevent the output voltage from rising too high with no load on the output.
12
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APPLICATION INFORMATION
he LM3017 may be operated in either continuous or discontinuous conduction mode. The following descriptions
assume continuous conduction operation (CCM). This mode of operation has higher efficiency and lower EMI
characteristics than the discontinuous mode.
BOOST CONVERTER
The most common topology for the LM3017 is the boost or step-up topology. The boost converter converts a low
input voltage into a higher output voltage. The basic configuration for a boost regulator is shown in Figure 16. In
continuous conduction mode (when the inductor current never reaches zero at steady state), the boost regulator
operates in two cycles. In the first cycle of operation, MOSFET Q is turned on and energy is stored in the
inductor. During this cycle, diode D1 is reverse biased and load current is supplied by the output capacitor,
COUT.
In the second cycle, MOSFET Q is off and the diode is forward biased. The energy stored in the inductor is
transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The
output voltage is defined as:
V
V
VOUT = IN ; D = 1 - IN
1- D
VOUT
including the voltage drop of the diode:
V
- VIN + VD1
V
VOUT +VD1 = IN ; D = OUT
1- D
VOUT + VD1
where D is the duty cycle of the switch, VD1 is the forward voltage drop of the diode. The following sections
describe selection of components for a boost converter.
L
VIN
D1
+
+
Q
PWM
(a)
L
VOUT
COUT
VOUT
+
+
COUT
-
VIN
+
RLOAD
-
(b)
L
+
-
VIN
D1
VOUT
+
COUT
+
RLOAD
-
Figure 16. 4 Simplified Boost Converter Diagram (a) First cycle of operation. (b) Second cycle of
operation
Programming the Output Voltage
The output voltage can be programmed using a resistor divider between the output and the feedback pins, as
shown in Figure 19. The resistors are selected such that the voltage at the feedback pin is equal to VFB (refer to
Electrical Characteristic). RFBT and RFBB can be selected using the equation,
æ R
VOUT = VFB ´ ç 1 + FBT
ç R
FBB
è
ö
÷
÷
ø
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25
MAXIMUM OUTPUT VOLTAGE (V)
MAXIMUM OUTPUT VOLTAGE (V)
140
120
100
80
60
40
20
20
15
10
5
5 6
7
8
9 10 11 12 13 14 15 16 17 18
5 6
INPUT VOLTAGE (V)
7
8
9 10 11 12 13 14 15 16 17 18
INPUT VOLTAGE (V)
Figure 17. Maximum Output Voltage
Figure 18. Minimum Output Voltage
Figure 17 shows maximum regulated output voltage based on maximum duty cycle value of 85% and by
assuming a voltage drop on the output diode of 0.5V and 90% efficiency. Figure 18 shows the minimum
regulated output voltage, the calculation is based on minimum on time of 126ns (typ.) that generates a minimum
duty cycle equal to:
DMIN = tON(min) × fS = 0.076
where fS is the switching frequency and it equal to 600kHz and by assuming 90% efficiency.
Power Inductor Selection
The inductor is one of the two energy storage elements in a boost converter.
Choose the minimum IOUT to determine the minimum inductance L. A common choice is to set (2 x ΔiL) from 30%
to 50% of IL. Choosing an appropriate core size for the inductor involves calculating the average and peak
currents expected through the inductor. In a boost converter the inductor current IL, the peak of the inductor
current and the inductor current ripple ΔiL are equal to:
I
IL = OUT
1- D
ILpeak = IL (max) + DiL (max)
D ´ VIN
DiL =
2 ´ L ´ fS
The inductance used is a tradeoff between size and cost. Larger inductance means lower input ripple current,
however because the inductor is connected to the output during the off-time only, there is a limit to the reduction
in output voltage ripple. Lower inductance results in smaller, less expensive magnetics.
All the analysis in this datasheet assumes operation in continuous conduction mode. To operate in continuous
conduction mode, the following conditions must be met:
IL = DiL
IOUT
D ´ VIN
=
1 - D 2 ´ fS ´ L
L³
14
(1 - D )´ D ´ VIN
2 ´ fS ´ IOUT
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A core size with ratings higher than these values should be chosen. If the core is not properly rated, saturation
will dramatically reduce overall efficiency or damage the power stage. Choose an inductor with a saturation
current value higher than ILpeak. The LM3017 senses the peak current through the switch. The peak current
through the switch is the same as the peak current calculated above.
Losses due to DCR of the inductance can be easily calculated as:
2
éæ I
Di2 ù
ö
PL = DCR ´ êç OUT ÷ + L ú
12 ú
êè 1 - D ø
ë
û
No core losses have been considered.
Setting the Output Current
The maximum amount of current that can be delivered at the output can be controlled by the sense resistor,
RSEN. Current limit occurs when the voltage that is generated across the sense resistor equals the current sense
threshold voltage, VSENSE. Limits for VSENSE have been specified in the electrical characteristics section. This can
be expressed as:
Isw(peak) × RSEN = VSENSE
The peak current through the switch is equal to the peak inductor current:
Isw(peak) = IL(max) + ΔiL
Therefore for a boost converter:
I
D ´ VIN
= OUT +
ISW
peak
1 - D 2 ´ fS ´ L
Combining the two equations yields an expression for RSEN and includes a 20% margin on the peak of the
switching current:
VSENSE
RSEN =
æI
D ´ VIN ö
1.2 ´ ç OUT +
÷
´ fS ´ L ø
1
D
2
è
Evaluate RSEN at the maximum and minimum VIN values and choose the smallest RSEN calculated.
VIN
RSEN
L1
Q2
D1
VOUT
+
ISEN
VG
DR
Q1
COUT
RFBT
LM3017
FB
RFBB
Figure 19. Adjusting the Output Voltage
Additional Slope Compensation
It is good design practice to only add as much slope compensation as needed to avoid instability. Additional
slope compensation (see Figure 23) minimizes the influence of the sensed current in the control loop. With very
large slope compensation the control loop characteristics are similar to a voltage mode regulator which compares
the error voltage to a saw tooth waveform rather than the inductor current. It is possible to calculate the minimum
value of RS in order to meet the equation (see CONTROL LOOP COMPENSATION IN DETAIL section):
MC > M2/2
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Hense:
RS ³
ù
1 é RSEN ´ (VOUT - VIN (min) )
´ê
- VSL ú
K ëê
2 ´ L ´ fS
ûú
Where K = 40 µA.
If the result of the previous equation is negative it means that no additional slope compensation is needed,
anyway a 100Ω resistor is recommended. For details see SLOPE COMPENSATION RAMP section.
Current Limit with Additional Slope Compensation
If an external slope compensation resistor is used then the internal control signal will be modified and this will
have an effect on the current limit.
If RS is used, then this will add to the existing slope compensation. The command voltage, VCS, will then be given
by:
VCS = VSL + ΔVSL
Where VSENSE is a defined parameter in the electrical characteristics section, VSL is the amplitude of the internal
compensation ramp and ΔVSL = RS x K is the additional slope compensation generated as discussed in the
SLOPE COMPENSATION RAMP section. This changes the equation for RSEN to:
V
- D ´ VCS
RSEN = SENSE
æ IOUT
D ´ VIN ö
+
ç
÷
è 1 - D 2 ´ fS ´ L ø
Note that since ΔVSL = RS x K as defined earlier, RS can be used to provide an additional method for setting the
current limit. In some designs RS can also be used to help filter noise to keep the ISEN pin quiet. Dissipation due
to RSEN resistor is equal to:
2
2 ù
éæ I
DiLpp
ö
ú
PSEN = RSEN ´ êç OUT ÷ +
12 ú
êè 1 - D ø
ë
û
Power Diode Selection
Observation of the boost converter circuit shows that the average current through the diode is the average output
current, and the peak current through the diode is the peak current through the inductor. The peak diode current
can be calculated using the formula:
ID(Peak) = [IOUT/ (1−D)] + ΔiL
The peak reverse voltage for a boost converter is equal to the regulator output voltage. The diode must be
capable of handling this peak reverse voltage as well as the output rms current. To improve efficiency, a low
forward drop Schottky diode is recommended due to low forward drop and near-zero reverse recovery time. The
overall efficiency becomes more dependent on the selection of D at low duty cycles, where the boost diode
carries the load current for an increasing percentage of the time. This power dissipation can be calculated by
checking the typical diode forward voltage VD, from the I-V curve on the diode's datasheet and the multiplying it
by IO. Diode data sheets will also provide a typical junction-to-ambient thermal resistance, θJA, which can be
used to estimate the operating die temperature of the Schottky. Multiplying the power dissipation (PD = IO x VD)
by θJA gives the temperature rise. The diode case size can then be selected to maintain the Schottky diode
temperature below the operational maximum.
Low Side MOSFET Selection (switching MOSFET)
The drive pin, DR, of the LM3017 must be connected to the gate of an external MOSFET. In a boost topology,
the drain of the external N-Channel MOSFET is connected to the inductor and the source is connected to the
ground. The drive pin voltage, VDR, depends on the input voltage (see typical performance characteristics).
The selected MOSFET directly affects the efficiency. The critical parameters for selection of a MOSFET are:
1. Minimum threshold voltage, VTH(MIN)
2. On-resistance, RDS(ON)
3. Total gate charge, Qg
4. Reverse transfer capacitance, CRSS
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5. Maximum drain to source voltage, VDS(MAX)
The off-state voltage of the MOSFET is approximately equal to the output voltage. VDS(MAX) of the MOSFET must
be greater than the output voltage plus the voltage drop across the output diode (20% margin recommended).
The power losses in the MOSFET can be categorized into conduction losses, gate charging losses and switching
losses. RDS(ON) is needed to estimate the conduction losses. The conduction loss, PCOND, is the I2R loss across
the MOSFET. The maximum conduction loss is given by:
2
æ I
ö
PCOND = ç OUT ÷ ´ DMAX ´ RDS(on)
è 1 - DMAX ø
where DMAX is the maximum duty cycle.
V (min)
DMAX = 1 - IN
VOUT
To take in account the increase in MOSFET on resistance due to heating, a factor of 1.3 is introduced, hence:
PCOND_real = PCOND(max) x 1.3
Gate charging loss, PG, results from the current required to charge and discharge the gate capacitance of the
power MOSFET and is approximated as:
PG = VCC x QG fS
QG is the total gate charge of the MOSFET. Gate charge loss differs from conduction and switching losses
because the actual dissipation occurs in the LM3017 and not in the MOSFET itself. This loss, PVCC, is estimated
as:
PVCC = (VIN – VCC) x QG x fS
The switching losses are very difficult to calculate due to changing parasitics of a given MOSFET in operation.
Often, the individual MOSFET datasheet does not give enough information to yield a useful result. The following
formulas give a rough idea how the switching losses are calculated:
I ´ VOUT
´ fS ´ (tLH + tHL )
PSW = L
2
Where tLH and tHL are rise and fall times of the MOSFET.
Pass MOSFET Selection (High Side MOSFET)
The VG pin drives the gate of the high side MOSFET (Pass FET Q2). This requires special considerations. When
the output is shorted, this FET must sustain the full input voltage and the short circuit current simultaneously.
This is due to the fact that the controller regulates the short circuit current in a quasi-linear manner, through Q2.
This power pulse will only last for TLIM2 or TSC, depending on the operational mode. Therefore, the designer must
carefully examine the SOA curve for the desired FET before committing to the design. The following equations
give the maximum energy pulses that Q2 is required to survive:
æV
ö
E1 ³ (Vin + 2 )´ ç LIM2 ÷ ´ TLIM2
è Rsen ø
æV ö
E2 ³ (Vin + 2 )´ ç SC ÷ ´ TSC
è Rsen ø
These two energy points must fall within the SOA of the selected FET. In addition, Q2 should have a low
threshold voltage and low RDS(on) for high efficiency. Power dissipation during boost mode is given by:
2
2 ù
éæ I
DiLpp
ö
ú
PQ2 = RDS(on) ´ êç OUT ÷ +
12 ú
êè 1 - D ø
ë
û
Input Capacitor Selection
Due to the presence of an inductor at the input of a boost converter, the input current waveform is continuous
and triangular. The inductor ensures that the input capacitor sees fairly low ripple currents. However, as the input
capacitor gets smaller, the input ripple goes up. The rms current in the input capacitor is given by:
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ICIN (rms) =
DiL
3
=
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(VOUT - VIN )´ VIN
12 ´ VOUT ´ fS
The input capacitor must be capable of handling this rms current. Although the input capacitor is not as critical in
a boost application, low values can cause impedance interactions. Therefore a good quality capacitor should be
chosen in the range of 10 µF to 20 µF. Furthermore, a low ESR 0.1µF ceramic bypass capacitor is
recommended in order to avoid transients and ringing due to parasitics. Bypass capacitors must be placed as
close as possible to the VIN pin and grounded close to the GND pin on the IC to minimize additional ESR and
ESL. The following formula can be used to define the input voltage ripple:
DVipp
æ
ö
1
= DiLPP ´ ESR + ç
÷
è 8 ´ fS ´ Ci ø
2
2
Where ΔiLpp = 2 x ΔiL is the peak-to-peak inductor current ripple and ΔVipp is the peak-to-peak input voltage
ripple. Many times it is necessary to use an electrolytic capacitor on the input in parallel with the ceramics. The
ESR of this capacitor can help to damp any ringing on the input supply caused by long power leads.
Output Capacitor Selection
The output capacitor in a boost converter provides all the output current when the inductor is charging and it
determines the steady state output voltage ripple ΔVOpp. As a result it sees very large ripple currents. The output
capacitor should be selected based on its capacitance CO, its equivalent series resistance ESR and its RMS
current rating. The rms current in the output capacitor is:
é
DiL2 úù
D
2
IC OUT (rms) = (1 - D) ´ êIOUT
´
+
ê
(1 - D )2 3 úû
ë
Where ΔiL is the inductor ripple current and D is the duty cycle.
The magnitude of the output voltage ripple during the on-time is equal to the ripple voltage during the off-time
and it is composed of two parts. For simplicity the analysis will be performed for off-time only.
The first part of the ripple voltage is the surge created as the output diode D turns on. At this point inductor/diode
current is at the peak value, and the ripple voltage increase can be calculated as:
ΔVO1 = IPK x ESR
Where IPK = IOUT/ (1−D).
The second portion of the ripple voltage is the increase due to the charging of CO through the output diode. This
portion can be approximated as:
ΔVO2 = (IO / CO) x (D / fS)
The following formula can be used to define the output voltage ripple:
´D
æI
ö I
DVOpp = ESR ´ ç OUT + DiL ÷ + OUT
1
D
C
´
è
ø
o fS
The ESR of the output capacitor(s) has a strong influence on the slope and direction of the output voltage ripple.
Capacitors with high ESR such as tantalum and aluminum electrolytic create an output voltage ripple that is
dominated by ΔVO1 with a shape shown in Figure 20. Ceramic capacitors, in contrast, have a very low ESR and
lower capacitance and the shape of the output voltage ripple is dominated by ΔVO2 with a shape shown in
Figure 21.
18
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PsOpp
VOUT
VOUT
PsOpp
ID
ID
Figure 20. ΔVOpp Using High ESR Capacitors
Figure 21. ΔVOpp Using Low ESR Capacitors
Ceramic capacitors are recommended with a typical value between 10µF and 100µF. The minimum quality
dielectric that is suitable for switching power supply output capacitors is X5R, while X7R (or better) is preferred.
Careful attention must be paid to the DC voltage rating and case size, as ceramic capacitors can lose 60% or
more of their rated capacitance at the maximum DC voltage. This is the reason that ceramic capacitors are often
de-rated to 50% of their capacitance at their working voltage.
VCC Decoupling Capacitor
The internal bias of the LM3017 comes from either the internal bias voltage generator as shown in the block
diagram or directly from the voltage at the VIN pin. At input voltages lower than 6V the internal IC bias is the
input voltage and at voltages above 6V the internal bias voltage generator of the LM3017 provides the bias. A
good quality ceramic bypass capacitor must be connected from the VCC pin to the PGND pin for proper
operation. This capacitor supplies the transient current required by the internal MOSFET driver, as well as
filtering the internal supply voltage for the controller. A value of between 0.47µF and 4.7µF is recommended.
Thermal Considerations
The majority of power dissipation and heat generation comes from FETs and diode. Selecting MOSFETs with
exposed pads will aid the power dissipation of these devices. Careful attention to RDS(on) at high temperature
should be observed. Diode data sheets will provide a typical junction-to-ambient thermal resistance θJA, which
can be used to estimate the operating die temperature of the Schottky. Multiplying the power dissipation by θJA
gives the temperature rise. The diode case size can then be selected to maintain the Schottky diode temperature
below the operational maximum. Larger case sizes generally have lower θJA and lower forward voltage drop.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the LM3017 in the event that the maximum junction
temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power standby
state, disabling the output driver and the VCC regulator. After the temperature is reduced (typical hysteresis is
10°C) the VCC regulator will be re-enabled and the LM3017 will perform a soft-start.
SLOPE COMPENSATION RAMP
The LM3017 uses a current mode control scheme. The main advantages of current mode control are inherent
cycle-by-cycle current limit for the switch, simpler control loop characteristics and excellent line and load transient
response. However there is a natural instability due to sub-harmornic oscillations that will occur for duty cycles,
D, greater than 50% if slope compensation is not addressed.
MC > M2/2
For best input noise immunity:
MC = M2
For best sub-harmonic suppression:
MC = M2/2
Where:
• MC is the slope of the compensation ramp.
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•
•
•
•
•
•
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M1 is the slope of the inductor current during the ON time.
M2 is the slope of the inductor current during the OFF time.
RSEN is the sensing resistor value.
VOUT represents the output voltage.
VIN represents the input voltage.
A is equal to 0.86 and it is the internal sensing amplification of the LM3017.
In the case of the boost topology:
M1 = [VIN / L] × RSEN × A
M2 = [(VOUT – VIN) / L] × RSEN × A
The compensation ramp has been added internally in the LM3017. The slope of this compensation ramp has
been selected to satisfy most applications, and its value depends on the switching frequency. This slope can be
calculated using the formula:
MC = VSL × fS
In the above equation, VSL is the amplitude of the internal compensation ramp and fS is the controller's switching
frequency. Limits for VSL have been specified in the electrical characteristics section.
In order to provide the user additional flexibility, a patented scheme has been implemented inside the IC to
increase the slope of the compensation ramp externally, if the need arises. Adding a single external resistor, RS
(as shown in Figure 23) increases the amplitude of the compensation ramp as shown in Figure 22.
Control Signal
Compensation Ramp
with RSL
Control Signal
Compensation Ramp
without RSL
'VSL
-MC
VSL
Figure 22. Additional Slope Compensation Added Using External Resistor RS
Where,
ΔVSL = K × Rs
K = 40 µA typically and changes slightly as the switching frequency changes.
A more general equation for the slope compensation ramp, MC, is shown below to incluse ΔVSL cause by the
resistor Rs.
MC = (VSL + ΔVSL) × fs
RSEN
VIN
CS
L1
Q2
RS
ISEN
VG
DR
LM3017
Figure 23. Increasing the Slope of the Compensation Ramp
An additional capacitor CS could be added if the sensing signal generated by RSEN is very noisy (parasitic circuit
capacitance, inductance and gate drive current create a spike in the current sense voltage at the point where Q1
turns on.) The time constant RSEN x CS should be long enough to reduce the parasitics spike without significantly
affecting the shape of the actual current sense voltage (a typical range is from 100pF to 2.2nF).
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CONTROL LOOP COMPENSATION IN DETAIL
The LM3017 uses peak current-mode PWM control to correct changes in output voltage due to line and load
transients. Peak current-mode provides inherent cycle-by-cycle current limiting, improved line transient response,
and easier control loop compensation. The control loop is comprised of two parts. The first is the power stage,
which consists of the pulse width modulator, output filter, and the load. The second part is the error amplifier.
Figure 24 shows the regulator control loop components.
L
RSEN
+
D
VIN
CO
RO
+
ESR
RFBT
-
+
A
+
-
Current
Sense
Amp.
+
CCOMP
CCOMP2
RFBB
+ V
REF
-
RCOMP
Figure 24. Power Stage and Error Amp
The power stage in a CCM peak current mode boost converter consists of the DC gain, GVC0, a single low
frequency pole, fP, the ESR zero, fZ, a right-half plane zero, fR, and a double pole resulting from the sampling of
the peak current. The power stage transfer function (also called the Control-to-Output transfer function) can be
written:
æ
s öæ
s ö
ç1 ÷ ç1 +
÷
wR ø è
wZ ø
è
GVC (s) = GVC0 ´
æ
s öæ
s
s2
+ 2
ç1 +
÷ çç 1 +
wP ø è
wn wn
è
ö
÷
÷
ø
The DC gain is defined as:
RO (1 - D)
GVC0 =
2 ´ A ´ RSEN
Where: RO = VOUT / IOUT
In the equation for GVC0, DC gain is highest when input voltage and output current are at the maximum. The
system ESR zero is:
wZ
1
=
fZ =
2p 2p ´ CO ´ ESR
The low frequency pole is:
w
2
fP = P =
2p 2p ´ CO ´ (ESR + RO )
The right-half plane zero is:
2
RO ´ (1 - D )
w
fR = R =
2p
2p ´ L
The sampling double pole quality factor is:
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Qn =
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1
é
ù
æ M ö
p ´ ê(1 - D )´ ç 1 + C ÷ - 0.5 ú
M1 ø
êë
úû
è
The sampling double corner frequency is: ωn = π x fS
The natural inductor current slope is: M1 = RSEN x VIN / L
The external ramp slope is: MC = (VSL + ΔVSL) x fS
A step-up converter produces an undesirable right-half plane zero in the regulation feedback loop. This requires
compensating the regulator such that the crossover frequency occurs well below the frequency of the right-half
plane zero
COMPENSATION NETWORK COMPONENTS CALCULATIONS
As shown in Figure 24, the LM3017 uses a compensation network base on a transconductance amplifier. The
closed loop transfer function is defined as:
T(s) = GVA(s) × GVC(s)
Where GVA(s) is the transfer function implemented by the compensation network:
æ
s ö
wP1 ç 1 +
÷
w
Z1 ø
è
GVA (s) =
æ
s ö
s ç1 +
÷
wP2 ø
è
wZ1 =
1
CCOMP ´ RCOMP
RFBB
RFBB + RFBT
CCOMP + CCOMP2
Gm ´
wP1 =
wP2 =
CCOMP + CCOMP2
CCOMP ´ CCOMP2 ´ RCOMP
To stabilize the regulator, ensure that the regulator crossover frequency is less than or equal to one-fifth of the
right-half plane zero:
f
fC £ R
5
To determine the crossover frequency it is important to note that, at that frequency, the compensation impedance
(ZCOMP) is dominated by a resistor, and the output impedance (ZOUT) is dominated by the impedance of an output
capacitor. Therefore, when solving for the crossover frequency, the equation (by definition of the crossover
frequency) of the loop gain is simplified to:
V
V
1
1
| T |= FB ´ IN ´ Gm ´
´ RCOMP ´
=1
VOUT VOUT
2p ´ fC ´ CO
A ´ RSEN
Where:
• |T| is the loop gain magnitude.
• VFB is feedback voltage, 1.275V.
• VOUT is the output voltage.
• VIN is the input voltage
• Gm is the error amplifier transconductance.
• ZCOMP is the impedance of the compensation network from the COMP pin to ground.
• RSEN is the current sensing resistor.
• A is equal to 0.86 and it is the internal sensing amplification of the LM3017.
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CO is the output capacitor value.
Solve for RCOMP:
RCOMP =
2
2p ´ fC ´ CO ´ VOUT
´ A ´ RSEN
VFB ´ VIN ´ Gm
Once the compensation resistor is known, set the zero formed by the compensation capacitor and resistor to
one-fourth of the crossover frequency:
2
CCOMP =
p ´ fC ´ RCOMP
Where CCOMP is the compensation capacitor.
he high frequency capacitor CCOMP2, is chosen to cancel the zero introduced by output capacitance ESR:
ESR ´ CO
CCOMP2 =
RCOMP
For optimal transient performance, RCOMP and CCOMP might need to be adjusted by observing the load transient
response.
For detailed explanation on how to select the right compensation components for a boost topology please see
Application Note 1286 and Application Note 1994.
COMPENSATION DESIGN EXAMPLE
Referring to Figure 29:
input voltage VIN
8 V to 12 V
output voltage VOUT
15 V
output current IOUT
1A
switching frequency fS
600 kHz
duty cycle D (considering losses)
right-half plane zero fR
0.482 with VIN = 8 V
0.223 with VIN = 12 V
136.187 kHz when VIN = 8 V
306.421 kHz when VIN = 12 V
inductor L
4.7 µH
output capacitance CO (consireding derating
due to applied voltage)
33 µF
Figure 25. Control-to-output Transfer Function Bode Plot GVC(s), VIN=8V, VOUT=15V, IOUT=1A
By choosing the crossover frequency as:
fC = 20 kHz = fS / 20 fR / 5
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PARAMETER
CALCULATED
VALUE
ACTUAL VALUE
RCOMP
3.42 kΩ
3.4 kΩ
CCOMP
9.306 nF
10 nF
CCOMP2
96.48 pF
100 pF
Figure 26. GVC(s) and Compensation Network GVA(s) Bode Plots, VIN=8V, VOUT=15V, IOUT=1A
Figure 27. Closed Loop Bode Plot T(s), VIN=8V, VOUT=15V, IOUT=1A
LAYOUT GUIDELINES
Good board layout is critical for switching controllers such as the LM3017. First the ground plane area must be
sufficient for thermal dissipation purposes and second, appropriate guidelines must be followed to reduce the
effects of switching noise. Switch mode converters are very fast switching devices. In such devices, the rapid
increase of input current combined with the parasitic trace inductance generates unwanted voltage noise spikes.
The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may
create electromagnetic interference (EMI), and can also cause problems in device performance. Therefore, care
must be taken in layout to minimize the effect of this switching noise.
FILTER CAPACITORS
Ceramic filter capacitors are most effective when the inductance of the current loops that they filter is minimized.
Place CBYP as close as possible to the VIN and GND pins of the LM3017. Place CVCC next to the VCC and GND
pins of the LM3017 (refer to Figure 29 for designators).
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SENSE LINES
The current sensing circuit in current mode devices can be easily effected by switching noise. This noise can
cause duty cycle jitter which leads to increased spectral noise. RSEN should be connected to the ISEN pin with a
separate trace made as short as possible, it is also recommended to route the trace the connects the VIN pin to
the input voltage as close as possible to RSEN. Route this trace away from the inductor and the switch node
(where D1, Q1, and L1 connect). For the voltage loop, keep RFBB/T close to the LM3017 and run a trace as close
as possible to the positive side of CO. As with the ISEN line, the FB line should be routed away from the inductor
and the switch node. These measures minimize the length of high impedance lines and reduce noise pickup.
COMPACT LAYOUT
The most important layout rule is to keep the AC current loops as small as possible. Figure 28 shows the current
flow of a boost converter. The top schematic shows a dotted line which represents the current flow during onstate and the middle schematic shows the current flow during off-state. The bottom schematic shows the currents
we refer to as AC currents. They are the most critical ones since current is changing in very short time periods.
The dotted line traces of the bottom schematic are the ones to make as short as possible. In a boost regulator
the primary switching loop consists of the output capacitor, diode and MOSFET. Minimizing the area of this loop
reduces the stray inductances and minimizes noise and possible erratic operation (see Figure 28 for a layout
example). The output capacitor(s) should be placed as close as possible to the diode cathode and MOSFET
GND.
GROUND PLANE AND VIAS
A ground plane in the printed circuit board is recommended as a means to connect the quiet end (input voltage
ground side) of the input filter capacitor to the output filter capacitors and the PGND pin of the controller. Connect
all the low power ground connections directly to the regulator AGND. Connect the AGND and PGND pins
together through a copper area covering the entire underside of the device. Place several vias in this underside
copper area to ground plane. If a via is needed to connect the sensing resistor to the ISEN pin, then place that
via in the inner side of the sensing resistor such that no current flow occurs. Place several vias from the ground
side of the output capacitor(s) to ground place, that will minimize the path for AC current. The PGND and AGND
pins have to be connected to the same ground very close to the IC. To avoid ground loop currents attach all the
grounds of the system only at one point.
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SNOSC66C – MARCH 2012 – REVISED MARCH 2013
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Figure 28. Current Flow in a Boost Application (left) and Layout Example (right) (a) top layer (b) bottom layer
26
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APPLICATION CIRCUITS
VIN = 8V to 12V
L1
RSEN
D1
Q2
VOUT = [email protected]
RS
EN/MODE
U1
ISEN
RFBT
VG
EN/MODE
CIN1
VIN
CO1
Q1
DR
CO2
CO3
VCC LM3017
COMP
CBYP
CVCC
CCOMP2
RCOMP
PGND
FB
AGND
RFBB
CCOMP
GND
GND
Figure 29. Example 1A High Efficiency Step-Up (Boost) Converter
Bill of Materials (BOM) LM3017
Designation
Description
Size
Manufacturer Part #
Vendor
CIN1
Cap 22µF 25V X5R
1206
GRM31CR61E226KE15L
Murata
CO1,CO2, CO3
Cap 22µF 25V X5R
1206
GRM31CR61E226KE15L
Murata
CCOMP
Cap 0.022µF
0603
C0603C103J1RACTU
Kemet
CCOMP2
Cap 1000pF
0603
C1608C0G1H101J
TDK
CBYP
Cap 0.1µF 25V X7R
0603
06033C104KAT2A
AVX
CVCC
Cap 0.47μF 16V X7R
0805
C2012X7R1C474K
TDK
RCOMP
RES, 3.4k ohm, 1%, 0.1W
0603
CRCW06033K40FKEA
Vishay
RFBT
RES, 21.5k ohm, 1%, 0.1W
0603
CRCW060321K5FKEA
Vishay
RFBB
RES, 2k ohm, 1%, 0.1W
0603
CRCW06032K00FKEA
Vishay
RS
RES, 100 ohm, 1%, 0.1W
0603
CRCW0603100RFKEA
Vishay
RSEN
RES, 0.03 ohm, 1%, 1W
1206
WSLP1206R0300FEA
Vishay
Q1
NexFET™ N-CH, 25V, 60A, RDS(on)= 4.4mohm
8-SON
CSD16323Q3
TI
Q2
NexFET™ N-CH, 25V, 60A, RDS(on)= 4.3mohm
8-SON
CSD16340Q3
TI
D1
Diode Schottky, 30V, 2A
SMB
20BQ030TRPBF
Vishay
L1
Shielded Inductor, 4.7μH, 2.3A
4mm L × 4mm W × 1.85mm H
MPI4040R3-4R7-R
Cooper
U1
LM3017
TI
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L1
RSEN
VIN = 5V to 10V
Q2
D1
VOUT = [email protected]
RS
EN/MODE
U1
ISEN
CIN1
VIN
VCC
CVCC
CCOMP2
RCOMP
Q1
DR
CO1
CO2
CO3
LM3017
COMP
CBYP
RFBT
VG
EN/MODE
FB
PGND
AGND
RFBB
GND
CCOMP
GND
Figure 30. Example 2A High Efficiency Step-Up (Boost) Converter
Bill of Materials (BOM) LM3017
28
Designation
Description
Size
Manufacturer Part #
Vendor
CIN1
Cap 220µF 16V
Radial
EEE-FC1C221P
Panasonic
CO1,CO2, CO3
Cap 22µF 25V X5R
1206
GRM31CR61E226KE15L
Murata
CCOMP
Cap 0.047µF
0603
06033C473JAT2A
AVX
CCOMP2
Cap 470pF
0603
06031C471JAT2A
AVX
CBYP
Cap 0.1µF 25V X7R
0603
06033C104KAT2A
AVX
CVCC
Cap 0.47μF 16V X7R
0805
C2012X7R1C474K
TDK
RCOMP
RES, 1kΩ, 1%, 0.1W
0603
CRCW06031K00FKEA
Vishay
RFBT
RES,16.9kΩ, 1%, 0.1W
0603
CRCW060316K9FKEA
Vishay
RFBB
RES, 2kΩ, 1%, 0.1W
0603
CRCW06032K00FKEA
Vishay
RS
RES, 100Ω, 1%, 0.1W
0603
CRCW0603100RFKEA
Vishay
RSEN
RES, 0.01Ω, 1%, 1W
1206
WSLP1206R0100FEA
Vishay
Q1
NexFET™ N-CH, 25V, 60A, RDS(on)= 4.4mΩ
8-SON
CSD16323Q3
TI
Q2
NexFET™ N-CH, 25V, 60A, RDS(on)= 4.3mΩ
8-SON
CSD16340Q3
TI
D1
Diode Schottky, 30V, 5A
SOD128
PMEG3050BEP
NXP
L1
Shielded Inductor, 2.2μH, 10A
6.36mm L × 6.56mm W × 3.1mm H
XAL6030-182ME
Coilcraft
U1
LM3017
TI
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LM3017LE/NOPB
PREVIEW
WQFN
NKL
10
1000
Green (RoHS
& no Sb/Br)
SN
Level-3-260CNOTCALC
-40 to 125
SK6B
LM3017LEX/NOPB
PREVIEW
WQFN
NKL
10
4500
Green (RoHS
& no Sb/Br)
SN
Level-3-260CNOTCALC
-40 to 125
SK6B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM3017LEX/NOPB
Package Package Pins
Type Drawing
WQFN
NKL
10
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
4500
330.0
12.4
Pack Materials-Page 1
2.7
B0
(mm)
K0
(mm)
P1
(mm)
3.0
1.0
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3017LEX/NOPB
WQFN
NKL
10
4500
358.0
343.0
63.0
Pack Materials-Page 2
MECHANICAL DATA
NKL0010A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
LEK10A (Rev A)
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