a FEATURES –2 V to +6 V Output Range 2.5 ⍀ Output Resistance 2.5 ns Tr/Tf for a 3 V Step 300 MHz Toggle Rate Can Drive 25 ⍀ Lines and Lower Peak Dynamic Current Capability of 400 mA Inhibit Leakage <1 A On-Chip Temperature Sensor APPLICATIONS Automatic Test Equipment Semiconductor Test Systems Board Test Systems Instrumentation and Characterization Equipment High Speed, High Current Capability Pin Driver AD53500 FUNCTIONAL BLOCK DIAGRAM VCC VCC VEE VEE 39nF 39nF VH VHDCPL DATA DATA 2V DRIVER INH VOUT INH VL VLDCPL TVCC AD53500 THERM 1.0mA/K GND PRODUCT DESCRIPTION: The AD53500 is a complete high speed driver designed for use in digital or mixed signal test systems where high speed and high output drive capabilities are needed. Combining a high speed monolithic process and a unique surface mount package, this product attains superb electrical performance while preserving optimum packing densities and long-term reliability thanks to an ultrasmall 20-lead, PSOP package with built-in heat sink. High and low reference levels can be set within a –2 V to +6 V range with low offset voltage and high gain accuracy. A 2.5 Ω output resistance allows use of an external backmatch resistor for application to 50 Ω, 25 Ω or other complex impedance load requirements. Without a backmatch resistor it is also capable of driving highly capacitive loads, typically achieving a rise/fall time GND GND GND GND of less than 10 ns with a 1000 pF capacitance. To test I/O devices, the pin driver can be switched into a high impedance state (Inhibit Mode), electrically removing the driver from the path. The pin driver leakage current in inhibit is typically less than 1 µA and output capacitance is typically less than 18 pF. Transitions from HI/LO or to inhibit are controlled through the data and inhibit inputs. The input circuitry utilizes high-speed differential inputs with a common-mode range of –2 V to +5 V. This allows for direct interface to the precision of differential ECL timing or the simplicity of stimulating the pin driver from a single-ended CMOS or TTL logic source or any combination over the common-mode range. The analog logic HI/LO inputs are equally easy to interface, typically requiring 50 µA of bias current. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 (All specifications are at T = +85ⴗC ⴞ 5ⴗC, +V = +10 V ⴞ 3%, –V = +6 V ⴞ 3% AD53500–SPECIFICATIONS unless otherwise noted. All temperature coefficients are measured over T = 75ⴗC–95ⴗC). (In test figures, voltmeter loading is 1 M⍀ or greater, J S S J scope probe loading is 100 k⍀ in parallel with 5 pF.) 39 nF capacitors must be connected between VCC and VHDCPL and between VEE and VLDCPL. Parameter Min DIFFERENTIAL INPUT CHARACTERISTICS (DATA to DATA, INH to INH) Common-Mode Input Voltage Differential Input Range Bias Current –2 Typ Max Units +5 Volts ECL or TTL ± 100 Test Conditions µA ECL = –0.8 V/–1.8 V, TTL = 0 V/5 V VCM = –2 V, +5 V REFERENCE INPUTS Bias Currents –50 +50 µA VL , VH = 5 V OUTPUT CHARACTERISTICS Logic High Range Logic Low Range Amplitude (VH and VL) +1 –2 0.1 +6 +2 8 Volts Volts Volts –10 +10 mV DATA = H, VL = –2 V, VH = +1 V to +6 V DATA = L, VL = –2 V to +2 V, VH = +6 V VL = –0.05 V, VH = +0.05 V and VL = –2 V, VH = +6 V 100 mV Output Amplitude VH, VL Interaction Absolute Accuracy VH Offset VH Gain + Linearity Error VL Offset VL Gain + Linearity Error Offset TC, VH or V L Output Resistance –100 –100 1.5 Dynamic Current Limit Static Current Limit DYNAMIC PERFORMANCE, DRIVE (V H and VL ) Propagation Delay Time +100 mV % of VH + mV +100 mV % of VL + mV mV/°C 5.5 Ω ± 0.3 ±5 ± 0.3 ±5 0.5 2.5 400 mA 60 –180 180 –60 mA mA DATA = H, VH = 0 V, VL = –2 V DATA = H, VL = –2 V, VH = +1 V to +6 V DATA = L, VL = 0 V, V H = +6 V DATA = L, VL = –2 V to +2 V, VH = +6 V VL , VH = 0 V, +5 V and –2 V, 0 V VH = +3 V, VL = 0 V, I OUT = 0, –30 mA, +30 mA C BYP = 39 nF, V H = +5 V, VL = 0 V C LOAD = 1000 pF, Tr/Tf = 10 ns Output to –2 V, VH = +6 V, VL = –1 V, DATA = H and Output to +6 V, VH = +6 V, VL = –2 V, DATA = L Measured at 50%, VH = +400 mV, VL = –400 mV Measured at 50%, VH = +400 mV, VL = –400 mV Measured at 50%, VH = +400 mV, VL = –400 mV 2.5 ns Propagation Delay TC 1 ps/°C Delay Matching, Edge-to-Edge 100 ps 0.85 2.5 4.0 ns ns ns Measured 20%–80%, V L = 0 V, VH = 1 V Measured 10%–90%, V L = 0 V, VH = 3 V Measured 10%–90%, V L = 2 V, VH = 3 V ±1 ±2 ±3 +5.0 +30 ps/°C ps/°C ps/°C % of Step + mV Measured 20%–80%, V L = 0 V, VH = 1 V Measured 10%–90%, V L = 0 V, VH = 3 V Measured 10%–90%, V L = 0 V, VH = 5 V VH –VL = 0.5 V, 1 V, 3 V, 8 V 40 8 100 ns µs ps VL = 0 V, VH = 0.5 V VL = 0 V, VH = 0.5 V VL = 0 V, VH = 2 V, Pulsewidth = 2.5 ns/ Period = 10 ns and Pulsewidth = 30 ns/ Period = 120 ns 3.8 ns 5 V Swing 5.5 ns Toggle Rate 300 MHz VL = 0 V, VH = 3 V, Output = 2.7 V p-p, Measure at 50% VL = 0 V, VH = 5 V, Output = 4.5 V p-p, Measure at 50% VL = –1.8 V, VH = –0.8 V, VOUT > 600 mV p-p Rise and Fall Time 1 V Swing 3 V Swing 5 V Swing Rise and Fall Time TC 1 V Swing 3 V Swing 5 V Swing Overshoot, Undershoot and Preshoot Settling Time to 15 mV to 4 mV Delay Change vs. Pulsewidth Minimum Pulsewidth 3 V Swing –2– REV. 0 AD53500 Parameter Min DYNAMIC PERFORMANCE, INHIBIT Delay Time, Active to Inhibit Delay Time, Inhibit to Active I/O Spike Output Leakage Output Capacitance PSRR, Drive Mode POWER SUPPLIES Total Supply Range Positive Supply Negative Supply Positive Supply Current Negative Supply Current Total Power Dissipation Temperature Sensor Gain Factor Typ Max Units Test Conditions 2 10 ns 2 10 ns 18 35 mV, p-p µA pF dB Measured at 50%, VH = +2 V, VL = –2 V, 50 Ω Terminated to Ground Measured at 50%, VH = +2 V, VL = –2 V, 50 Ω Terminated to Ground VH = 0 V, VL = 0 V VOUT = –2 V to +6 V Driver Inhibited VS = VS ± 3% 16 +10 –6 85 88 1.37 1.0 V V V mA mA W µA/K R LOAD = 10 kΩ, VSOURCE = +10 V <200 –1.0 +1.0 95 98 1.54 NOTES Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 VOUT VOUT = (MAX) = +7V Power Supply Voltage +VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V –VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V +VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18 V Inputs DATA, DATA, INH, INH . . . . . . . . . . . . . . . . +5 V, –3 V DATA to DATA, INH to INH . . . . . . . . . . . . . . . . ±3 V VH, V L to GND . . . . . . . . . . . . . . . . . . . . . . . . . +7 V, –3 V VH to VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10 V, 0 V Outputs VOUT Short Circuit Duration to Ground . . . . . . . Indefinite2 VOUT Range in Inhibit Mode . . . . . . . . . . . . . See Figure 1 VHDCPL . . . . . . . . Do Not Connect Except for Cap to VCC3 VLDCPL . . . . . . . . . Do Not Connect Except for Cap to VEE3 THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS, 0 V Environmental Operating Temperature (Junction) . . . . . . . . . . . . . .+175°C Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec)4 . . . . . . . . . . +260°C 7 6 5 4 3 2 1 VH, VL –2 –1 1 –1 3 4 5 6 –2 –3 VOUT = (MIN) = –3V FIGURE 1 SHOWS THE MAXIMUM ALLOWABLE LIMITS FOR VOUT AS A FUNCTION OF VHIGH AND VLOW WHEN THE DRIVER IS OPERATING IN INHIBIT MODE. THE LIMITS, AS STATED BEFORE, ARE MAXIMUM RATINGS ONLY, AND SHOULD NOT BE USED AS THE PART'S NORMAL OPERATING RANGE. THIS RANGE APPLIES ONLY TO SUPPLIES OF +VS = +10V AND –VS = –6V AND SHOULD BE DERATED PROPORTIONALLY FOR LOWER SUPPLIES. VHIGH / VLOW NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Absolute maximum limits apply individually, not in combination. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Output short circuit protection is guaranteed as long as proper heat sinking is employed to ensure compliance with the operating temperature limits. 3 The V HDCPL and VLDCPL capacitors may be replaced by a low value resistor for higher dc-current drive capability. 4 To ensure lead coplanarity (±0.002 inches) and solderability, handling with bare hands should be avoided and the device should be stored in environments at 24°C ± 5°C (75°F ± 10°F) with relative humidity not to exceed 65%. Figure 1. Absolute Maximum Ratings for V OUT CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD53500 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 2 –3– WARNING! ESD SENSITIVE DEVICE AD53500 PIN CONFIGURATION VCC 1 20 THERM VCC 2 19 TVCC VHDCPL 3 18 VH GND 4 17 GND VOUT 5 16 GND AD53500 Table I. Pin Driver Truth Table TOP VIEW 15 V GND L (Not to Scale) 7 14 GND VLDCPL DATA DATA INH INH Output State 0 1 0 1 1 0 1 0 0 0 1 1 1 1 0 0 VL VH Hi-Z Hi-Z 6 Table II. Package Thermal Characteristics VEE 8 13 DATA VEE 9 12 DATA Air Flow, FM JC, ⴗC/W JA, ⴗC/W INH 10 11 INH 50 400 3.28 3.91 49.1 33.74 PIN FUNCTION DESCRIPTIONS Pin Name Pin Number Description VCC 1, 2 VEE 8, 9 GND 4, 6, 14, 16, 17 VL 15 VH 18 VOUT VHDCPL 5 3 VLDCPL 7 INH, INH 10, 11 DATA, DATA 13, 12 TVCC THERM 19 20 Positive Power Supply. Both pins should be connected to minimize inductance and allow maximum speed of operation. VCC should be decoupled to GND with a low inductance 0.1 µF capacitor. Negative Power Supply. Both pins should be connected to keep the inductance down and allow maximum speed of operation. VEE should be decoupled to GND with a low inductance 0.1 µF capacitor. Device Ground. These pins should be connected to the circuit board’s ground plane at the pins. Analog input that sets the voltage level of a Logic 0 of the driver. Determines the driver output for DATA > DATA. Analog input that sets the voltage level of a Logic 1 of the driver. Determines the driver output for DATA > DATA. The Driver Output. Internal supply decoupling for the output stage. This pin is connected to VCC through a 39 nF (minimum) capacitor. Internal supply decoupling for the output stage. This pin is connected to VEE through a 39 nF (minimum) capacitor. Differential inputs that control the high impedance state of the driver. When INH > INH, the driver goes into a high impedance state. Differential inputs that determine the high and low state of the driver. Driver output is high for DATA > DATA. Temperature Sensor Startup Pin. This pin should be connected to VCC. Temperature sensor output pin. A resistor (10 kΩ) should be connected between THERM and VCC. The approximate die temperature can be determined by measuring the current through the resistor. The typical scale factor is 1 µA/K. ORDERING GUIDE Shipment Method, Quantity Per Package Shipping Container Option Model Package Description AD53500JRP 20-Lead Power SOIC Tube, 38 Pieces –4– RP-20 REV. 0 AD53500 APPLICATION INFORMATION Power Supply Distribution, Bypassing and Sequencing The AD53500 draws substantial transient currents from its power supplies when switching between states and careful design of the power distribution and bypassing is key to obtaining specified performance. Supplies should be distributed using broad, low inductance traces or (preferably) planes in a multilayered board with a dedicated ground-plane layer. All of the device’s power supply pins should be used to minimize the internal inductance presented by the part’s bond wires. Each supply must be bypassed to ground with at least one 0.1 µF capacitor; chip-style capacitors are preferable as they minimize inductance. One or more 10 µF (or greater) Tantalum capacitors per board are also advisable to provide additional local energy storage. capacitor to the positive supply (and the VLDCPL capacitor to the negative supply)—failure to do so causes considerable thermal stress in the current-limiting resistor(s) during normal supply sequencing and may ultimately cause them to fail, rendering the part nonfunctional. Finally, the AD53500 may appear to function normally for small output steps (less than 3 V or so) if one or both of these caps is absent, but it may exhibit excessive rise or fall times for steps of larger amplitude. The AD53500 does not require special power-supply sequencing. However, good design practice dictates that digital and analog control signals not be applied to the part before the supplies are stable. Violating this guideline will not normally destroy the part, but the active inputs can draw considerable current until the main supplies are applied. The AD53500’s current-limit circuitry also requires external bypass capacitors. Figure 2 shows a simplified schematic of the positive current-limit circuit. Excessive collector current in output transistor Q49 creates a voltage drop across the 5 Ω resistor, which turns on PNP transistor Q48. Q48 diverts the rising-edge slew current, shutting down the current mirror and removing the output stage’s base drive. The VHDCPL pin should be bypassed to the positive supply with a 0.039 µF capacitor, while the VLDCPL pin (not shown) requires a similar capacitor to the negative supply. These capacitors ensure that the AD53500 does not current-limit during normal output transitions up its full 8 V rated step size. Both capacitors must have minimumlength connections to the AD53500. Here again, chip capacitors are ideal. V+ 5V Q48 RISING-EDGE SLEW CONTROL CURRENT LEVEL-SHIFTED LOGIC DRIVE VH V– Q49 Several points about the current-limit circuitry should be noted. First, the limiting currents are not tightly controlled, as they are functions of both absolute transistor VBE and junction temperature; higher dc output current is available at lower junction temperatures. Second, it is essential to connect the VHDCPL REV. 0 VHDCPL OUT Q50 Figure 2. Simplified Schematic of the AD53500 Output Stage and Positive Current-Limit Circuitry –5– INH –6– 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 50V 50V DB15 P1 J2 SMA DATA J1 SMA R5 50V R6 50V 4 5 4 5 C13 0.01mF 3 2 –5.2V –2V C21 0.1mF 6 7 –5.2V C4 1mF JP3 1 –VS TP TP JP1 1 GND TP JP2 1 +VS –2V C22 0.1mF 6 7 U2 9 8 MC10EL16 C12 0.01mF 3 2 U1 9 8 MC10EL16 C7 1mF R1 50V R4 50V J5 J6 C8 0.1mF SMA SMA J3 SMA SMA C5 1mF C15 0.1mF C14 0.1mF C6 1mF R2 50V R3 50V J4 +VS –VS THERM –5.2V VL –2V VH 50V 50V 50V 50V C1 0.1mF VL C2 0.1mF C10 0.1mF –VS 9 2 8 C11 0.1mF –5.2V 16 14 INH 1 IL+ C19 0.1mF VCC IL– U3 AD53500 VOUT DATA VH VL TH 19 17 +VS 7 6 5 4 3 GND C3 0.1mF C17 0.039mF C16 0.039mF 50V C20 1000pF R8 47V NOTES: 1. 50V TERMINATION TO BE AS CLOSE TO RECEIVER AS POSSIBLE. (END OF TRACE MARKED BY *). THROUGH SMA CONNECTS BETWEEN MC10EL16 OUTPUTS AND DUT. 2. NO VIAS ALLOWED ON VOUT LINE. 3. SMA ON VOUT TO BE MOUNTED ON ITS SIDE FOR BEST IMPEDANCE MATCH. 4. ONE DIMENSION OF BOARD TO BE 4 1/2 INCHES. 5. DUT PACKAGE IS TO BE CENTERED ON BOARD. 6. ALL RESISTORS AND NONELECTROLYTIC CAPS ARE 0805-SIZE SURFACE MOUNT. 7. SEE DATA FOR HIDDEN POWER AND GROUND PINS ON LOGIC GATES. 8. ALL 100nF BYPASS CAPACITORS TO BE LOCATED CLOSE TO PACKAGE. 9. PCB IS TO BE FOUR-LAYER WITH POWER GND ( ) AND –2V AS INNER PLANES. C9 0.1mF VEE 10* 11 13* 12 18 15 20 THERM VH VOUT J7 SIDE SMA AD53500 Figure 3. Evaluation Board Schematic REV. 0 AD53500 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Thermally Enhanced Small Outline Package (PSOP) (RP-20) 20 11 0.1890 (4.80) 0.4193 (10.65) 0.1791 (4.55) 0.3937 (10.00) HEAT SINK 0.2992 (7.60) 0.2914 (7.40) 1 PIN 1 C3527–2–4/99 0.5118 (13.00) 0.4961 (12.60) 10 0.3340 (8.61) 0.3287 (8.35) 0.1043 (2.65) 0.0926 (2.35) 88 08 0.0201 (0.51) SEATING 0.0500 (1.27) 0.0130 (0.33) PLANE 0.0057 (0.40) 0.0295 (0.75) 3 458 0.0098 (0.25) PRINTED IN U.S.A. 0.0118 (0.30) 0.0500 0.0040 (0.10) (1.27) BSC STANDOFF REV. 0 –7–