TI TPS55340RTET

TPS55340
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SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012
Integrated 5-A 40-V Wide Input Range Boost/SEPIC/Flyback DC-DC Regulator
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FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The TPS55340 is a monolithic non-synchronous
switching regulator with integrated 5-A, 40-V power
switch. It can be configured in several standard
switching-regulator topologies, including boost,
SEPIC and isolated flyback. The device has a wide
input voltage range to support applications with input
voltage from multi-cell batteries or regulated 3.3-V, 5V, 12-V, and 24-V power rails.
1
2
•
•
•
Internal 5-A, 40-V Low-Side MOSFET Switch
2.9-V to 32-V Input Voltage Range
±0.7% Reference Voltage
0.5mA Operating Quiescent Current
2.7µA Shutdown Supply Current
Fixed Frequency Current Mode PWM Control
Frequency Adjustable from 100kHz to 1.2MHz
Synchronization Capability to External Clock
Adjustable Soft-Start Time
Pulse-Skipping for Higher Efficiency at Light
Loads
Cycle-by-Cycle Current Limit, Thermal
Shutdown, and UVLO Protection
QFN-16 (3mmx3mm) and HTSSOP-14
Packages with PowerPad™
Wide –40°C to 150°C Operating TJ Range
•
•
The device features a programmable soft-start
function to limit inrush current during start-up and has
other built-in protection features including cycle-bycycle over current limit and thermal shutdown.
The TPS55340 is available in a small 3mm x 3mm
16-pin QFN as well as 14-pin HTSSOP packages
with PowerPad™ for enhanced thermal performance.
APPLICATIONS
•
•
•
The TPS55340 regulates the output voltage with
current mode PWM (pulse width modulation) control,
and has an internal oscillator. The switching
frequency of PWM is set by either an external resistor
or by synchronizing to an external clock signal. The
user can program the switching frequency from 100
kHz to 1.2 MHz.
3.3-V, 5-V, 12-V, 24-V Power Conversion
Boost, SEPIC, and Flyback Topologies
Thunderbolt Port, Power Docking for Tablets
and Portable PCs
Industrial Power Systems
ADSL Modems
The 5-A, 40-V TPS55340 Boost Converter in the
HTSSOP-14 package is pin-to-pin compatible with
the 3-A, 40-V TPS61175 and it extends the maximum
input voltage from 18 V to 32 V.
TYPICAL APPLICATION (BOOST)
L
VIN
D
100
VOUT
95
TPS55340
VIN
SW
RSH
EN
SW
FREQ
SW
SS
FB
COMP
PGND
SYNC
PGND
AGND
PGND
CSS
RFREQ
RC
90
CO
CC
Efficiency (%)
CI
85
VOUT = 24 V
fSW = 600 kHz
80
75
70
65
RSL
VIN = 15 V
VIN = 12 V
VIN = 5 V
60
55
50
0
0.4
0.8
1.2
1.6
Output Current (A)
2
2.4
G031
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS55340
SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TJ
PART NUMBER
-40°C to 150°C
(1)
PACKAGE
TPS55340RTE
QFN-16
TPS55340PWP
HTSSOP-14
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
PIN ASSIGNMENTS
16
14
2
EN
3
PGND
HTSSOP-14 PACKAGE
(Top View)
13
1
VIN
12
PowerPAD
(17)
4
5
6
7
8
COMP
FB
PGND
11
PGND
10
NC
9
AGND
SS
15
SYNC
SW
NC
SW
SW
QFN-16 PACKAGE
(Top View)
FREQ
SW
1
14
PGND
SW
2
13
PGND
VIN
3
12
PGND
EN
4
SS
PowerPAD
(15)
11
NC
5
10
FREQ
SYNC
6
9
FB
AGND
7
8
COMP
PIN FUNCTIONS
PIN
NAME
DESCRIPTION
NO.
QFN-16
HTSSOP-14
VIN
2
3
SW
1, 15, 16
1, 2
SW is the drain of the internal power MOSFET. Connect SW to the switched side of the boost or SEPIC inductor or
the flyback transformer.
FB
8
9
Error amplifier input and feedback pin for positive voltage regulation. Connect to the center tap of a resistor divider
to program the output voltage.
EN
3
4
Enable pin. When the voltage of this pin falls below the enable threshold for more than 1ms, the IC turns off.
COMP
7
8
Output of the transconductance error amplifier. An external RC network connected to this pin compensates the
regulator feedback loop.
SS
4
5
Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start timing.
FREQ
9
10
Switching frequency program pin. An external resistor connected between the FREQ pin and AGND sets the
switching frequency.
Signal ground of the IC.
The input supply pin to the IC. Connect VIN to a supply voltage between 2.9V and 32V. It is acceptable for the
voltage on the pin to be different from the boost power stage input.
AGND
6
7
PGND
11, 12, 13
12, 13, 14
SYNC
5
6
Switching frequency synchronization pin. An external clock signal can be used to set the switching frequency
between 200kHz and 1.0MHz. If not used, this pin should be tied to AGND.
10, 14
11
Reserved pin that must be connected to ground.
17
15
The PowerPAD should be soldered to the AGND. If possible, use thermal vias to connect to internal ground plane
for improved power dissipation.
NC
PowerPAD
2
Power ground of the IC. It is connected to the source of the internal power MOSFET switch.
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FUNCTIONAL BLOCK DIAGRAM
VIN
SW
FB
Error
Amp
EN
1.229V
Reference
COMP
PWM
Control
Ramp
Generator
Gate
Driver
Lossless
Current Sense
S
Oscillator
SS
SYNC
FREQ
AGND
PGND
ABSOLUTE MAXIMUM RATINGS (1)
over operating temperature range (unless otherwise noted)
VALUE
UNIT
MIN
MAX
Supply voltages on pin VIN (2)
–0.3
34
V
Voltage on pin EN (2)
–0.3
34
V
Voltage on pins FB, FREQ, and COMP (2)
–0.3
3
V
Voltage on pin SS
(2)
–0.3
5
V
Voltage on pin SYNC (2)
–0.3
7
V
Voltage on pin SW (2)
–0.3
40
V
Operating junction temperature range
–40
150
°C
Storage temperature range
–65
150
°C
2
kV
500
V
Electrostatic discharge
(1)
(2)
(HBM) QSS 009-105 (JESD22-A114A)
(CDM) QSS 009-147 (JESD22-C101B 01)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal
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THERMAL INFORMATION
TPS55340
THERMAL METRIC (1)
QFN (16-PINS)
HTSSOP (14PINS)
θJA
Junction-to-ambient thermal resistance
43.3
43.2
θJCtop
Junction-to-case (top) thermal resistance
38.7
33.3
θJB
Junction-to-board thermal resistance
14.5
28.3
ψJT
Junction-to-top characterization parameter
0.4
1.3
ψJB
Junction-to-board characterization parameter
14.5
28.1
θJCbot
Junction-to-case (bottom) thermal resistance
3.5
3.9
UNITS
°C/W
space
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VIN
Input voltage range
2.9
32
V
VOUT
Output voltage range
VIN
38
V
VEN
EN voltage range
0
32
V
VSYN
External switching frequency logic input range
0
5
V
TA
Operating free-air temperature
–40
125
°C
TJ
Operating junction temperature
–40
150
°C
MAX
UNIT
ELECTRICAL CHARACTERISTICS
Vin=5V, TJ = –40°C to +150°C, unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
SUPPLY CURRENT
VIN
Input voltage range
IQ
Operating quiescent current into Vin
Device non-switching, VFB = 2 V
0.5
ISD
Shutdown current
EN = GND
2.7
10
VUVLO
Under-voltage lockout threshold
VIN falling
2.5
2.7
V
Vhys
Under-voltage lockout hysteresis
140
160
mV
4
2.9
120
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32
V
mA
µA
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SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012
ELECTRICAL CHARACTERISTICS (continued)
Vin=5V, TJ = –40°C to +150°C, unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
ENABLE AND REFERENCE CONTROL
VEN
EN threshold voltage
0.9
1.08
1.30
VENh
EN threshold hysteresis
EN rising input
0.1
0.16
0.22
V
REN
EN pull down resistor
400
950
1600
kΩ
Toff
Shutdown delay, SS discharge
VSYNh
SYN logic high voltage
VSYNl
SYN logic low voltage
EN high to low
1.0
ms
1.2
0.4
V
VOLTAGE AND CURRENT CONTROL
1.204
1.229
1.254
1.220
1.229
1.238
TA = 25°C
1.6
20
VFB = VREF+200 mV, VCOMP = 1 V
42
µA
42
µA
3.1
0.75
V
VREF
Voltage feedback regulation voltage
IFB
Voltage feedback input bias current
Isink
Comp pin sink current
Isource
Comp pin source current
VFB = VREF–200 mV, VCOMP = 1 V
VCCLP
Comp pin Clamp Voltage
High Clamp, VFB = 1 V
Low Clamp, VFB = 1.5 V
VCTH
Comp pin threshold
Duty cycle = 0%
1.04
V
Gea
Error amplifier transconductance
Rea
Error amplifier output resistance
fea
Error amplifier crossover frequency
TA = 25°C
240
360
V
nA
440 µmho
10
MΩ
500
kHz
FREQUENCY
fSW
Frequency
Dmax
Maximum duty cycle
VFREQ
FREQ pin voltage
Tmin_on
Minimum on pulse width
RFREQ = 480 kΩ
75
94
RFREQ = 80 kΩ
460
577
740
RFREQ = 40 kΩ
920
1140
1480
89%
96%
VFB = 1.0 V, RFREQ = 80 kΩ
130
kHz
1.25
V
RFREQ = 80 kΩ
77
ns
60
70
POWER SWITCH
RDS(ON)
N-channel MOSFET on-resistance
VIN = 5 V
VIN = 3 V
ILN_NFET
N-channel leakage current
VDS = 25 V, TA = 25°C
110
120
mΩ
2.1
µA
7.75
A
OCP and SS
ILIM
N-Channel MOSFET current limit
D = Dmax
ISS
Soft-start bias current
Vss = 0 V
5.25
6.6
6
µA
165
°C
15
°C
THERMAL SHUTDOWN
Tshutdown
Thermal shutdown threshold
Thysteresis
Thermal shutdown threshold hysteresis
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TYPICAL CHARACTERISTICS
Vin = 5 V, TA = 25°C (unless otherwise noted)
8
Current Limit Threshold (A)
Transconductance (µA/V)
400
380
360
340
320
7
6
5
4
3
2
300
−50
−25
0
25
50
75
Temperature (°C)
100
125
1
−50
150
Figure 1. Error Amplifier Transconductance vs Temperature
125
150
G002
VIN = 3 V
Resistance (mΩ)
Voltage Reference (V)
100
100
1.228
1.226
1.224
80
60
VIN = 12 V
40
VIN = 5 V
20
1.22
−50
−25
0
25
50
75
Temperature (°C)
100
125
0
−50
150
−25
0
G003
Figure 3. Feedback Voltage Reference vs Temperature
1600
1400
1400
1200
Frequency (kHz)
1000
800
600
400
25
50
75
Temperature (°C)
30
100
Resistance (kΩ)
500
125
150
G004
1000
800
600
RFREQ = 40 kΩ
RFREQ = 80 kΩ
RFREQ = 480 kΩ
400
200
200
100
Figure 4. RDS(ON) vs Temperature
1200
Frequency (kHz)
25
50
75
Temperature (°C)
120
1.222
0
−50
G005
Figure 5. Frequency vs FREQ Resistance
6
0
Figure 2. Switch Current Limit vs Temperature
1.23
0
−25
G001
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−25
0
25
50
75
Temperature (°C)
100
125
150
G006
Figure 6. Frequency vs Temperature
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TYPICAL CHARACTERISTICS (continued)
Vin = 5 V, TA = 25°C (unless otherwise noted)
700
3.5
RFREQ = 80 kΩ
3
500
COMP Voltage (V)
Frequency (kHz)
600
400
Non-Foldback
Foldback
300
200
2.5
1.5
1
100
0
−50
−25
0
25
50
75
Temperature (°C)
100
125
0.5
−50
150
0
25
50
75
Temperature (°C)
100
125
150
G008
Figure 8. COMP Clamp Voltage vs Temperature
2.7
1.3
EN Voltage Rising
EN Voltage Falling
1.2
Enable Voltage (V)
2.66
2.62
UVLO Start
UVLO Stop
2.58
2.54
1.1
1
0.9
0.8
2.5
−50
−25
0
25
50
75
Temperature (°C)
100
125
0.7
−50
150
0
25
50
75
Temperature (°C)
100
125
150
G010
Figure 10. Enable Voltage vs Temperature
100
100
RFREQ = 80 kΩ
RFREQ = 80 kΩ
95
Minimum On Time (ns)
99
98
97
96
95
94
−50
−25
G009
Figure 9. Input Voltage UVLO vs Temperature
Maximum Duty Cycle (%)
−25
G007
Figure 7. Non-Foldback Frequency vs Foldback Frequency
Input Voltage (V)
COMP Pin Clamp High
COMP Pin Clamp Low
2
90
85
80
75
−25
0
25
50
75
Temperature (°C)
100
125
150
70
−50
G011
Figure 11. Maximum Duty Cycle vs Temperature
−25
0
25
50
75
Temperature (°C)
100
125
150
G012
Figure 12. Minimum On Time vs Temperature
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TYPICAL CHARACTERISTICS (continued)
8
2.1
7
1.8
Supply Current (mA)
Shutdown Current (µA)
Vin = 5 V, TA = 25°C (unless otherwise noted)
6
5
4
3
Switching
Non-Switching
1.2
0.9
0.6
2
1
−50
−25
0
25
50
75
Temperature (°C)
100
125
150
0.3
−50
−25
G013
Figure 13. Shutdown Current vs Temperature
8
1.5
0
25
50
75
Temperature (°C)
100
125
150
G014
Figure 14. Supply Current vs Temperature
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DETAILED DESCRIPTION
OPERATION
The TPS55340 integrates a 5 A, 40 V low side n-channel MOSFET for boost converter output up to 38V. The
TPS55340 regulates the output with current mode PWM (pulse width modulation) control. The PWM control
circuitry turns on the switch at the beginning of each oscillator clock cycle. The input voltage is applied across the
inductor and stores the energy as inductor current ramps up. During this portion of the switching cycle, the load
current is provided by the output capacitor. When the inductor current reaches a threshold level set by the error
amplifier output, the power switch turns off and the external Schottky diode is forward biased to allow the
inductor current to flow to the output. The inductor transfers stored energy to replenish the output capacitor and
supply the load current. This operation repeats every switching cycle. The duty cycle of the converter is
determined by the PWM control comparator which compares the error amplifier output and the current signal.
The oscillator frequency is programmed by the external resistor or synchronized to an external clock signal.
A ramp signal from the oscillator is added to the inductor current ramp to provide slope compensation. Slope
compensation is necessary to avoid sub-harmonic oscillation that is intrinsic to peak current mode control at duty
cycles higher than 50%. If the inductor value is too small, the internal slope compensation may not be adequate
to maintain stability.
The PWM control feedback loop regulates the FB pin to a reference voltage through a transconductance error
amplifier. The output of the error amplifier is connected to the COMP pin. An external RC compensation network
connected to the COMP pin is chosen for feedback loop stability and optimum transient response.
SWITCHING FREQUENCY
The switching frequency is set by a resistor (RFREQ) connected to the FREQ pin of the TPS55340. The
relationship between the timing resistance RFREQ and frequency is shown in the Figure 5. Do not leave this pin
open. A resistor must always be connected from the FREQ pin to ground for proper operation. The resistor value
required for a desired frequency can be calculated using Equation 1.
RFREQ(kΩ) = 57500 × ƒsw(kHz)–1.03
(1)
For the given resistor value, the corresponding frequency can be calculated by Equation 2.
ƒsw(kHz) = 41600 × RFREQ(kΩ)–0.97
(2)
The TPS55340 switching frequency can be synchronized to an external clock signal that is applied to the SYNC
pin. The required logic levels of the external clock are shown in the specification table. The recommended duty
cycle of the clock is in the range of 10% to 90%. A resistor must be connected from the FREQ pin to ground
when the converter is synchronized to the external clock and the external clock frequency must be within ±20%
of the corresponding frequency set by the resistor. For example, if the frequency programmed by the FREQ pin
resistor is 600kHz, the external clock signal should be in the range of 480kHz to 720kHz.
VOLTAGE REFERENCE AND SETTING OUTPUT VOLTAGE
An internal voltage reference provides a precise 1.229 V voltage reference at the error amplifier non-inverting
input. To set the output voltage, select the FB pin resistor RSH and RSL according to Equation 3.
æR
ö
VOUT = 1.229V ´ ç SH + 1÷
è RSL
ø
(3)
SOFT-START
The TPS55340 has a built-in soft-start circuit which significantly reduces the start-up current spike and output
voltage overshoot. When the IC is enabled, an internal bias current source (6 µA typical) charges a capacitor
(CSS) on the SS pin. The voltage at the capacitor clamps the output of the internal error amplifier that determines
the peak current and duty cycle of PWM controller. Limiting the peak switch current during start-up with a slow
ramp on the SS pin will reduce in-rush current and output voltage overshoot. Once the capacitor reaches 1.8V,
the soft-start cycle is completed and the soft-start voltage no longer clamps the error amplifier output. When the
EN is pulled low for at least 1ms, the IC enters the shutdown mode and the SS capacitor is discharged through a
5kΩ resistor to prepare for the next soft-start sequence.
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SLOPE COMPENSATION
The TPS55340 has internal slope compensation to prevent sub-harmonic oscillations. The sensed current slope
of boost converter can be expressed as Equation 4:
V
Sn = IN ´ RSENSE
(4)
L
The slope compensation dv/dt can be calculated using Equation 5.
0.32 V RFREQ 0.5 mA
Se =
+
16 ´ (1 - D) ´ 6 pF
6 pF
(5)
In a converter with current mode control, in addition to the output voltage feedback loop, the inner current loop
including the inductor current sampling effect as well as the slope compensation on the small signal response
should be taken into account, which can be modeled as seen in Equation 6:
1
He(s) =
éæ
ù
S ö
s ´ êç 1 + e ÷ ´ (1 - D) - 0.5 ú
Sn ÷ø
êëçè
úû
s2
1+
+
2
fsw
p ´ fsw
(6)
(
)
Where RSENSE (15mΩ) is the equivalent current sense resistor, RFREQ is timing resistor used to set frequency,
and D is the duty cycle.
Note that if Sn << Se, the converter operates in voltage mode control rather than current mode control, and
Equation 6 is no longer valid.
OVER-CURRENT PROTECTION AND FREQUENCY FOLDBACK
The TPS55340 provides cycle-by-cycle over-current protection that turns off the power switch once the inductor
current reaches the over-current limit threshold. The PWM circuitry resets itself at the beginning of the next
switch cycle. During an over-current event, the output voltage begins to droop as a function of the load on the
output. When the FB voltage through the feedback resistors, drops lower than 0.9 V, the switching frequency is
automatically reduced to 1/4 of the normal value. Figure 7 shows the non-foldback frequency with an 80kΩ timing
resistor and the corresponding foldback frequency. The switching frequency does not return to normal until the
over-current condition is removed and the FB voltage increases above 0.9 V. The frequency foldback feature is
disabled during soft-start.
ENABLE AND THERMAL SHUTDOWN
The TPS55340 enters shutdown when the EN voltage is less than 0.68 V (min) for more than 1ms. In shutdown,
the input supply current for the device is less than 10µA (max). The EN pin has an internal 950kΩ pull down
resistor to disable the device if the pin is floating.
An internal thermal shutdown turns off the device when the junction temperature exceeds 165°C (typical). The
device will restart when the junction temperature drops by 15°C.
UNDER-VOLTAGE LOCKOUT (UVLO)
An under-voltage lockout circuit prevents mis-operation of the device at input voltages below 2.5 V (typical).
When the input voltage is below the UVLO threshold, the device remains off and the internal power MOSFET is
turned off. The UVLO threshold is set below minimum operating voltage of 2.9 V to ensure that a transient VIN
dip will not cause the device to reset. For the input voltages between UVLO threshold and 2.9 V, the device
attempts to operate, but the electrical specifications are not guaranteed.
10
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MINIMUM ON TIME AND PULSE SKIPPING
The TPS55340 PWM control system has a minimum PWM pulse width of 77ns (typical). This minimum on-time
determines the minimum duty cycle of the PWM, for any set switching frequency. When the voltage regulation
loop of the TPS55340 requires a minimum on-time pulse width less than 77ns, the IC enters pulse-skipping
mode. In this mode, the device will hold the power switch off for several switching cycles to prevent the output
voltage from rising above the desired regulated voltage. This operation typically occurs in light load conditions
when the PWM operates in discontinuous conduction mode. Pulse skipping increases the output ripple as shown
in Figure 21.
LAYOUT COSIDERATIONS
As for all switching power supplies, especially those with high frequency and high switch current, printed circuit
board (PCB) layout is an important design step. If the layout is not carefully designed, the regulator could suffer
from instability as well as noise problems. To maximize efficiency, switch rise and fall times are made as short as
possible. To prevent radiation of high frequency resonance problems, proper layout of the high frequency
switching path is essential. Minimize the length and area of all traces connected to the SW pin and always use a
ground plane under the switching regulator to minimize inter-plane coupling. The high current path including the
internal MOSFET switch, Schottky diode, and output capacitor, contains nanosecond rise and fall times and
should be kept as short as possible. The input capacitor needs not only to be close to the VIN pin, but also to the
AGND pin in order to reduce the IC supply ripple.
THERMAL CONSIDERATIONS
The maximum IC junction temperature should be restricted to 150°C under normal operating conditions. This
restriction limits the power dissipation of the TPS55340. The TPS55340 features a thermally enhanced QFN
package. This package includes a PowerPad™ that improves the thermal capabilities of the package. The
thermal resistance of the QFN package in any application greatly depends on the PCB layout and the
PowerPad™ connection. The PowerPad™ must be soldered to the analog ground on the PCB. Use thermal vias
underneath the PowerPad™ to achieve good thermal performance.
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DESIGN GUIDE-STEP-BY-STEP DESIGN PROCEDURE OF BOOST CONVERTER
The following section provides a step-by-step design approach for configuring the TPS55340 as a voltage
regulating boost converter, as shown in Figure 15. When configured as SEPIC or flyback converter, a different
design approach is required. A design example of SEPIC converter is provided in the next section.
100 pF
Figure 15. Boost Converter Application Schematic
A few parameters must be known in order to start the design process. These parameters are typically determined
at the system level. For this example, we will start with the following known parameters:
Table 1. Key Parameters of Boost Converter Example
PARAMETER
VALUE
Output Voltage
24 V
Input Voltage
5 V to 12 V
Maximum Output Current
800 mA
Transient Response 50% load step (ΔVOUT = 3%)
960 mV
Output Voltage Ripple (0.5% of VOUT)
120 mV
SELECTING THE SWITCHING FREQUENCY (R4)
The first step is to decide on a switching frequency for the regulator. There are tradeoffs to consider for a higher
or lower switching frequency. A higher switching frequency allows for lower valued inductor and smaller output
capacitors leading to the smallest solution size. A lower switching frequency will result in a larger solution size
but better efficiency. The user will typically set the frequency for the minimum tolerable efficiency to avoid
excessively large external components.
A switching frequency of 600 kHz is a good trade-off between efficiency and solution size. The appropriate
resistor value is found from the resistance versus frequency graph of Figure 5, or calculated using Equation 1.
R4 is calculated to be 78.4 kΩ and the nearest standard value resistor of 78.7 kΩ is selected. A resistor must be
placed from the FREQ pin to ground, even if an external oscillation is applied for synchronization.
12
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DETERMINING THE DUTY CYCLE
The input to output voltage conversion ratio of the TPS55340 is limited by the worst case maximum duty cycle of
89% and the minimum duty cycle which is determined by the minimum on-time of 77 ns and the switching
frequency. The minimum duty cycle can be estimated with Equation 7. With a 600 kHz switching frequency the
minimum duty cycle is 4%.
DPS = TON min × ƒsw
(7)
The duty cycle at which the converter operates is dependent on the mode in which the converter is running. If the
converter is running in discontinuous conduction mode (DCM), where the inductor current ramps to zero at the
end of each cycle, the duty cycle varies with changes of the load much more than it does when running in
continuous conduction mode (CCM). In continuous conduction mode, where the inductor maintains a minimum
dc current, the duty cycle is related primarily to the input and output voltages as computed below. Assume a 0.5
V drop VD across the Schottky rectifier. At the minimum input of 5 V, the duty cycle will be 80%. At the maximum
input of 12 V, the duty cycle is 51%.
+ VD - VIN
V
D = OUT
VOUT + VD
(8)
At light loads the converter will operate in DCM. In this case the duty cycle is a function of the load, input and
output voltages, inductance and switching frequency as computed below. This can be calculated only after an
inductance is chosen in the following section. While operating in DCM with very light load conditions the duty
cycle demand will force the TPS55340 to operate with the minimum on time. The converter will then begin pulse
skipping which can increase the output ripple.
D=
2 ´ (VOUT + VD - VIN ) ´ L ´ IOUT ´ ¦ SW
VIN
(9)
All converters using a diode as the freewheeling or catch component have a load current level at which they
transit from discontinuous conduction mode to continuous conduction mode. This is the point where the inductor
current just falls to zero during the off-time of the power switch. At higher load currents, the inductor current does
not fall to zero and diode and switch current assume a trapezoidal wave shape as opposed to a triangular wave
shape. The load current boundary between discontinuous conduction and continuous conduction can be found
for a set of converter parameters as follows.
IOUT(crit) =
(VOUT + VD - VIN )´ VIN2
2
2 ´ (VOUT + VD ) ´ ¦ SW ´ L
(10)
For loads higher than the result of the Equation 10, the duty cycle is given by Equation 8. For loads less than the
results of Equation 10, the duty cycle is given Equation 9. For Equation 7 through Equation 10, the variable
definitions are as follows.
• VOUT is the output voltage of the converter in V
• VD is the forward conduction voltage drop across the rectifier or catch diode in V
• VIN is the input voltage to the converter in V
• IOUT is the output current of the converter in A
• L is the inductor value in H
• ƒSW is the switching frequency in Hz
Unless otherwise stated, the design equations that follow assume that the converter is running in continuous
conduction mode, which typically results in a higher efficiency for the power levels of this converter.
SELECTING THE INDUCTOR (L1)
The selection of the inductor affects steady state operation as well as transient behavior and loop stability. These
factors make it the most important component in power regulator design. There are three important inductor
specifications: inductor value, DC resistance and saturation current. Considering inductor value alone is not
enough. Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches
saturation level, the effective inductance can fall to a fraction of the zero current value.
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The minimum value of the inductor should be able to meet inductor current ripple (ΔIL) requirement at worst
case. In a boost converter, maximum inductor current ripple occurs at 50% duty cycle. For the applications where
duty cycle is always smaller or larger than 50%, Equation 12 should be used with the duty cycle closest to 50%
and corresponding input voltage to calculate the minimum inductance. For applications that need to operate with
50% duty cycle when input voltage is somewhere between the minimum and the maximum input voltage,
Equation 13 should be used. KIND is a coefficient that represents the amount of inductor ripple current relative to
the maximum input current (IINDC = ILavg). The maximum input current can be estimated with Equation 11, with
an estimated efficiency based on similar applications (ηEST). The inductor ripple current will be filtered by the
output capacitor. Therefore, choosing high inductor ripple currents will impact the selection of the output
capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple
current. In general, the inductor ripple value (KIND) is at the discretion of the designer. However, the following
guidelines may be used.
For CCM operation, it is recommended to use KIND values in the range of 0.2 to 0.4. Choosing KIND closer to 0.2
results in a larger inductance value, maximizes the converter’s potential output current and minimizes EMI.
Choosing KIND closer to 0.4 results in a smaller inductance value, a physically smaller inductor, and improved
transient response, but potentially worse EMI and lower efficiency. Using an inductor with a smaller inductance
value may result in the converter operating in DCM. This reduces the boost converter’s maximum output current,
causes larger input voltage and output voltage ripple and reduced efficiency. For this design, choose KIND = 0.3
and a conservative efficiency estimate of 85% with the minimum input voltage and maximum output current.
Equation 12 is used with the maximum input voltage because this corresponds to duty cycle closest to 50%. The
maximum input current is estimated at 4.52A and the minimum inductance is 7.53 µH. A standard value of 10 µH
is chosen.
VOUT ´ IOUT
IINDC =
hEST ´ VIN min
(11)
LO min ³
LO min ³
VIN
D
´
IINDC ´ KIND ¦ SW
(VOUT + VD )
IINDC ´ KIND
´
, D ≠ 50%, VIN with D closest to 50%
1
, D=50%
4 ´ ¦ SW
(12)
(13)
After choosing the inductance, the required current ratings can be calculated. The inductor will be closest to its
ratings with the minimum input voltage. The ripple with the chosen inductance is calculated with Equation 14.
The RMS and peak inductor current can be found with Equation 15 and Equation 16. For this design the current
ripple is 663mA, the RMS inductor current is 4.52 A, and the peak inductor current is 4.85 A. It is generally
recommended for the peak inductor current rating of the selected inductor be 20% higher to account for
transients during power up, faults or transient load conditions. The most conservative approach is to specify an
inductor with a saturation current greater than the maximum peak current limit of the TPS55340. This helps to
avoid saturation of the inductor. The chosen inductor is a Würth Elektronik 74437368100. It has a saturation
current rating of 12.5 A, RMS current rating of 5.2 A, and typical DCR of 27.0mΩ.
V min Dmax
DIL = IN
´
LO
¦ SW
(14)
æ DI ö
(IINDC )2 + ç L ÷
è 12 ø
DI
IL peak = IINDC + L
2
2
IL rms =
(15)
(16)
The TPS55340 has built-in slope compensation to avoid sub-harmonic oscillation associated with current mode
control. If the inductor value is too small, the slope compensation may not be adequate, and the loop can be
unstable.
14
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COMPUTING THE MAXIMUM OUTPUT CURRENT
The over-current limit for the integrated power MOSFET limits the maximum input current and thus the maximum
input power for a given input voltage. Maximum output power is less than maximum input power due to power
conversion losses. Therefore, the current limit setting, input voltage, output voltage and efficiency can all change
maximum current output (IOUTmax). The current limit clamps the peak inductor current, therefore the ripple has to
be subtracted to derive maximum DC current. Decreasing the KIND or designing for a higher efficiency will
increase the maximum output current. This can be evaluated with the chosen inductance or the chosen KIND.
This should be evaluated with the minimum input voltage and minimum peak current limit (ILIM) of 5.25 A.
DIL ö
æ
æ KIND ö
VIN min ´ ç ILIM ÷ ´ hEST VIN min ´ ILIM ´ ç 1 - 2 ÷ ´ hEST
2
è
ø
è
ø
IOUT max =
=
VOUT
VOUT
(17)
In this design with 5 V input boosted to 24 V output and a 10 μH inductor with an assumed the Schottky forward
voltage of 0.5 V and estimated efficiency of 85%, the maximum output current is 871 mA. With the 12 V input
and increased estimated efficiency of 90%, the maximum output current increases to 2.13 A. This circuit was
evaluated to its maximum output currents with both the minimum and maximum input voltage.
SELECTING THE OUTPUT CAPACITOR (C8-C10)
At least 4.7 µF of ceramic type X5R or X7R capacitance is recommended at the output. The output capacitance
is mainly selected to meet the requirements for the output ripple (VRIPPLE) and voltage change during a load
transient. Then the loop is compensated for the output capacitor selected. The output capacitance should be
chosen based on the most stringent of these criteria. The output ripple voltage is related to the capacitance and
equivalent series resistance (ESR) of the output capacitor. Assuming a capacitor with zero ESR, the minimum
capacitance needed for a given ripple can be calculated by Equation 18. If high ESR capacitors are used it will
contribute additional ripple. The maximum ESR for a specified ripple is calculated with Equation 19. ESR ripple
can be neglected for ceramic capacitors but must be considered if tantalum or electrolytic capacitors are used.
The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated by the
Equation 20. Equation 21 can be used to calculate the RMS current that the output capacitor needs to support.
Dmax ´ IOUT
COUT ³
¦ SW ´ VRIPPLE
(18)
æ
Dmax ´ IOUT ö
ç VRIPPLE ÷
¦ SW ´ COUT ø
ESR £ è
DIL
(19)
DITRAN
³
2 ´ p ´ ¦BW ´ DVTRAN
(20)
COUT
ICOrms = IOUT
Dmax
(1 - Dmax )
(21)
Using Equation 18 for this design, the minimum output capacitance for the specified 120 mV output ripple is 8.8
µF. For a maximum transient voltage change (ΔVTRAN) of 960 mV with a 400 mA load transient (ΔITRAN) and a 6
kHz control loop bandwidth (fBW) with Equation 20, the minimum output capacitance is 11.1 µF. The most
stringent criteria is the 11.1 µF for the required load transient. Equation 21 gives a 1.58 A RMS current in the
output capacitor. The capacitor should also be properly rated for the desired output voltage.
Care must be taken when evaluating ceramic capacitors that derate under dc bias, aging and AC signal
conditions. For example, larger form factor capacitors (in 1206 size) have self-resonant frequencies in the range
of converter switching frequency. Self-resonance causes the effective capacitance to be significantly lower. The
DC bias can also significantly reduce capacitance. Ceramic capacitors can lose as much as 50% of the
capacitance whan operated at the rated voltage. Therefore, allow margin in selected capacitor voltage rating to
ensure adequate capacitance at the required output voltage. For this example, three 4.7 µF, 50V 1210 X7R
ceramic capacitors are used in parallel leading to a negligible ESR. Choosing 50 V capacitors instead of 35 V
reduces the effects of DC bias and allows this example circuit to be rated for the maximum output voltage range
of the TPS55340.
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SELECTING THE INPUT CAPACITORS (C2, C7)
At least 4.7µF of ceramic input capacitance is recommended. Additional input capacitance may be required to
meet ripple and/or transient requirements. High quality ceramic, type X5R or X7R are recommended to minimize
capacitance variations over temperature. The capacitor must also have an RMS current rating greater than the
maximum RMS input current of the TPS55340 calculated with Equation 22. The input capacitor must also be
rated greater than the maximum input voltage. The input voltage ripple can be calculated with Equation 23.
DI
ICIrms = L
12
(22)
DIL
Vripple
=
+ DIL ´ RCIN
I
4 ´ ¦ SW ´ CIN
(23)
In the design example, the input RMS current is calculated to be 191 mA. The chosen input capacitor is a 10 µF,
35V 1210 X7R with 3 mΩ ESR. Although one with a lower voltage rating can be used, a 35 V rated capacitor
was chosen to limit the affects of dc bias and to allow it the circuit to be rated for the entire input range of the
TPS55340. The input ripple is calculated to be 30 mV. An additional 0.1 µF, 50V 0603 X5R is located close to
the VIN and GND pins for extra decoupling.
SETTING OUTPUT VOLTAGE (R1, R2)
To set the output voltage in either DCM or CCM, select the values of R1 and R2 according to the following
equations.
æ R1 ö
VOUT = 1.229V ´ ç
+ 1÷
è R2 ø
(24)
æ V
ö
R1 = R2 ´ ç OUT - 1÷
è 1.229V
ø
(25)
Considering the leakage current through the resistor divider and noise decoupling into FB pin, an optimum value
for R2 is around 10 kΩ. The output voltage tolerance depends on the VFB accuracy and the tolerance of R1 and
R2. In this example with a 24 V output using Equation 25, R1 is calculated to 185.3 kΩ. The nearest standard
value of 187 kΩ is used.
SETTING THE SOFT-START TIME (C7)
Choose the appropriate capacitor to set soft-start time and avoid overshoot. Increasing the soft-start time
reduces the overshoot during start-up. A 0.047 µF ceramic capacitor is used in this example.
SELECTING THE SCHOTTKY DIODE (D1)
The high switching frequency of the TPS55340 demands high-speed rectification for optimum efficiency. Ensure
that the diode’s average and peak current rating exceed the average output current and peak inductor current. In
addition, the diode’s reverse breakdown voltage must exceed the regulated output voltage. The diode must also
be rated for the power dissipated which can be calculated with Equation 26.
PD = VD × IOUT
(26)
In this conservative design example, the diode is chosen to be rated for the maximum output current of 2.13 A.
During normal operation with 800 mA output current and assuming a Schottky diode drop of 0.5V, the diode must
be capable of dissipating 400 mW. The recommended minimum ratings for this design are a 40 V, 3 A diode.
However to improve the flexibility of this design, a Diodes Inc B540-13-F in an SMC package is used with voltage
and current ratings of 40 V and 5A.
COMPENSATING THE CONTROL LOOP (R3, C4, C5)
The TPS55340 requires external compensation which allows the loop response to be optimized for each
application. The COMP pin is the output of the internal error amplifier. An external resistor R3 and ceramic
capacitor C4 are connected to the COMP pin to provide a pole and a zero, shown in the application circuit. This
pole and zero, along with the inherent pole and zero of a boost converter, determine the closed loop frequency
response. This is important for converter stability and transient response. Loop compensation should be
designed for the minimum operating voltage.
16
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The following equations summarize the loop equations for the TPS55340 configured as a CCM boost converter.
They include the power stage output pole (ƒOUT) and the right-half-plane zero (ƒRHPZ) of a boost converter
calculated with Equation 27 and Equation 28 respectively. When calculating ƒOUT it is important to include the
derating of ceramic output capacitors. In the example with an estimated 10.2 µF capacitance, these frequencies
are calculated to 980 kHz and 22.1 kHz respectively. The DC gain (A) of the power stage is calculated with
Equation 27 and is 39.9 dB in this design. The compensation pole (ƒP) and zero (ƒZ) generated by R3, C4 and
internal transconductance amplifier are calculated with Equation 30 and Equation 31 respectively.
Most CCM boost converters will have a stable control loop if fZ is set slightly above ƒP through proper sizing of
R3 and C4. A good starting point is C4 = 0.1 µF and R3 = 2kΩ. Increasing R3 or reducing C4 increases the
closed loop bandwidth, and therefore improves the transient response. Adjusting R3 and C4 in opposite direction
increases the phase and gain margin of the loop, which improves loop stability. It is generally recommended to
limit the bandwidth of the loop to the lower of either 1/5 of the switching frequency ƒSW or 1/3 the RHPZ
frequency, ƒRHPZ shown in Equation 28. The spreadsheet tool located in the TPS55340 product folder at
www.ti.com can also be used to aid in compensation design.
2
¦ OUT »
2p ´ ROUT ´ COUT
(27)
2
ROUT æ VIN ö
´ç
÷
2p ´ L è VOUT ø
VIN
1.229
1
A=
´ Gea ´ 10MW ´
´ ROUT ´
VOUT
VOUT ´ RSENSE
2
¦RHPZ »
(28)
(29)
1
¦P =
2p ´ 10MW ´ C4
1
¦Z =
2p ´ R3 ´ C4
¦
¦ co1 = SW
5
¦
¦ co2 = RHPZ
3
(30)
(31)
(32)
(33)
Where
COUT is the equivalent output capacitor (COUT=C8+C9+C10)
ROUT is the equivalent load resistance (VOUT/IOUT)
Gea is the error amplifier transconductance located in the ELECTRICAL CHARACTERISTICS table
RSENSE (15mΩ, typical) is the sense resistor in the current control loop
ƒco1 and ƒco2 are possible bandwith.
An additional capacitor from the COMP pin to GND (C5) can be used to place a high frequency pole in the
control loop. This is not always necessary with ceramic output capacitors. If a non-ceramic output capacitor is
used, there is an additional zero (fZESR) in the control loop which can be calculated with Equation 35. The value
of C5 and the pole created by C5 can be calculated with Equation 36 and Equation 34 respectively. Finally if
more phase margin is needed, an additional zero (fZFF) can be added by placing a capacitor (CFF) in parallel with
the top feedback resistor R1. It is recommended to place the zero at the target cross-over frequency or higher.
The feed forward capacitor also adds a pole at a higher frequency. The recommended value of CFF can be
calculated with Equation 37.
1
¦P2 =
2p ´ R3 ´ C5
(34)
1
¦ ZESR »
2p ´ RESR ´ COUT
(35)
C5 =
RESR ´ COUT
R3
(36)
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CFF =
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1
2p ´ R1´ ¦ ZFF ´
VREF
VOUT
(37)
where RESR is the ESR of the output capacitor.
If a network measurement tool is available, the most accurate compensation design can be achieved following
this procedure. The power stage frequency response is first measured using a network analyzer at the minimum
5 V input and maximum 800 mA load. This measurement is shown in Figure 16. In this design only one pole and
one zero are used, so the maximum phase increase from the compensation will be 180 degrees. For a 60
degree phase margin, the power stage phase must be –120 degrees at its lowest point. Based on the target
6 kHz bandwidth, the measured power stage gain, KPS(fBW), is 24.84 dB and the phase is –110.3 degrees.
0
60
Gain
Phase
40
−30
−60
0
−90
Gain (dB)
20
−20
−120
−40
−150
−60
100
1k
10k
Frequency (Hz)
−180
100k
G016
Figure 16. Power Stage Gain and Phase of the Boost Converter
R3 is then chosen to set the compensation gain to be the reciprocal of the power stage gain at the target
bandwidth using Equation 38. C4 is then chosen to place a zero at 1/10 the target bandwidth with Equation 39.
In this case R3 is calculated to be 2.56 kΩ, the nearest standard value 2.55 kΩ is used. C4 is calculated at
0.104 µF and the nearest standard value 0.100 µF is used. Although not necessary because this design uses all
ceramic capacitors, a 100 pF capacitor is selected for C5 to add a high frequency pole at a frequency 100 times
the target bandwidth.
1
R3 =
KPS (¦BW )
æ
ö
20
R1
ç Gea ´
÷
´ 10
çç
÷÷
(R1 + R2 )
è
ø
(38)
1
C4 =
¦
2p ´ R3 ´ BW
10
(39)
CHARACTERISTICS OF THE BOOST CONVERTER
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100
95
VOUT (ac coupled) = 500mV/div
Efficiency (%)
90
85
80
75
IOUT = 200mA/div
70
65
60
VIN = 5 V
VIN = 12 V
55
50
0
0.4
0.8
1.2
Output Current (A)
1.6
2
Time - 1ms/div
G017
Figure 17. Efficiency vs Output Current
IL = 1A/div
Figure 18. Load Transient Response
IL = 1A/div
VOUT (ac coupled) = 100mV/div
VOUT (ac coupled) = 10mV/div
SW = 20V/div
SW = 20V/div
Time - 1ms/div
Time - 1ms/div
Figure 19. CCM PWM Operation
Figure 20. DCM PWM operation
VIN = 1V/div
IL = 200mA/div
EN = 2V/div
VOUT (ac coupled) = 20mV/div
SW = 10V/div
SW = 20V/div
VOUT = 10V/div
Time - 50ms/div
Time - 500ms/div
Figure 21. Pulse Skipping
Figure 22. Start Up
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180
60
40
120
20
60
0
0
−60
−20
−40
−60
100
Phase (°)
Gain (dB)
IOUT = 800 mA
5 V Gain
5 V Phase
15 V Gain
15 V Phase
−120
1k
10k
Frequency (Hz)
−180
100k
G023
Figure 23. Closed Loop Gain and Phase of the Boost Converter
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DESIGN GUIDE-STEP-BY-STEP DESIGN PROCEDURE OF SEPIC CONVERTER
Lb
TP4
VIN
La
VIN
6-18V
12V, 1A
1
TP5
49.9
TP2
VIN
86.6k
SYNC
SYNC
1
TP3
Not Populated
Figure 24. SEPIC Converter Application Schematic
The following parameters are used for a SEPIC converter design. These calculations are performed only for
CCM operation, and the use of a coupled inductor is assumed.
Table 2. Key Parameters of SEPIC Converter Example
PARAMETER
VALUE
Output Voltage
12 V
Input Voltage
6 V to 18 V, 12 V nominal
Maximum Output Current
1A
Transient Response 50% load step (ΔVOUT = 4%)
480 mV
Output Voltage Ripple (0.5% of VOUT)
60 mV
SELECTING THE SWITCHING FREQUENCY (R4)
A 500 kHz switching frequency (ƒSW) is selected for this design. Using Equation 1, R4 is calculated and the
nearest standard value 95.3 kΩ is used.
DUTY CYCLE
The duty cycle of a SEPIC converter is calculated with Equation 40. With the 6 V minimum input the duty cycle is
68% and with the 18 V maximum input voltage the duty cycle is 41%.
VOUT + VD
D=
VOUT + VD + VIN
(40)
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SELECTING THE INDUCTOR (L1)
With an estimated 85% efficiency, the input current is calculated with Equation 9 to be 2.35 A. With KIND of 0.3
and the maximum 18 V input the minimum inductance is calculated to be 10.5µH using Equation 41. The nearest
standard value of 12µH is used. As mentioned previously, this equation assumes a coupled inductor is used.
VIN max´ Dmin
L³
2 ´ ¦ SW ´ IINDC ´ KIND
(41)
The inductor ripple current is recalculated to be 615mA with Equation 42. The peak current is calculated to
3.69 A. The typical current limit is used as the saturation rating for the inductor used. The RMS current for La is
approximately the average input current 2.35 A. The RMS current for Lb is approximately the output current of
1 A. For this design a CoilCraft MSD1260-123 is used with 6.86 A saturation, 74 mΩ DCR and 3.12 A RMS
current rating for one winding.
V max´ Dmin
DIL = IN
2 ´ ¦ SW ´ L
(42)
DI ö æ
DI ö
æ
IL peak = ILa peak + ILb peak = ç IINDC + L ÷ + ç IOUT + L ÷
2 ø è
2 ø
è
(43)
CALCULATING THE MAXIMUM OUTPUT CURRENT
The maximum output current with the minimum input voltage 6 V, chosen inductance 12µH, 5.25 A minimum
current limit and estimated 85% efficiency is calculated to be 1.47 A using Equation 44.
(ILIM - DIL )
(ILIM - IINDC ´ KIND )
IOUT max =
=
æ
ö æ
ö
VOUT
VOUT
+ 1÷ ç
+ 1÷
ç
è VIN min´ hEST
ø è VIN min´ hEST
ø
(44)
SELECTING THE OUTPUT CAPACITOR (C8-C10)
To meet the 60 mV ripple specification, the minimum output capacitance is calculated to be 22.5µF with
Equation 45. This design uses ceramic output capacitors and the effects of ESR are ignored. To meet the
transient response of 500mA with less than 480mV voltage change and a 7kHz control loop bandwidth, the
minimum output capacitance is calculated to be 23.7µF using Equation 46. The RMS current is calculated with
Equation 22 to be 1.44 A. The output capacitors used in this design is 3 x 22 µF, 25 V X7R 1210 ceramic
capacitors. With voltage derating, the effective total output capacitance is estimated to be 30.4 µF.
Dmax ´ IOUT
COUT ³
¦ SW ´ VRIPPLE
(45)
COUT ³
DITRAN
2p ´ ¦BW ´ DVTRAN
(46)
SELECTING THE SERIES CAPACITOR (C6)
The series capacitor is chosen to limit the ripple current to 5% of the maximum input voltage. Using Equation 47
the minimum capacitance is 1.5 µF. Using Equation 48 the RMS current is calculated to be 1.63A. A 2.2 µF
ceramic capacitor in a 1206 package is selected.
IOUT ´ Dmax
CP ³
0.05 ´ VIN max ´ ƒSW
(47)
ICPrms = IINDC ´
(1 - Dmax)
Dmax
(48)
SELECTING THE INPUT CAPACITOR (C2, C7)
Based on the minimum 4.7µF ceramic recommended for the TPS55340, a 10µF X7R input capacitor is used with
an additional 0.1µF placed close to the VIN and GND pins. With an estimated 6 µF capacitance after voltage
derating, the input ripple voltage is calculated to be 39.9mV using Equation 49. The RMS current of the input
capacitance is calculated to be 0.177 A with Equation 50.
22
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VIripple =
ICIrms =
SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012
DIL
4 ´ ¦ SW ´ CIN
(49)
DIL
12
(50)
SELECTING THE SCHOTTKY DIODE (D1)
The selected diode must have a minimum breakdown voltage (VBR) calculated with Equation 51 which is 30.5 V
in this design. The average current rating is recommended to be greater than the maximum output current. With
the maximum 18 V input, average current is calculated to be 2.6 A using Equation 17. The package must also be
capable of handling the power dissipation. With an estimated 0.5V forward voltage, power dissipation is
calculated with Equation 26 to be 500mW. Diodes Inc B340B is chosen with a 40 V, 3 A rating in a SMB
package.
VBR = VO + VINmax + VF
(51)
SETTING THE OUTPUT VOLTAGE (R1, R2)
With R2 fixed at 10 kΩ using Equation 25 the nearest standard value of 86.6 kΩ is chosen for R1.
SETTING THE SOFT-START TIME (C3)
The recommended 0.047µF soft-start capacitor is used.
MOSFET RATING CONSIDERATIONS
In a SEPIC converter the MOSFET must be rated to handle the sum of the input and output voltages. In this
design with the maximum input voltage of 18 V and output voltage of 12 V the FET will see approximately 30 V.
A 10% tolerance is recommended to account for any ringing. The 40V rating of the TPS55340 power MOSFET
comfortably satisfies this requirement.
COMPENSATING THE CONTROL LOOP (R3, C4)
This design was compensated by measuring the frequency response of the power stage at the lowest input
voltage of 6 V and choosing the components for the desired bandwidth. The lowest right half plane zero (ƒRHPZ)
is calculated to be 36.7kHz with Equation 52. Using the recommendation to limit the bandwidth to 1/3 of ƒRHPZ
the maximum recommended is 12.2kHz.
VOUT
IOUT
¦RHPZ =
2
æ D ö
2´ p´L ´ç
÷
ç (1 - D ) ÷
è
ø
(52)
This design also uses only one pole and one zero. In order to achieve approximately 60 degrees of phase
margin, the power stage phase must be no lower than approximately –120 degrees at the desired bandwidth. To
ensure a stable design, R3 was initially set to 1kΩ and C4 was 1µF. Figure 25 shows the measurement of the
power stage At 7kHz the power stage has a gain of 19.52 dB and phase of –118.1 degrees.
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23
TPS55340
SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012
www.ti.com
180
60
6 V Input Gain
6 V Input Phase
40
120
0
0
Phase (°)
60
Gain (dB)
20
−20
−60
−40
−120
−60
100
1k
−180
100k
10k
Frequency (Hz)
G025
Figure 25. SEPIC Power Stage Gain and Phase
As there are no changes in the transconductance amplifier, the equations used to calculate the external
compensation components in a boost design can be used in the SEPIC design. Using the maximum Gea from
the electrical specification of 440 µmho, Equation 38 calculates the nearest standard value of R3 to be 2.37 kΩ.
Using Equation 39, C4 is calculated to the nearest standard value of 0.1 µF.
CHARACTERISTICS OF THE SEPIC CONVERTER
100
95
IOUT = 500mA/div
Efficiency (%)
90
85
VOUT (ac coupled) = 200mV/div
80
75
70
65
VIN = 6 V
VIN = 12 V
VIN = 18 V
60
55
50
0
0.2
0.4
0.6
0.8
Output Current (A)
1
1.2
Time - 500ms/div
G026
Figure 26. Efficiency vs Output Current
Figure 27. Load Transient Response
VIN = 2V/div
SW = 10V/div
EN = 2V/div
ILb = 1A/div
SW = 20V/div
ILa = 1A/div
VOUT = 5V/div
VOUT (ac coupled) = 50mV/div
Time - 2ms/div
Time - 1ms/div
Figure 28. CCM PWM Operation
24
Figure 29. Output Voltage Soft-start
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SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012
60
180
40
120
20
60
0
0
−60
−20
−40
−60
100
Phase (°)
Gain (dB)
www.ti.com
6 V Gain
6 V Phase
18 V Gain
18 V Phase
−120
1k
10k
Frequency (Hz)
−180
100k
G030
Figure 30. Closed Loop Gain and Phase of the SEPIC Converter
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25
TPS55340
SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012
www.ti.com
REVISION HISTORY
Changes from Original (May 2012) to Revision A
Page
•
Added PWP package ............................................................................................................................................................ 1
•
Added HTSSOP-14 package to FEATURES ........................................................................................................................ 1
•
Added 14-pin HTSSOP package to DESCRIPTION ............................................................................................................ 1
•
Added paragraph to end of DESCRIPTION ......................................................................................................................... 1
•
Added PWP package to PIN ASSIGNMENTS ..................................................................................................................... 2
•
Added PWP package to PIN FUNCTIONS .......................................................................................................................... 2
•
Added HTSSOP package to THERMAL INFORMATION .................................................................................................... 4
Changes from Revision A (October 2012) to Revision B
•
26
Page
Corrected the pin numbers to the QFN-16 Package drawing .............................................................................................. 2
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPS55340PWP
ACTIVE
HTSSOP
PWP
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
55340
TPS55340PWPR
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
55340
TPS55340RTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
55340
TPS55340RTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
55340
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Oct-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPS55340PWPR
HTSSOP
PWP
14
2000
330.0
12.4
TPS55340RTER
WQFN
RTE
16
3000
330.0
TPS55340RTET
WQFN
RTE
16
250
180.0
6.9
5.6
1.6
8.0
12.0
Q1
12.4
3.3
3.3
1.1
8.0
12.0
Q2
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Oct-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS55340PWPR
HTSSOP
PWP
14
2000
367.0
367.0
35.0
TPS55340RTER
WQFN
RTE
16
3000
367.0
367.0
35.0
TPS55340RTET
WQFN
RTE
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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