WOLFSON XM9707CFT/V

WM9707
AC’97 Revision 2.1 Audio Codec with SPDIF Output
Advanced Information, January 2001, Rev 2.2
DESCRIPTION
AC’97 FEATURES
•
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•
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WM9707 is a high-quality stereo audio codec compliant with
the AC’97 Revision 2.1 specification. It performs full duplex
18-bit codec functions and supports variable sample rates
from 8 to 48k samples/s and offers excellent quality with
high SNR. Additional features include 3D sound
enhancement, line-level outputs, hardware sample rate
conversion, master/slave mode operation and SPDIF
output.
WM9707 is interchangeable with AC’97 codecs from
Wolfson and other suppliers. The WM9707 is fully operable
on 3.3V or 5V or mixed 3.3/5V supplies, and is packaged in
the industry standard 48-pin TQFP package with 7mm body
size.
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3.3V or 5V operation
18-bit stereo codec
S/N ratio > 95dB
Multiple stereo input mixer
Mono and stereo volume control
48-pin TQFP package
Power management features
Very low standby power
Variable rate audio (VRA) support
Analogue 3D stereo enhancement
Line level outputs
Supports Rev. 2.1 specified modem sample rates
and filtering
Master/slave ID selection
PC-beep connection when device held reset
SPDIF digital output
BLOCK DIAGRAM
VOL/
MUTE
VOL/
MUTE
Σ
VOL/
MUTE
(35,36) LINEOUT
VOL/
MUTE
(39,41) LNLVLOUT
Σ
KEY:
MONO
STEREO
VOL/
MUTE
MUX
(37) MONOOUT
VOL/
MUTE
VOL/
MUTE
STEREO
DAC
SRC
(47) EAPD
3D
VOL/
MUTE
VOL/
MUTE
VOL/
MUTE
(6) BITCLK
Σ
Σ
SERIAL
I/F
WM9707
(10) SYNC
(8) SDATAIN
(5) SDATAOUT
(11) RESETB
VOL/
MUTE
(44) SPDIF ENABLE
VOL/
MUTE
CD (18,20)
LINEIN (23,24)
VIDEO (16,17)
AUX (14,15)
PHONE (13)
PCBEEP (12)
MIC1 (21)
RECORD
MUX
AND
MUTE
MUX
MIC2 (22)
(48) SPDIF
VOL
0dB/
20dB
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
http://www.wolfson.co.uk
STEREO
ADC
SRC
MASTER/
SLAVE
SELECT
OSC
(45) CID
(2) XTLIN
(3) XTLOUT
Advanced Information data sheets contain
preliminary data on new products in the
preproduction phase of development.
Supplementary data will be published at a
later date.
2001 Wolfson Microelectronics Ltd.
WM9707
Advanced Information
41
MONOOUT
42
AVDD2
43
NC
LNLVLOUTR
44
ORDERING INFORMATION
LNLVLOUTL
AVSS2
45
SPDIF ENABLE
46
NC
47
NC
48
CID
SPDIF
EAPD
PIN CONFIGURATION
40
39
38
37
5
32
CAP2
BITCLK
6
31
NC
DVSS2
7
30
NC
SDATIN
8
29
NC
DVDD2
9
28
VREFOUT
SYNC
10
27
VREF
RESETB
11
26
AVSS1
PCBEEP
12
25
AVDD1
13
14
15
16
17
18
19
20
21
22
23
24
LINEINL
CX3D1
SDATAOUT
LINEINR
33
MIC2
4
MIC1
CX3D2
DVSS1
CDR
34
CDGND
3
CDL
LINEOUTL
XTLOUT
VIDEOR
35
AUXR
LINEOUTR
2
VIDEOL
36
XTLIN
AUXL
1
PHONE
DVDD1
DEVICE
TEMP. RANGE
PACKAGE
XWM9707CFT/V
0 to 70oC
48-pin TQFP
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
As per specifications IPC/JEDEC J-STD-020A and JEDEC A113-B, this product requires specific storage conditions prior to
surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in
vacuum-sealed moisture barrier bags.
CONDITION
MIN
MAX
Digital supply voltage
-0.3V
+7V
Analogue supply voltage
-0.3V
+7V
Voltage range digital inputs
DVSS -0.3V
DVDD +0.3V
Voltage range analogue inputs
AVDD -0.3V
AVDD +0.3V
0oC
+70oC
-65oC
+150oC
Operating temperature range, TA
Storage temperature
Package body temperature (soldering 10 seconds)
+240oC
Package body temperature (soldering 2 minutes)
+183oC
Note:
1.
The digital supply voltage (DVDD) must always be less than or equal to the analogue supply voltage (AVDD).
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
2
WM9707
Advanced Information
Recommended Operating Conditions
PARAMETER
MIN
TYP
MAX
UNIT
Digital supply range
DVDD1, DVDD2
SYMBOL
TEST CONDITIONS
-10%
3.3 to 5.0
+10%
V
Analogue supply range
AVDD1, AVDD2
-10%
3.3 to 5.0
+10%
Digital ground
DVSS1, DVSS2
Analogue ground
AVSS1, AVSS2
0
0
Difference DVSS to AVSS
-0.3
0
V
V
V
+0.3
V
Analogue supply current
DVDD, AVDD = 5V
30
mA
Digital supply current
DVDD, AVDD = 5V
30
mA
Standby supply current (all PRs set)
DVDD, AVDD = 5V
10
uA
Analogue supply current
DVDD, AVDD = 3.3V
20
mA
Digital supply current
DVDD, AVDD = 3.3V
20
mA
Standby supply current (all PRs set)
DVDD, AVDD = 3.3V
10
uA
ELECTRICAL CHARACTERISTICS
Test Characteristics:
AVSS = 5V, GND = 0V …………..TA = 0oC to +70oC, unless otherwise stated
DVDD = 3.3V, GND = 0V …………..TA = 0oC to +70oC, unless otherwise stated
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (DVDD = 3.3 or 5.0V)
Input LOW level
VIL
AVSS -0.3
0.8
V
Input HIGH level
VIH
2.2
AVDD +0.3
V
0.10 x VDD
V
Output LOW
VOL
Output HIGH
VOH
0.90 x VDD
V
Analogue I/O Levels (Input Signals on any inputs, Outputs on LINEOUT L, R and MONOOUT)
Input level
Minimum input
impedance = 10k
AVSS
-100mV
Output level
Into 10kohm load
AVSS
+300mV
2/5 AVDD
AVDD
+100mV
V
Near rail to
rail
AVDD
-300mV
V
AVDD/2
3/5 AVDD
Reference Levels
Reference input/output
CAP2
CAP2 impedance
V
75
kohms
Mixer reference
VREF
Buffered
CAP2
V
MIC reference
VREFOUT
Buffered
CAP2
V
MIDBUFF current sink
(pins VREF and VREFOUT)
AVDD = 5V
-5
-15
mA
MIDBUFF current source
(pins VREF and VREFOUT)
AVDD = 5V
5
15
mA
MIDBUFF current source
(pins VREF and VREFOUT)
AVDD = 3.3V
10
mA
MIDBUFF current sink
(pins VREF and VREFOUT)
AVDD = 3.3V
-10
mA
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
3
WM9707
Advanced Information
Test Characteristics:
AVSS = 5V, GND = 0V …………..TA = 0oC to +70oC, unless otherwise stated
DVDD = 3.3V, GND = 0V …………..TA = 0oC to +70oC, unless otherwise stated
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC Circuit Specifications (AVDD = 5V) 48kHz sampling
SNR A-weighted (Note 1)
85
Full scale output voltage
VREF = 2.5V
THD
-3dBfs input
Frequency response
74 (0.02%)
95
dBv
1.0
Vrms
90
dBv
20
19,200
Hz
Transition band
19,200
28,800
Hz
Stop band
28,800
Hz
Out of band rejection
-40
dB
Spurious tone reduction
-100
dB
40
dB
PSRR
20 to 20kHz
ADC Circuit Specifications (AVDD = 5V) 48kHz sampling
SNR A-weighted (Note 1)
ADC input for full scale output
THD
75
VREF = 2.5V
-6dBv input
Frequency response
74
92
dB
1.0
Vrms
95
dB
20
19,200
Hz
Transition band
19,200
28,800
Hz
Stop band
28,800
Stop band rejection
PSRR
Hz
-74
20 to 20kHz
dB
40
dB
Mixer Circuit Specifications (AVDD = 5V) 48kHz sampling
SNR CD path A-weighted (Note
1)
90
100
dB
SNR Other paths A-weighted
(Note 1)
85
95
dB
AVSS
1.0
1.0
1.8
74
90
Maximum input voltage
Maximum output voltage on
LINEOUT
THD
0dBv input
Frequency response (+/-1dB)
20
AVDD
Vrms
Vrms
dB
20,000
Hz
Input impedance (CD inputs)
At any gain
15
kohm
Input impedance (other mixer
inputs)
At max gain
10
20
kohm
At 0db gain
50
100
kohm
Input impedance MIC inputs
At max gain
10
30
kohm
At 0db gain
55
110
kohm
50
dB
PSRR
20 to 20kHz
DAC Circuit Specifications (AVDD = 3.3V) 48kHz sampling
SNR A-weighted (Note 1)
92
dB
Full scale output voltage
VREF = 1.65V
0.7
Vrms
THD
-3dBFS input
85
dB
Frequency response
Hz
Transition band
Hz
Stop band
Hz
Out of band rejection
dB
Spurious tone reduction
PSRR
WOLFSON MICROELECTRONICS LTD
dB
20 to 20kHz
dB
AI Rev 2.2 January 2001
4
WM9707
Advanced Information
Test Characteristics:
AVSS = 5V, GND = 0V …………..TA = 0oC to +70oC, unless otherwise stated
DVDD = 3.3V, GND = 0V …………..TA = 0oC to +70oC, unless otherwise stated
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Circuit Specifications (AVDD = 3.3V) 48kHz sampling
SNR A-weighted (Note 1)
ADC input for full scale output
THD
VREF = 1.65V
-6dBv input
Frequency response
85
dB
0.7
Vrms
80
dB
20
19,200
Hz
Transition band
19,200
28,800
Hz
Stop band
28,800
Stop band rejection
PSRR
Hz
-74
20 to 20kHz
dB
40
dB
SNR CD path A-weighted
(Note 1)
95
dB
SNR Other paths A-weighted
(Note 1)
90
dB
Maximum input voltage
0.6
Vrms
Maximum output voltage on
LINEOUT
1.2
Vrms
85
dBv
Mixer Circuit Specifications (AVDD = 3.3V) 48kHz sampling
THD (Note 2)
-3.6dBv input
Frequency response (+/-1dB)
20
20,000
Hz
Input impedance (CD inputs)
At any gain
Input impedance (other Mixer
inputs)
At max gain
20
kohm
At 0db gain
100
kohm
Input impedance MIC inputs
At max gain
30
kohm
At 0db gain
110
kohm
20 to 20kHz
50
dB
Crystal clock
24.576
MHz
BIT_CLK frequency
12.288
MHz
48.0
kHz
PSRR
15
kohm
Clock Frequency Range
SYNC frequency
Notes:
1.
SNR is the ratio of 0dB signal output to the output level with no signal, measured A-weighted over a 20Hz to 20kHz
bandwidth.
2.
Inputs are scaled for AVDD eg; 0dBv at 5.0V is equivalent to –3.6dBv at 3.3V.
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
5
WM9707
Advanced Information
PIN DESCRIPTION
PIN
NAME
1
DVDD1
2
XTLIN
3
XTLOUT
4
DVSS1
5
SDATAOUT
6
TYPE
Supply
DESCRIPTION
Digital positive supply
Digital input
Clock crystal connection or clock input (XTAL not used)
Digital output
Clock crystal connection
Supply
Digital ground supply
Digital input
Serial data input
BITCLK
Digital output (master)
Digital input (slave)
Serial interface clock output to AC’97 controller
or input from AC’97 master codec
7
DVSS2
Supply
Digital ground supply
8
SDATAIN
Digital output
Serial data output to AC’97 controller
9
DVDD2
Supply
Digital positive supply
10
SYNC
Digital input
Serial interface sync pulse from AC’97 controller
11
RESETB
Digital input
NOT reset input (active low, resets registers)
12
PCBEEP
Analogue input
Mixer input, typically for PCBEEP signal
13
PHONE
Analogue input
Mixer input, typically for PHONE signal
14
AUXL
Analogue input
Mixer input, typically for AUX signal
15
AUXR
Analogue input
Mixer input, typically for AUX signal
16
VIDEOL
Analogue input
Mixer input, typically for VIDEO signal
17
VIDEOR
Analogue input
Mixer input, typically for VIDEO signal
18
CDL
Analogue input
Mixer input, typically for CD signal
19
CDGND
Analogue input
CD input common mode reference (ground)
20
CDR
Analogue input
Mixer input, typically for CD signal
21
MIC1
Analogue input
Mixer input with extra gain if required
22
MIC2
Analogue input
Mixer input with extra gain if required
23
LINEINL
Analogue input
Mixer input, typically for LINE signal
24
LINEINR
Analogue input
Mixer input, typically for LINE signal
25
AVDD1
Supply
Analogue positive supply
26
AVSS1
Supply
Analogue ground supply, chip substrate
27
VREF
Analogue output
Buffered CAP2
28
VREFOUT
Analogue output
Reference for microphones; buffered CAP2
29
NC
No internal connection
30
NC
No internal connection
31
NC
32
CAP2
Analogue input
Reference input/output; pulls to midrail if not driven
33
CX3D1
Analogue output
Output pin for 3D difference signal
No internal connection
34
CX3D2
Analogue input
Input pin for 3D difference signal
35
LINEOUTL
Analogue output
Main analogue output for left channel
36
LINEOUTR
Analogue output
Main analogue output for right channel
37
MONOOUT
Analogue output
Main mono output
38
AVDD2
39
LNLVLOUTL
40
NC
41
LNLVLOUTR
42
AVSS2
Supply
Analogue positive supply
Analogue output
Left channel line level output
No internal connection
Analogue output
Right channel line level output
Supply
Analogue ground supply, chip substrate
43
NC
44
SPDIF ENABLE
Digital input
No internal connection
SPDIF ENABLE (internal pull-down)
45
CID
Digital input
Master/slave ID select (internal pull-up), Hi = master
46
NC
47
EAPD
Digital output
External amplifier powerdown/GPO
48
SPDIF
Digital output
SPDIF digital audio data output
WOLFSON MICROELECTRONICS LTD
No internal connection
AI Rev 2.2 January 2001
6
WM9707
Advanced Information
DETAILED TIMING DIAGRAMS
Test Characteristics:
AVDD = 5V, GND = 0V …………..TA = 0oC to +70oC, unless otherwise stated.
DVDD = 3.3V, GND = 0V …………..TA = 0oC to +70oC, unless otherwise stated.
All measurements are taken at 10% to 90% VDD, unless otherwise stated. All
the following timing information is guaranteed, not tested.
AC-LINK LOW POWER MODE
SLOT 1
SLOT 2
SYNC
BIT_CLK
SDATA_OUT
WRITE
TO 0X20
DON’T
CARE
DATA PR4
tS2_PDOWN
SDATA_IN
Figure 1 AC-Link Powerdown Timing
PARAMETER
SYMBOL
End of slot 2 to BITCLK SDATIN
low
tS2_PDOWN
MIN
TYP
MAX
UNIT
1.0
µs
MAX
UNIT
COLD RESET
tRST_LOW
tRST2CLK
RESETB
BIT_CLK
Figure 2 Cold Reset Timing
PARAMETER
SYMBOL
MIN
TYP
RESETB active low pulse width
tRST_LOW
1.0
µs
RESETB inactive to BIT_CLK
startup delay
tRST2_CLK
162.8
ns
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
7
WM9707
Advanced Information
WARM RESET
tSYNC_HIGH
tSYNC2CLK
SYNC
BIT_CLK
Figure 3 Warm Reset Timing
PARAMETER
SYMBOL
SYNC active high pulse width
tSYNC_HIGH
SYNC inactive to BIT_CLK startup
delay
tSYNC2_CLK
MIN
TYP
MAX
UNIT
µs
1.3
162.4
ns
CLOCK SPECIFICATIONS
tCLK_HIGH
tCLK_LOW
BIT_CLK
tCLK_PERIOD
tSYNC_HIGH
tSYNC_LOW
SYNC
tSYNC_PERIOD
Figure 4 Clock Specifications (50pF External Load)
Note: Worst case duty cycle restricted to 40/60.
PARAMETER
SYMBOL
MIN
BIT_CLK frequency
BIT_CLK period
TYP
MAX
12.288
tCLK_PERIOD
MHz
81.4
BIT_CLK output jitter
UNIT
ns
750
ps
BIT_CLK high pulse width
( See Note)
tCLK_HIGH
32.56
40.7
48.84
ns
BIT_CLK low pulse width
( See Note)
tCLK_LOW
32.56
40.7
48.84
ns
SYNC frequency
48.0
kHz
tSYNC_PERIOD
20.8
µs
SYNC high pulse width
tSYNC_HIGH
1.3
µs
SYNC low pulse width
tSYNC_LOW
19.5
µs
SYNC period
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
8
WM9707
Advanced Information
DATA SETUP AND HOLD (50pF EXTERNAL LOAD)
tSETUP
BIT_CLK
tHOLD
SYNC
SDATA_OUT
Figure 5 Data Setup and Hold (50pF External Load)
Note: Setup and hold time parameters for SDATA_IN are with respect to AC’97 Controller.
PARAMETER
SYMBOL
MIN
Setup to falling edge of BIT_CLK
tSETUP
15.0
TYP
MAX
UNIT
ns
Hold from falling edge of BIT_CLK
tHOLD
5.0
ns
SIGNAL RISE AND FALL TIMES
triseCLK
tfallCLK
BIT_CLK
triseSYNC
tfallSYNC
SYNC
triseDIN
tfallDIN
SDATA_IN
triseDOUT
tfallDOUT
SDATA_OUT
Figure 6 Signal Rise and Fall Times (50pF external load)
PARAMETER
SYMBOL
MIN
MAX
UNIT
BIT_CLK rise time
triseCLK
2
6
ns
BIT_CLK fall time
tfallCLK
2
6
ns
SYNC rise time
triseSYNC
2
6
ns
SYNC fall time
tfallSYNC
2
6
ns
SDATA_IN rise time
triseDIN
2
6
ns
SDATA_IN fall time
triseDIN
2
6
ns
SDATA_OUT rise time
triseDOUT
2
6
ns
SDATA_OUT fall time
tfallDOUT
2
6
ns
WOLFSON MICROELECTRONICS LTD
TYP
AI Rev 2.2 January 2001
9
WM9707
Advanced Information
SYSTEM INFORMATION
CD, VIDEO,
AUX, LINEINL/R
MIC1
PCBEEP
MIC2
22
21
12
PHONE
13
35
LINEOUTL/R
36
RESET
11
BITCLK
DIGITAL
SYNC
CONTROLLER
SDATAIN
SDATAOUT
CID
39
41
6
WM9707
10
{
AC’97
8
LNLVLOUTL/R
37
MONO_OUT
48
SPDIF OUTPUT
5
45
AUDIO SPDIF
TRANSFORMER
CIRCUIT
Figure 7 Revision 2.1 Compliant 2-Channel Codec
SDATAOUT
SDATAOUT
BITCLK
Front R data
LINEOUTL
BITCLK
SDATAIN_0
SDATAIN
WM9707
SDATAIN_1
SYNC
SYNC
PC I/O
CHIPSET RESET
OR AC’97
CONTROLLER
RESET
XTLOUT
XTLIN
Front L data
LINEOUTR
ID=0
Surround R data
LINEOUTL
SDATAOUT
BITCLK
SDATAIN
WM9707
SYNC
RESET
Surround L data
LINEOUTR
ID=1
Figure 8 WM9707 in a 4 Channel System
SDATAOUT
BITCLK
SDATAIN
SYNC
RESETB
PC I/O
CHIPSET
OR AC’97
CONTROLLER
Option of using RESETB
or SDATAIN to disable
NB CODEC
when docked.
CID
SYNC
RESETB
SDATAOUT
BITCLK
SDATAIN
LINEOUTL
SDATAOUT
BITCLK
SDATAIN WM9707
LINEOUTR
ID=0
WM9707
SYNC
RESETB
ID=0
NOTEBOOK/
LAPTOP
If pin CID is not driven
then CODEC ID
defaults to 0.
When docked CID is
pulled low making
CODEC a ’slave’ (1)
stopping BITCLK
DOCKING STATION
Figure 9 WM9707 in a Docking Station System
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
10
WM9707
Advanced Information
DEVICE DESCRIPTION
INTRODUCTION
The WM9707 is fully compliant with Revision 2.1 of the AC’97 specification.
The WM9707 comprises a stereo 18-bit Codec, (that is, 2 ADCs and 2 DACs) a comprehensive
analogue mixer with 4 sets of stereo inputs, phone, 2 microphone, and PC-beep inputs. Additionally,
on-chip reference generation circuits generate the necessary bias voltages for the device, and a
bidirectional serial interface allows transfer of control data and DAC and ADC words to and from the
AC’97 controller. The WM9707 supports 18-bit resolution within the DAC and ADC functions, but the
AC’97 serial interface specification allows any word length up to 20-bits to be written to, or read from,
the AC’97 Codec. These words are MSB justified, and any LSBs not used will simply default to 0.
Normally it is anticipated that 16-bit words will be used in most PC type systems. Therefore, for the
DAC, 16-bit words will be downloaded into the Codec from the controller, along with padding of 0s to
make the 16-bit word up to 20-bit length. In this case, the WM9707 will process the 16-bit word along
with 0 padding bits in the 2 LSB locations (to make 18-bit). At the ADC output, WM9707 will provide
an 18-bit word, again with 0s in the two LSB locations (20-bit). The AC’97 controller will then ignore
the 4 LSBs of the 20-bit word. When the WM9707 is interrogated at Register 00h, it responds
indicating it is an 18-bit device.
The WM9707 has the ADC and DAC functions implemented using oversampled, or sigma-delta
converters, and uses on-chip digital filters to convert these 1-bit signals to and from the 48ks/s 16/18bit PCM words that the AC’97 controller requires. The digital parts of the device are powered
separately from the analogue to optimise performance, and 3.3V digital and 5V analogue supplies
may be used on the same device to further optimise performance. Digital IOs are 5V tolerant when
the analogue supplies are 5V, so the WM9707 may be connected to a controller running on 5V
supplies, but use 3.3V for the digital section of WM9707. WM9707 is also capable of operating with a
3.3V supply only (digital and analogue).
An internally generated midrail reference is provided at pin CAP2 which is used as the chip
reference. This pin should be heavily decoupled. Refer to Figure 17 for more details.
The WM9707 is not limited to PC-only applications. The ability to power down sections of the device
selectively, and the option to choose alternative master clock, and hence sample rates, means that
many alternative applications in areas such as telecomms, may be anticipated.
Additional features added to the Intel AC’97 specification, such as the EAPD (External Amplifier
Powerdown) bit, internal connection of PC-beep to the outputs in the case where the device is reset,
are supported, along with optional features such as variable sample rate support and SPDIF output.
3D STEREO ENHANCEMENT
This device contains a stereo enhancement circuit, designed to optimise the listening experience
when the device is used in a typical PC operating environment. That is, with a pair of speakers
placed either side of the monitor with little spatial separation. This circuit creates a difference signal
by differencing left and right channel playback data, then filters this difference signal using lowpass
and highpass filters whose time constants are set using external capacitors connected to the CX3D
pins 33 and 34. Typically the values of 100nF and 47nF set highpass and lowpass poles at about
100Hz and 1kHz respectively. This frequency band corresponds to the range over which the ear is
most sensitive to directional effects.
The filtered difference signal is gain adjusted by an amount set using the 4-bit value written to
Register 22h bits 3 to 0. Value 0h is disable, value Fh is maximum effect. Typically a value of 8h is
optimum. The user interface would most typically use a slider type of control to allow the user to
adjust the level of enhancement to suit the program material. Bit D13 3D in Register 20h is the
overall 3D enable bit. The capability Register 00h reads back the value 11000 in bits D14 to D10.
This corresponds to decimal 24, which is registered with Intel as Wolfson Stereo Enhancement.
Note that the external capacitors setting the filtering poles applied to the difference signal may be
adjusted in value, or even replaced with a direct connection between the pins. If such adjustments
are made, then the amount of difference signal fed back into the main signal paths may be
significant, and can cause large signals which may limit, distort, or overdrive signal paths or
speakers. Adjust these values with care, to select the preferred acoustic effect.
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There is no provision for pseudo-stereo effects. Mono signals will have no enhancement applied
(if the signals are in phase and of the same amplitude).
Signals from the PCM DAC channels can have stereo enhancement applied. It can also be bypassed
if desired. This control is enabled by setting the POP bit in Register 20h.
VARIABLE SAMPLE RATE SUPPORT
The DACs and ADCs on this device support all the recommended sample rates specified in the Intel
Revision 2.1 specification for audio rates. The default rate is 48ks/s. If alternative rates are selected
and variable rate audio is enabled (Register 2Ah, bit 0), the AC’97 interface continues to run at 48k
words per second, but data is transferred across the link in bursts such that the net sample rate
selected is achieved. It is up to the AC’97 Revision 2.1 compliant controller to ensure that data is
supplied to the AC link, and received from the AC link, at the appropriate rate.
The device supports on demand sampling. That is, when the DAC signal processing circuits need
another sample, a sample request is sent to the controller which must respond with a data sample in
the next frame it sends. For example, if a rate of 24ks/s is selected, on average the device will
request a sample from the controller every other frame, for each of the stereo DACs. Note that if an
unsupported rate is written to one of the rate registers, the rate will default to the nearest rate
supported. The Register will then respond when interrogated with the supported rate the device has
defaulted to.
The left and right channels of the ADCs and DACs always sample at the same rate.
AUDIO
SAMPLE RATE
CONTROL VALUE
D15-D0
8000
1F40
11025
2B11
16000
3E80
22050
5622
44100
AC44
48000
BB80
Table 1 Variable Sample Rates Supported
SPDIF DIGITAL AUDIO DATA OUTPUT
Pin 48 may be used to output the PCM DAC playback data in SPDIF (IEC958) digital data format. In
order to enable this output, bit SPDF in Register 5Ch should be set or pin 44 pulled high.
Additionally, a bit SCMS in Register 5Ch may also be set, which removes the copyright flag in the
IEC958 data, allowing serial copy protect mechanisms to be implemented. Note that this data output
will only operate at the SYNCH rate and so only supports 48ks/s operation. The PCM DACs continue
to function normally when SPDIF output is enabled.
GAIN CONTROL REGISTER LOCATION
PGA
CONTROL REGISTER
MUTE DEFAULT
DAC
18h
Mixer
72h
Muted (bit-15)
Not-muted (bit-15)
Volume
02h
Muted (15)
Table 2 Gain Control Register Location
MASTER/SLAVE ID SUPPORT
WM9707 supports operation as either a master or a slave codec. Configuration of the device as
either a master or as a slave, is selected by tying the CID pin 45 on the package.
Fundamentally, a device identified as a master (ID = 0) produces BITCLK as an output, whereas a
slave (any other ID) must be provided with BITCLK as an input. This has the obvious implication that
if the master device on an AC link is disabled, the slave devices cannot function.
The AC’97 Revision 2.1 specification defines that the CID pin has inverting sense, and are provided
with internal weak pull ups. Therefore, if no connections are made to the CID pin, then the pin pulls hi
and an ID = 0 is selected, i.e. master. External connects to ground will select other IDs.
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PIN 45 CID
ID
SELECTED
MASTER OR
SLAVE
BITCLK
NC
0
Master
Output
Ground
1
Slave
Input
Table 3 ID Selection
CONTROL INTERFACE
A digital interface has been provided to control the WM9707 and transfer data to and from it. This
serial interface is compatible with the Intel AC’97.
The main control interface functions are:
•
•
•
Control of analogue gain and signal paths through the mixer
Bi-directional transfer of ADC and DAC words to and from AC’97 controller
Selection of Powerdown down modes.
AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL
The WM9707 incorporates a 5-pin digital serial interface that links it to the AC’97 controller. AC-link
is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input and output audio
streams, as well as control Register accesses employing a time division multiplexed (TDM) scheme.
The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams,
each with 20-bit sample resolution. With a minimum required DAC and ADC resolution of 16-bits,
AC’97 may also be implemented with 18 or 20-bit DAC/ADC resolution, given the headroom that the
AC-link architecture provides. The WM9707 provides support for 18-bit operation.
SLOT
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
TAG
CMD
ADR
CMD
DATA
PCM
LEFT
PCM
RIGHT
RSRVD
PCM
CENTRE
PCM
L SURR
PCM
R SURR
PCM
LFE
RSRVD
RSRVD
RSRVD
PCM L
(n+1)
PCM R
(n+1)
PCM C
(n+1)
RSRVD
RSRVD
RSRVD
SYNC
SDATA_OUT
CODEC ID
SDATA_IN
TAG
STATUS
ADDR
STATUS
DATA
PCM
LEFT
PCM
RIGHT
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
SLOTREQ 3-12
DATA PHASE
TAG PHASE
Figure 10 AC’97 Standard Bi-directional Audio Frame
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TAG PHASE
DATA PHASE
20.8µS (48kHz)
SYNC
12.288MHz
81.4nS
BIT_CLK
SDATA_OUT
VALID
FRAME
END OF PREVIOUS
AUDIO FRAME
SLOT(1)
SLOT(2)
SLOT(12)
’0’
(ID1)
(ID0)
19
TIME SLOT ’VALID’ BITS
(’1’ = TIME SLOT CONTAINS
VALID PCM DATA)
0
SLOT (1)
19
0
SLOT (2)
19
0
SLOT (3)
19
0
SLOT (12)
Figure 11 AC-link Audio Output Frame
The datastreams currently defined by the AC’97 specification include:
PCM playback - 2 output slots
2-channel composite PCM output stream
PCM record data - 2 input slots
2-channel composite PCM input stream
Control - 2 output slots
Control Register write port
Status - 2 input slots
Control Register read port
Optional modem line codec output 1 output slot
Modem line codec DAC input stream
Optional modem line codec input –
1 input slot
Modem line codec ADC output stream
Optional dedicated microphone input 1 input slot
Dedicated microphone input stream in support
of stereo AEC and/or other voice applications.
Synchronisation of all AC-link data transactions is signalled by the WM9707 controller. The WM9707
drives the serial bit clock onto AC-link, which the AC’97 controller then qualifies with a
synchronisation signal to construct audio frames.
SYNC, fixed at 48kHz, is derived by dividing down the serial clock (BIT_CLK). BIT_CLK, fixed at
12.288MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming
time slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-link
data, (WM9707 for outgoing data and AC’97 controller for incoming data), samples each serial bit on
the falling edges of BIT_CLK.
The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid
tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0
indicates that the corresponding time slot within the current audio frame has been assigned to a data
stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the
data, (the WM9707 for the input stream, AC’97 controller for the output stream), to stuff all bit
positions with 0s during that slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame.
The portion of the audio frame where SYNC is high is defined as the Tag Phase. The remainder of
the audio frame where SYNC is low is defined as the Data Phase. Additionally, for power savings, all
clock, sync, and data signals can be halted. This requires that the WM9707 be implemented as a
static design to allow its register contents to remain intact when entering a power savings mode.
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AC-LINK AUDIO OUTPUT FRAME (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data
targeting the WM9707’s DAC inputs, and control registers. As briefly mentioned earlier, each audio
output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot
containing 16-bits, which are used for AC-link protocol infrastructure.
OUTPUT TAG SLOT (16-BITS)
Bit (15)
Frame Valid
Bit (14)
Slot 1 Valid Command Address bit
(Primary Codec only)
Bit (13)
Slot 2 Valid Command Data bit
(Primary Codec only)
Bit (12:3)
Slot 3-12 Valid bits as defined by AC’97
Bit 2
Reserved
(Set to 0)
Bit (1:0)
2-bit Message ID field
(00 reserved for Primary; 01
indicates Secondary)
Within slot 0 the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the
entire audio frame. If the Valid Frame bit is a 1, this indicates that the current audio frame contains at
least one time slot of valid data. The next 12-bit positions sampled by the WM9707 indicate which of
the corresponding 12 time slots contain valid data.
In this way data streams of differing sample rates can be transmitted across AC-link at its fixed
48kHz audio frame rate. Figure 11 illustrates the time slot based AC-link protocol.
When the Codec is a slave device, bits 14 and 13 are not used to validate data in slots 1 and 2.
Instead, if the message ID bits (1:0) match the Codec ID then the address is valid and bit 19 from
slot 1 then indicates if slot 2 is valid.
WM9707 SAMPLES
SYNC ASSERTION HERE
SYNC
WM9707 SAMPLES
FIRST SDATA_OUT
BIT OF FRAME HERE
BIT_CLK
SDATA_OUT
VALID
FRAME
SLOT (1)
SLOT (2)
END OF PREVIOUS AUDIO FRAME
Figure 12 Start of an Audio Output Frame
A new audio output frame begins with a low to high transition of SYNC as shown in Figure 12. SYNC
is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK,
the WM9707 samples the assertion of SYNC. This falling edge marks the time when both sides of
AC-link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, AC’97
transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is
presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the WM9707 on the
following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent
sample points for both incoming and outgoing data streams are time aligned.
Baseline AC’97 specified audio functionality MUST ALWAYS sample rate convert to and from a fixed
48ks/s on the AC’97 controller. This requirement is necessary to ensure that interoperability between
the AC’97 controller and the WM9707, among other things, can be guaranteed by definition for
baseline specified AC’97 features.
SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slot bit positions
stuffed with 0s by the AC’97 controller.
In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC’97
controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s.
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As an example, consider an 8-bit sample stream that is being played out to one of the WM9707’s
DACs. The first 8 bit positions are presented to the DAC (MSB justified) followed by the next 12 bit
positions, which are stuffed with 0s by the AC’97 controller. This ensures that regardless of the
resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least
significant bits.
When mono audio sample streams are output from the AC’97 controller, it is necessary that BOTH
left and right sample stream time slots be filled with the same data.
SLOT 1: COMMAND ADDRESS PORT
The command port is used to control features, and monitor status for the WM9707 functions
including, but not limited to, mixer settings, and power management (refer to the Serial Interface
Register Map). The control interface architecture supports up to 64, 16-bit read/write registers,
addressable on even byte boundaries. Only the even Registers (00h, 02h, etc.) are valid. Odd
register read/write will have no effect on the WM9707.
Audio output frame slot 1 communicates control register address, and read/write command
information to the WM9707.
COMMAND ADDRESS PORT BIT ASSIGNMENTS
Bit (19)
Read/write command (1 = read, 0 = write)
Bit (18:12)
Control register index (64 16-bit locations, addressed on even
byte boundaries)
Bit (11:0)
Reserved (stuffed with 0s)
The first bit (MSB) sampled by the WM9707 indicates whether the current control transaction is a
read or write operation. The following 7 bit positions communicate the targeted control register
address. The trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the
AC’97 controller.
SLOT 2: COMMAND DATA PORT
The command data port is used to deliver 16-bit control register write data in the event that the
current command port operation is a write cycle. (As indicated by slot 1, bit 19).
Bit (19:4)
Control register write data (stuffed with 0s if current operation is
a read)
Bit (3:0)
Reserved (stuffed with 0s)
If the current command port operation is a read then the entire time slot must be stuffed with 0s by
the AC’97 controller.
SLOT 3: PCM PLAYBACK LEFT CHANNEL
Audio output frame slot 3 is the composite digital audio left playback stream. In a typical Games
Compatible PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the
AC’97 controller or host processor) with music synthesis output samples. If a sample stream of
resolution less than 20-bits is transferred, the AC’97 controller must stuff all trailing non-valid bit
positions within this time slot with 0s.
SLOT 4: PCM PLAYBACK RIGHT CHANNEL
Audio output frame slot 4 is the composite digital audio right playback stream. In a typical Games
Compatible PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the
AC’97 controller or host processor) with music synthesis output samples.
If a sample stream of resolution less than 20-bits is transferred, the AC’97 controller must stuff all
trailing non-valid bit positions within this time slot with 0s.
SLOT 5: OPTIONAL MODEM LINE CODEC
Audio output frame slot 5 contains the MSB justified modem DAC input data. This optional AC’97
feature is not supported in the WM9707, and if data is written to this location it is ignored. This may
be determined by the AC’97 controller interrogating the WM9707 Vendor ID registers.
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SLOTS 6 TO 9: SURROUND SOUND DATA
Audio output frame slots 6 to 9 are used to send surround sound data.
SLOTS 10 AND 11: LINE2 AND HANDSET DAC
These data slots are not supported.
SLOT 12: GPIO CONTROL
These data slots are not supported.
AC-LINK AUDIO INPUT FRAME (SDATA_IN)
TAG PHASE
DATA PHASE
20.8µS (48kHz)
SYNC
12.288MHz
81.4nS
BIT_CLK
SDATA_IN
CODEC
READY
END OF PREVIOUS
AUDIO FRAME
SLOT(1)
SLOT(2)
SLOT(12)
’0’
’0’
TIME SLOT ’VALID’ BITS
(’1’ = TIME SLOT CONTAINS
VALID PCM DATA)
’0’
19
0
SLOT (1)
19
0
SLOT (2)
19
0
SLOT (3)
19
0
SLOT (12)
Figure 13 AC-link Audio Input Frame
The audio input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC’97 controller. As is the case for audio output frame, each AC-link audio input frame
consists of 12, 20-bit time slots.
Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol
infrastructure.
Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the WM9707 is
in the Codec Ready state or not. If the Codec Ready bit is a 0, this indicates that the WM9707 is not
ready for normal operation. This condition is normal following the desertion of power on reset for
example, while the WM9707’s voltage references settle. When the AC-link Codec Ready indicator bit
is a 1, it indicates that the AC-link and the WM9707 control and status registers are in a fully
operational state. The AC’97 controller must further probe the Powerdown Control/Status Register to
determine exactly which subsections, if any, are ready.
Prior to any attempts at putting the WM9707 into operation the AC’97 controller should poll the first
bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that the WM9707 has gone
Codec Ready.
Once the WM9707 is sampled Codec Ready then the next 12 bit positions sampled by the AC’97
controller indicate which of the corresponding 12 time slots are assigned to input data streams, and
that they contain valid data. Figure 13 illustrates the time slot based AC-link protocol.
There are several subsections within the WM9707 that can independently go busy/ready. It is the
responsibility of the WM9707 controller to probe more deeply into the WM9707 register file to
determine which the WM9707 subsections are actually ready.
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THE WM9707 SAMPLES SYNC ASSERTION HERE
SYNC
AC’97 CONTROLLER SAMPLES FIRST
SDATA_IN BIT OF FRAME HERE
BIT_CLK
SDATA_IN
CODEC
READY
SLOT (1)
SLOT (2)
END OF PREVIOUS AUDIO FRAME
Figure 14 Start of an Audio Input Frame
A new audio input frame begins with a low to high transition of SYNC as shown in Figure 14. SYNC
is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK,
AC’97 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link
are aware of the start of a new audio frame. On the next rising of BIT_CLK, AC’97 transitions
SDATA_IN into the first bit position of slot 0 (“Codec Ready” bit). Each new bit position is presented
to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC’97 Controller on the
following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent
sample points for both incoming and outgoing data streams are time aligned.
SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned time slots) stuffed with 0s by the WM9707. SDATA_IN should be
sampled on the falling edges of BIT_CLK.
SLOT 1: STATUS ADDRESS PORT
The status port is used to monitor status for the WM9707 functions including, but not limited to, mixer
settings, and power management.
Audio input frame slot 1 echoes the control register index, for historical reference, for the data to
be returned in slot 2. (Assuming that slots 1 and 2 had been tagged valid by the WM9707 during slot
0).
STATUS ADDRESS PORT BIT ASSIGNMENTS:
Bit (19)
RESERVED (stuffed with 0s)
Bit (18:12)
Control register index (echo of register index for which data is
being returned)
Bit (11:2)
Variable sample rate SLOTREQ bits.
Bit (1:0)
RESERVED (stuffed with 0s)
The first bit (MSB) generated by the WM9707 is always stuffed with a 0. The following 7 bit positions
communicate the associated control register address. The next 10 bits support the AC’97 Rev 2.1
variable sample rate signalling protocol, and the trailing 2 bit positions are stuffed with 0s by AC’97.
SLOT 2: STATUS DATA PORT
The status data port delivers 16-bit control register read data.
Bit (19:4)
Control register read data (stuffed with 0s if tagged invalid by
WM9701)
Bit (3:0)
RESERVED (stuffed with 0s)
If slot 2 is tagged invalid by the WM9707, then the entire slot will be stuffed with 0s by the WM9707.
SLOT 3: PCM RECORD LEFT CHANNEL
Audio input frame slot 3 is the left channel output of the WM9707’s input Mux, post-ADC.
The WM9707 sends out its ADC output data (MSB first), and stuffs any trailing non-valid bit positions
with 0s to fill out its 20-bit time slot.
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SLOT 4: PCM RECORD RIGHT CHANNEL
Audio input frame slot 4 is the right channel output of the WM9707’s input Mux, post-ADC.
The WM9707’s ADCs can be implemented to support 16, 18, or 20-bit resolution.
The WM9707 ships out its ADC output data (MSB first), and stuffs any trailing non-valid bit positions
with 0s to fill out its 20-bit time slot.
SLOT 5: OPTIONAL MODEM LINE CODEC
Not supported by WM9707.
SLOT 6: OPTIONAL DEDICATED MICROPHONE RECORD DATA
Not supported by WM9707.
SLOTS 7 TO 12: RESERVED
Audio input frame slots 7 to 12 are reserved for future use and are always stuffed with 0s by the
WM9707.
AC-LINK LOW POWER MODE
The AC-link signals can be placed in a low power mode. When the WM9707’s Powerdown Register
26h, is programmed to the appropriate value, both BIT_CLK and SDATA_IN will be brought to, and
held at a logic low voltage level.
BIT_CLK and SDATA_IN are transitioned low immediately following the decode of the write to the
Powerdown Register 26h with PR4. When the AC’97 controller driver is at the point where it is ready
to program the AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid
stream in the audio output frame. At this point in time it is assumed that all sources of audio input
have also been neutralised.
The AC’97 controller should also drive SYNC and SDATA_OUT low after programming the WM9707
to this low power, halted mode.
Once the WM9707 has been instructed to halt BIT_CLK, a special wake up protocol must be used to
bring the AC-link to the active mode since normal audio output and input frames can not be
communicated in the absence of BIT_CLK.
WAKING UP THE AC-LINK
There are 2 methods for bringing the AC-link out of a low power, halted mode. Regardless of the
method, it is the AC’97 controller that performs the wake up task.
AC-link protocol provides for a Cold WM9707 Reset, and a Warm WM9707 Reset.
The current Powerdown state would ultimately dictate which form of WM9707 reset is appropriate.
Unless a cold or register reset (a write to the Reset Register 00h) is performed, wherein the WM9707
registers are initialised to their default values, registers are required to keep state during all
Powerdown modes.
Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not occur
for a minimum of 4 audio frame times following the frame in which the Powerdown was triggered.
When AC-link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit 15).
COLD WM9707 RESET
A cold reset is achieved by asserting RESETB for the minimum specified time (1µs). By driving
RESETB low, BIT_CLK, and SDATA_OUT will be activated, or re-activated as the case may be, and
all the WM9707 control registers will be initialised to their default power on reset values.
RESETB is an asynchronous WM9707 input.
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WARM WM9707 RESET
A warm WM9707 reset will re-activate the AC-link without altering the current WM9707 register
values. A warm reset is signalled by driving SYNC high for a minimum of 1µs in the absence of
BIT_CLK.
Within normal audio frames SYNC is a synchronous input. In the absence of BIT_CLK, SYNC is
treated as an asynchronous input used in the generation of a warm reset to the WM9707. The
WM9707 will not respond with the activation of BIT_CLK until SYNC has been sampled low again by
the WM9707. This will preclude the false detection of a new audio frame.
SERIAL INTERFACE REGISTER MAP DESCRIPTION
(See Table 17)
The serial interface bits perform control functions described as follows: The register map is fully
specified by the AC’97 specification, and this description is simply repeated below, with optional
unsupported features omitted.
RESET REGISTER (INDEX 00h)
Writing any value to this register performs a register reset, which causes all registers to revert to their
default values. Reading this register returns the ID code of the part, indication of modem support (not
supported by the WM9707) and a code for the type of 3D stereo enhancement.
The ID decodes the capabilities of the WM9707 based on the following:
BIT
FUNCTION
ID0
Dedicated Mic PCM in channel
0
ID1
Modem line codec support
0
ID2
Bass and treble control
0
ID3
Simulated stereo (mono to stereo)
0
ID4
Headphone out support
1
ID5
Loudness (bass boost) support
0
ID6
18-bit DAC resolution
1
ID7
20-bit DAC resolution
0
ID8
18-bit ADC resolution
1
ID9
20-bit ADC resolution
SE4...SE0
Wolfson Microelectronics 3D enhancement
VALUE ON
WM9707
0
11000
Table 4 Reset Register Function
Note that the WM9707 defaults to indicate 18-bit compatibility.
PLAY MASTER VOLUME REGISTERS (INDEX 02h, 04h AND 06h)
These registers manage the output signal volumes. Register 02h controls the stereo master volume
(both right and left channels), Register 04h controls the optional stereo headphone out, and Register
06h controls the mono volume output. Each step corresponds to 1.5dB. The MSB of the register is
the mute bit. When this bit is set to 1 the level for that channel is set at -∞dB.
ML5 to ML0 is for left channel level, MR5 to MR0 is for the right channel and MM5 to MM0 is for the
mono out channel.
Support for the MSB of the volume level is not provided by the WM9707. If the MSB is written to,
then the WM9707 detects when that bit is set and sets all 4 LSBs to 1s. Example: If the driver writes
a 1xxxxx the WM9707 interprets that as x11111. It will also respond when read with x11111 rather
than 1xxxxx, the value written to it. The driver can use this feature to detect if support for the 6th bit is
there or not.
The default value of both the mono and the stereo registers is 8000h (1000 0000 0000 0000), which
corresponds to 0dB gain with mute on.
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MUTE
MX4...MX0
0
0 0000
FUNCTION
0dB attenuation
0
0 0001
1.5dB attenuation
0
1 1111
46.5dB attenuation
1
x xxxx
∞dB attenuation
Table 5 Volume Register Function
MASTER TONE CONTROL REGISTERS (INDEX 08h)
Optional register for support of tone controls (bass and treble). The WM9707 does not support bass
and treble and writing to this register will have no effect, reading will result in all zeros.
PC BEEP REGISTER (INDEX 0Ah)
This controls the level for the PC-beep input. Each step corresponds to approximately 3dB of
attenuation. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel
is set at -∞dB.
WM9707 defaults to the PC-beep path being muted, except during reset when the path is open, so
an external speaker should be provided within the PC to alert the user to power on self-test
problems.
MUTE
PV3...PV0
0
0000
FUNCTION
0dB attenuation
0
1111
45dB attenuation
1
xxxx
∞dB attenuation
Table 6 PC-beep Register Function
ANALOGUE MIXER INPUT GAIN REGISTERS (INDEX 0Ch - 18h AND 72h)
This controls the gain/attenuation for each of the analogue inputs and mixer PGA. Each step
corresponds to approximately 1.5dB. The MSB of the register is the mute bit. When this bit is set to 1
the level for that channel is set at -∞dB.
REGISTER 0Eh (MIC VOLUME REGISTER)
This has an extra bit that is for a 20dB boost. When bit 6 is set to 1 the 20dB boost is on. The default
value is 8008h, which corresponds to 0dB gain with mute on.
The default value for the mono registers is 8008h, which corresponds to 0dB gain with mute on. The
default value for stereo registers is 8808h, which corresponds to 0dB gain with mute on.
MUTE
GX4...GX0
FUNCTION
0
00000
+12dB gain
0
01000
0dB gain
0
11111
-34.5dB gain
1
xxxxx
-∞dB gain
Table 7 Mixer Gain Control Register Function
RECORD SELECT CONTROL REGISTER (INDEX 1Ah)
Used to select the record source independently for right and left (see Table 8). The default value is
0000h, which corresponds to Mic in.
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SR2 TO SR0
RIGHT RECORD SOURCE
SL2 TO SL0
LEFT RECORD SOURCE
0
Mic
0
Mic
1
CD in (R)
1
CD in (L)
2
Video in (R)
2
Video in (L)
3
Aux in (R)
3
Aux in (L)
4
Line in (R)
4
Line in (L)
5
Stereo mix (R)
5
Stereo mix (L)
6
Mono mix
6
Mono mix
7
Phone
7
Phone
Table 8 Record Select Register Function
RECORD GAIN REGISTERS (INDEX 1Ch)
1Ch is for the stereo input and 1Eh is for the optional special purpose correlated audio Mic channel.
Each step corresponds to 1.5dB. 22.5dB corresponds to 0F0Fh. The MSB of the register is the mute
bit. When this bit is set to 1, the level for that channel(s) is set at -∞dB.
The default value is 8000h, which corresponds to 0dB gain with mute on.
MUTE
GX3...GX0
0
1111
FUNCTION
+22.5dB gain
0
0000
0dB gain
1
xxxxx
-∞dB gain
Table 9 Record Gain Register Function
GENERAL PURPOSE REGISTER (INDEX 20h)
This register is used to control several miscellaneous functions of the WM9707.
Below is a summary of each bit and its function. Only the 3D, MIX, MS and LPBK bits are supported
by the WM9707. The MS bit controls the Mic selector. The LPBK bit enables loopback of the ADC
output to the DAC input without involving the AC-link, allowing for full system performance
measurements. The function default value is 8000h which is all off.
BIT
POP
FUNCTION
PCM out path and mute, 0 = pre-3D, 1 = post-3D
WM9707
SUPPORT
Yes
ST
Simulated stereo enhancement, on/off 1 = on
No
3D
3D stereo enhancement on/off, 1 = on
Yes
LD
Loudness (bass boost) on/off, 1 = on
No
LLBK
Local loop back - for modem, line codec
No
RLBK
Remote loop back - for modem, line codec
No
MIX
Mono output select 0 = Mix, 1 = Mic
Yes
MS
Mic select 0 = Mic1, 1 = Mic2
Yes
ADC/DAC loopback mode
Yes
LPBK
Table 10 General Purpose Register Function
3D CONTROL REGISTER (INDEX 22h)
This register is used to control the centre and/or depth of the 3D stereo enhancement function built
into of the AC’97 component. Only the depth bits DP0 to 3 have effect in the WM9707.
DP3…DP0
DEPTH
0
0%
1
8
Typical value
15
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POWERDOWN CONTROL/STATUS REGISTER (INDEX 26h)
This read/write register is used to program Powerdown states and monitor subsystem readiness. The
lower half of this register is read only status, a 1 indicating that the subsection is ready. Ready is
defined as the subsection able to perform in its nominal state. When this register is written the bit
values that come in on AC-link will have no effect on read only bits 0 to 7.
When the AC-link Codec Ready indicator bit (SDATA_IN slot 0, bit 15) is a 1 it indicates that the AClink and the WM9707 control and status registers are in a fully operational state. The AC’97 controller
must further probe this Powerdown Control/Status Register to determine exactly which subsections, if
any, are ready.
READ BIT
FUNCTION
REF
VREFs up to nominal level
ANL
Analogue mixers, etc ready
DAC
DAC section ready to accept data
ADC
ADC section ready to transmit data
Table 11 Powerdown Status Register Function
The powerdown modes are as follows. The first three bits are to be used individually rather than in
combination with each other. The last bit PR3 can be used in combination with PR2 or by itself. PR0
and PR1 control the PCM ADCs and DACs only. PR6 is not supported by the WM9707.
WRITE BIT
FUNCTION
PR0
PCM in ADCs and input Mux Powerdown
PR1
PCM out DACs Powerdown
PR2
Analogue mixer Powerdown
(VREF still on)
PR3
Analogue mixer Powerdown (VREF off)
PR4
Digital interface (AC-link) Powerdown
(external clock off)
PR5
Internal clock disable
PR6
HP amp Powerdown – not supported
EAPD
External amplifier Powerdown
Table 12 Powerdown Control Register Function
PR0 = 1
NORMAL
PR1 = 1
ADCs OFF
PR0
PR0 = 0 AND
ADC = 1
PR2 = 1
DACs OFF
PR1
PR1 = 0 AND
DAC = 1
PR4 = 1
ANALOGUE
OFF PR2 OR
PR3
PR2 = 0 AND
ANL = 1
READY = 1
DIGITAL I/F
OFF PR4
SHUT OFF
CODA LINK
WARM
RESET
COLD RESET
DEFAULT
Figure 15 An Example of the WM9707 Powerdown/Powerup Flow
Figure 15 illustrates one example procedure to do a complete Powerdown of the WM9707. From
normal operation sequential writes to the Powerdown Register are performed to Powerdown the
WM9707 a piece at a time. After everything has been shut off (PR0 to PR3 set), a final write (of PR4)
can be executed to shut down the WM9707’s digital interface (AC-link).
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The part will remain in sleep mode with all its registers holding their static values. To wake up the
WM9707, the AC’97 controller will send a pulse on the sync line issuing a warm reset. This will
restart the WM9707’s digital interface (resetting PR4 to 0). The WM9707 can also be woken up with
a cold reset. A cold reset will cause a loss of values of the registers, as a cold reset will set them to
their default states. When a section is powered back on, the Powerdown Control/Status Register
(index 26h) should be read to verify that the section is ready (i.e. stable) before attempting any
operation that requires it.
PR1 = 1
ADCs OFF
PR0
PR2 = 1
DACs OFF
PR1
PR1 = 0 AND
DAC = 1
PR4 = 1
ANALOGUE
OFF PR2
OR PR3
PR2 = 0 AND
ANL = 1
DIGITAL I/F
OFF PR4
SHUT OFF
CODA LINK
WARM RESET
Figure 16 The WM9707 Powerdown/Flow with Analogue Still Alive
Figure 16 illustrates a state when all the mixers should work with the static volume settings that are
contained in their associated registers. This is used when the user could be playing a CD (or external
LINE_IN source) through WM9707 to the speakers but have most of the system in low power mode.
The procedure for this follows the previous except that the analogue mixer is never shut down.
POWERDOWN CONTROL/STATUS REGISTER (INDEX 26h)
Note that in order to go into ultimate low power mode, PR4 and PR5 are required to be set which
turns off the oscillator circuit. Asserting SYNC resets the PR4 and PR5 bit and re-starts the oscillator
in the same was as the AC link is restarted. Note that PR4 is redundant in slave mode.
REVISION 2.1 REGISTERS (INDEX 28h T0 58h)
These registers are specified as to use in Revision 2.1 of the AC’97 specification and have the
following functions on the WM9707:
REGISTER 28h – EXTENDED AUDIO ID
The Extended Audio ID register is a read only register that identifies which extended audio features
are supported (in addition to the original AC’97 features identified by reading the reset register at
index 00h). A non zero value indicates the feature is supported.
DATA BIT
FUNCTION
ANY MODE
VRA
Variable rate audio support
1
DRA
Double rate audio support
0
VRM
Variable rate Mic ADC support
0
CDAC
Centre DAC support
0
SDAC
Surround DAC support
0
LDAC
LFE DAC support
0
AMAP
Slot to front DAC mapping support
0
ID1
Codec configuration – fixed in 9707
0
ID0
Codec configuration – pin 45 value
1 (Inverse of level at pin 45)
Table 13 Extended Audio ID Register
REGISTER 2Ah – EXTENDED AUDIO STATUS AND CONTROL REGISTER
The Extended Audio Status and Control Register is a read/write register that provides status and
control of the extended audio features.
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DATA BIT
VRA
FUNCTION
Enables variable rate audio mode
READ/WRITE
WM9707 SUPPORT
Read/write
Yes
DRA
Enable double rate audio mode
Read/write
No
VRM
Enables variable rate Mic ADC
Read/write
No
CDAC
Indicates centre DAC ready
Read
No
SDAC
Indicates surround DAC ready
Read
No
LDAC
Indicates LFE DAC ready
Read
No
MADC
Indicates Mic ADC ready
Read
No
PRI
Set to turn off centre DAC
Read/write
No
PRJ
Set to turn off surround DACs
Read/write
No
PRK
Set to turn off LFE DACs
Read/write
No
PRL
Set to turn off Mic ADC
Read/write
No
Table 14 Extended Audio Status and Control Register
REGISTER 2Ch TO 32h – AUDIO SAMPLE RATE CONTROL REGISTERS
These registers are read/write registers that are written to, to select alternative sample rates for the
audio PCM converters. Default is the 48ks/s rate. Note that only Revision 2.1 recommended rates
are supported by the WM9707, selection of any other unsupported rates will cause the rate to default
to the nearest supported rate, and the supported rate value to be latched and so read back.
Note that the SPDIF mode only supports 48ks/s rate.
REGISTERS 36h AND 38h – 6 CHANNEL VOLUME CONTROL
These read/write registers control the output volume of the optional four PCM channels. (not
supported by the WM9707)
VENDOR RESERVED REGISTERS (INDEX 5Ah - 7Ah)
These registers are vendor specific. Do not write to these registers unless the Vendor ID register has
been checked first to ensure that the driver knows the source of the AC ‘97 component.
SPDIF DIGITAL AUDIO DATA OUTPUT – (INDEX 5Ch)
The WM9707 provides an SPDIF output. In order to enable this output, bit SPDF in Register 5Ch
should be set. Additionally, a bit SCMS in Register 5Ch may also be set, which sets the copyright
flag in the IEC958 data, allowing serial copy protect mechanisms to be removed.
The WM9707 can be programmed to automute the DACs. By setting the mute bit, the WM9707 will
mute the DACs when it detects a continuous sequence of 1024 zeros.
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VENDOR SPECIFIC GAIN CONTROL REGISTERS – (INDEX 72h)
This register controls the gain and mute functions applied to the mixer path. This PGA is not
accommodated in the Intel specification, but is required in order to allow the option of simultaneous
recording of the mixer output and playback of DAC signals. The function is as per the other mixer
PGA’s. However, the default value of the register is not-muted. If it is not used it will be transparent to
the user.
VENDOR ID REGISTERS (INDEX 7Ch TO 7Eh)
This register is for specific vendor identification if so desired. The ID method is Microsoft’s Plug and
Play Vendor ID code. The first character of that ID is F7 to F0, the second character S7 to S0, and
the third T7 to T0. These three characters are ASCII encoded. The REV7 to REV0 field is for the
Vendor Revision number. In the WM9707 the vendor ID is set to WML3.
Wolfson is a registered Microsoft Plug and Play vendor.
VENDOR ID REGISTERS (INDEX 74h)
This register describes how data is mapped to the AC’97 DACs. Register 74h can be used to change
the incoming DAC data slots that are used by the on-board DACs. This allows software control of
multiple codecs.
SURROUND SOUND
DSS1, DSS0
PCM OUT LEFT
PCM OUT RIGHT
00
3
4
01
7
8
1X
6
9
Table 15 Vendor ID Registers - Reg 74 [1:0]
SURROUND SOUND
ASS1, ASS0
PCM IN LEFT
PCM IN RIGHT
00
3
4
01
7
8
1X
6
9
Table 16 Vendor ID Registers – Reg 74 [9:8]
This register describes how data is mapped onto the AC-link. Register 74h can be used to map ADC
data onto multiple AC-link slots under software control.
This allows the user to connect multiple codecs to a host controller using a single AC-link interface.
The volume control register is still 02h and the rate register is 2Ch. The ID pins have no effect on this
mapping.
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SERIAL INTERFACE REGISTER MAP
The following table shows the function and address of the various control bits that are loaded through
the serial interface during write operations.
Reg Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
efault
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
6150h
Master volume
Mute
X
X
ML4
ML3
ML2
ML1
ML0
X
X
X
MR4
MR3
MR2
MR1
MR0
8000h
04h
LNLVL volume
Mute
X
X
ML4
ML3
ML2
ML1
ML0
X
X
X
MR4
MR3
MR2
MR1
MR0
8000h
06h
Master volume
mono
Mute
X
X
X
X
X
X
X
X
X
X
MM4
MM3
MM2
MM1
MM0
8000h
0Ah
PCBEEP volume
Mute
X
X
X
X
X
X
X
X
X
X
PV3
PV2
PV2
PV0
X
8000h
0Ch
Phone volume
Mute
X
X
X
X
X
X
X
X
X
X
GN4
GN3
GN2
GN1
GN0
8008h
0Eh
Mic volume
Mute
X
X
X
X
X
X
X
X
20dB
X
GN4
GN3
GN2
GN1
GN0
8008h
10h
Line in volume
Mute
X
X
GL4
GL3
GL2
GL1
GL0
X
X
X
GR4
GR3
GR2
GR1
GR0
8808h
12h
CD volume
Mute
X
X
GL4
GL3
GL2
GL1
GL0
X
X
X
GR4
GR3
GR2
GR1
GR0
8808h
14h
Video volume
Mute
X
X
GL4
GL3
GL2
GL1
GL0
X
X
X
GR4
GR3
GR2
GR1
GR0
8808h
16h
Aux volume
Mute
X
X
GL4
GL3
GL2
GL1
GL0
X
X
X
GR4
GR3
GR2
GR1
GR0
8808h
18h
PCM out volume
Mute
X
X
GL4
GL3
GL2
GL1
GL0
X
X
X
GR4
GR3
GR2
GR1
GR0
8808h
1Ah
Rec select
X
X
X
X
X
SL2
SL1
SL0
X
X
X
X
X
SR2
SR1
SR0
0000h
1Ch
Rec gain
Mute
X
X
X
GL3
GL2
GL1
GL0
X
X
X
X
GR3
GR2
GR1
GR0
8000h
20h
General purpose
POP
ST
3D
lD
X
X
MIX
MS
LPBK
X
X
X
X
X
X
X
0000h
22h
3D control
X
X
X
X
X
X
X
X
X
X
X
X
DP3
DP2
DP1
DP0
0000h
24h
Reserved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0000h
26h
Power/down control APD
status
X
PR5
PR4
PR3
PR2
PR1
PR0
X
X
X
X
REF
ANL
DAC
ADC
000Fh
28h
Ext’d audio ID
ID1
ID0
X
X
X
X
Amap Ldac
Sdac Cdac
X
X
VRM
X
DRA
VRA
1001h
X
PRL
PRK
PRJ
PRI
X
00h
Reset
02h
2Ah
Ext’d audio stat/ctrl
Madc Ldac
Sdac Cdac
X
X
VRM
X
DRA
VRA
0000h
2Ch
Front DAC rate
SR15 SR14 SR13 SR12 SR11 SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
BB80h
32h
Audio ADC rate
SR15 SR14 SR13 SR12 SR11 SR10
SR2
SR1
SR0
BB80h
5Ch
Vendor specific
SCMS SPDF
Mute
1000h
72h
Front mixer volume
74h
Surround sound
7Ah
Vendor reserved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0000h
7Ch
Vendor ID1
F7
F6
F5
F4
F3
F2
F1
F0
S7
S6
S5
S4
S3
S2
S1
S0
574Dh
7Eh
Vendor ID2
T7
T6
T5
T4
T3
T2
T1
T0
Rev0
4C03h
REVISION
SR9
SR8
SR7
SR6
SR5
SR4
SR3
X
X
X
X
X
X
X
X
X
GL1
GL0
X
X
X
GR4
GR3
GR2
ASS1 ASS0
X
X
X
X
X
X
Mute
X
X
GL4
GL3
GL2
X
X
X
X
X
X
GR1
GR0
0808h
DSS1 DSS0
0000h
Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1
Table 17 Serial Interface Register Map Description
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RECOMMENDED EXTERNAL COMPONENTS
DVDD
AVDD
1
9
C1
4
C2
7
DVDD1
AVDD1
DVDD2
AVDD2
DVSS1
AVSS1
DVSS2
AVSS2
25
38
C3
C4
26
42
DGND
MIXER
INPUTS
C5
12
C6
13
C7
14
C8
15
C9
16
C10
17
C11
18
C12
19
C13
20
C14
21
C15
22
C16
23
C17
24
AGND
PCBEEP
PHONE
VREF
AUXL
VREFOUT
C18
VIDEOR
CAP2
AGND
CDR
AGND
MIC1
CX3D1
MIC2
CX3D2
33
34
C23
C24
LINEINL
LINEINR
AGND
LNLVLOUTL
CID
35
+ C25
36
+ C26
37
+ C27
39
+ C28
41
+ C29
STEREO OUTPUT
MONO OUTPUT
LINE LEVEL STEREO
AVDD
5
6
8
10
11
SDATAOUT
SPDIF ENABLE 44
BITCLK
SDATAIN
SPDIF
SYNC
EAPD
48
47
RESETB
XTLIN
Notes:
1. C1 to C24 should be as close to
WM9707 as possible.
2. AGND and DGND should be
connected as close to WM9707
as possible.
C22 +
C21
WM9707
CDGND
LNLVLOUTR
AC-LINK
C20 +
32
CDL
MONOOUT
AVSS
C19
VIDEOL
LINEOUTL
45
28
AUXR
LINEOUTR
MASTER/
SLAVE
SELECT
27
XTLOUT
2
3
XT
C31
C30
DGND
Figure 17 External Components Diagram
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RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1 to C4
10nF
De-coupling for DVDD and AVDD
C5 to C17
470nF
AC coupling capacitors for setting DC level of analogue inputs to VCAP1.
Value chosen to give corner frequency below 20Hz for min 10K input impedance.
C18
1µF
C19
0.1µF
Reference de-coupling capacitors for ADC, DAC, Mixer and CAP2 references.
Ceramic type or similar.
C20
10µF
C21
0.1µF
C22
10µF
C23
100nF
3D low pass filter. This value sets nominal 100Hz.
C24
47nF
3D high pass filter. This value sets nominal 1kHz.
C25 to C29
10µF
Output AC coupling caps to remove VREF DC level from outputs.
C30 and C31
22pF
Optional capacitors for better crystal frequency stability.
XT
24.576 MHz
AC’97 master clock frequency. A bias resistor is not required, but if connected will not
affect operation if value is large (above 1MΩ).
Table 18 External Component Values
Figure 18 Suggested SPDIF Output Circuit
RECOMMENDATIONS FOR 3.3V OPERATION
The device’s performance with AVDD = 3.3V is shown in Electrical Characteristics.
In 3.3V analogue operation, mid-rail reference scales to 1.5V. All ADC and DAC references are 3/5ths
of their nominal 5V value. Input and output signals that are 1Vrms in 5V applications, scale to
660mVrms in 3.3V applications. If 1Vrms output is required, the mixer gain adjust PGAs need to be
increased by 3 times 1.5dB steps.
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WM9707
Advanced Information
PACKAGE DIMENSIONS
DM003.B
FT: 48 PIN TQFP (7 x 7 x 1.4 mm)
b
e
36
25
37
24
E1
48
E
13
1
12
θ
D1
c
D
A A2
L
A1
-Cccc C
Symbols
A
A1
A2
b
c
D
D1
E
E1
e
L
MIN
----0.05
1.35
0.17
0.09
Dimensions
(mm)
NOM
--------1.40
0.22
----9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.50 BSC
0.60
o
3.5
MAX
1.60
0.15
1.45
0.27
0.20
θ
0.45
o
0
ccc
Tolerances of Form and Position
0.08
REF:
SEATING PLANE
0.75
o
7
JEDEC.95, MS-026
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MS-026, VARIATION = BBC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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